DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on July 6, 2026.
Claims 13-24 are amended. No claims are canceled. No claims are added.
Applicant’s amendments to the drawings and specification submitted on July 6, 2026, are acknowledged and objections to the drawings and specification are withdrawn.
Applicant’s amendments to the claims overcome the 112(b) rejection set forth in the previous office action and therefore the 112(b) rejection is withdrawn.
Response to Arguments
3. Applicant's arguments filed July 6, 2026, have been fully considered but they are not persuasive.
Applicant submits on page 3 Lim’s (US 6339238 B1) FeFET does not disclose a “separate” ferroelectric capacitance connected between the front-gate electrode and the second contact of the second contact pair as required by amended claim 13. However, Lim shows in FIG. 37 the ferroelectric capacitance (572; Col. 17, ll. 19-20) is electrically arranged or connected between the front-gate electrode (582) of the transistor and the second contact of the second contact pairs (584 – i.e., the ferroelectric capacitance 572 is shown connected between 582 and 584) of each of the at least two memory cells, as recited in amended claim 13. Therefore, Applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 13-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim, et al (US 6339238 B1), hereinafter Lim.
Regarding independent claim 13, Lim teaches a resistor network having at least two memory cells (FIG. 40, 804, 905) for storing one resistance characteristic value (FIGS. 3-4; Col. 8, ll. 33-39 teach the polarization of “on” and “off” states) in each of the at least two memory cells, which each have a transistor configured as a field-effect transistor (Col. 17, ll. 8-9 teaches “FIG. 37 shows an equivalent circuit the FET 40 of FIG. 1”), a ferroelectric capacitance (FIG. 37, 572; Col. 17, ll. 19-20) and a first contact pair (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65),
whereas source and drain electrodes of the transistor form first and second contacts of the first contact pairs of each of the at least two memory cells (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65),
whereas the first contact pairs of each of the at least two memory cells are configured to provide an electrical resistance corresponding to a stored resistance characteristic value in at least one operating mode (Col. 3, l. 62 – Col. 4, l. 2 teach “reading a ferroelectric memory including a plurality of ferroelectric FETs, the method comprising the steps of: sensing a first current through an electrical element of a first one of the FETs; sensing a second current through an electrical element of a second one of the FETs, the first current being greater than the second current; and associating a first logic state with the first current and a second logic state with the second current,” which indicates different resistances associated with each state), wherein first contacts of the first contact pairs of each of the at least two memory cells are directly connected to one another (FIG. 40, source contacts of cells 804 and 905 are coupled to each other and bit line B0/820) and second contacts of the first contact pairs of each of the at least two memory cells are electrically independent of one another (FIG. 40, drain contact of cell 804 is connected to drain line D0 and drain contact of cell 905 is connected to drain line D1, which are shown electrically independent from one another), characterized in that the at least two memory cells each have a second contact pair which is electrically independent of the first contact pair (FIG. 1, “second contact pair”, front gate contact 60 and back gate contact 66, are shown electrically independent of “first contact pair”, source contact 62 and drain contact 64),
whereas a back-gate electrode of the transistor forms the first contact of the second contact pairs of each of the at least two memory cells (FIG. 37, 584),
whereas the ferroelectric capacitance (FIG. 37, 572; Col. 17, ll. 19-20) is electrically arranged or connected between the front-gate electrode (FIG. 37, 582) of the transistor and the second contact of the second contact pairs (FIG. 37, 584 – i.e., the ferroelectric capacitance 572 is shown connected between 582 and 584) of each of the at least two memory cells, or connected in series,
whereas the second contact pairs of each of the at least two memory cells are arranged in such a way that the stored electrical resistance characteristic value of at least one of the at least two memory cell cells can be reversibly changed by suitable electrical signals via this second contact pair (Col. 18, l. 40 – Col. 19, l. 26 and Tables 2-3 discuss “writing” opposite polarities via “second contact pair” gate contact 60 (front gate) and substrate (back gate) contact 66).
Regarding claim 14, Lim teaches the limitations of claim 13.
Lim further teaches the first contacts of the second contact pairs of each of the at least two memory cells are directly connected to each other (FIG. 40, substrate (back gate) contacts of cells 804 and 905 are coupled to each other and SB0/840) and second contacts of the second contact pairs of each of the at least two memory cells are independent of each other (FIG. 40, gate contact of cell 804 is connected to W0/816 and gate contact of cell 905 is connected to W1/916, which are shown electrically independent of one another).
Regarding claim 15, Lim teaches the limitations of claim 13.
Lim further teaches at least one third memory cell (FIG. 40, e.g., cell 904) for storing a resistance characteristic value (FIGS. 3-4; Col. 8, ll. 33-39 teach the polarization of “on” and “off” states), comprising a first contact pair (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65) configured to provide an electrical resistance corresponding to a stored resistance characteristic value (Col. 3, l. 62 – Col. 4, l. 2 teach “reading a ferroelectric memory including a plurality of ferroelectric FETs, the method comprising the steps of: sensing a first current through an electrical element of a first one of the FETs; sensing a second current through an electrical element of a second one of the FETs, the first current being greater than the second current; and associating a first logic state with the first current and a second logic state with the second current”, which indicates different resistances associated with each state), wherein a first contact of the first contact pair of the at least one third memory cell is independent of the first contacts of the first contact pairs of each of the at least two memory cells (FIG. 40, e.g., source contact of “third” cell 904 is connected to B1/920 while source contacts of “first” and “second” cells 804 and 905 are coupled to each other and bit line B0/820, making the first contact of the first contact pair of the third cell independent from those of the first and second cells) and wherein a second contact of the first contact pair of the at least third memory cell is directly connected to the second contact of the first contact pair of one of the at least two memory cells (FIG. 40, drain contact of “third” cell 904 is connected to drain line D0 and drain contact of “first” cell 804) and is independent of the second contacts of the first contact pairs of each of the other of the at least two memory cells (FIG. 40, drain contact of “third” cell 904 is connected to drain line D0 while drain contact of “second” cell 905 is connected to drain line D1, the drain lines/contacts shown electrically independent from one another).
Regarding claim 16, Lim teaches the limitations of claim 13.
Lim further teaches at least one of the at least two memory cells comprises at least one transistor configured as a ferroelectric field effect transistor (Abstract).
Regarding claim 17, Lim teaches the limitations of claim 16.
Lim further teaches the first contact pair of the one of the at least two memory cells that comprises the at least one transistor is connected to a source electrode and a drain electrode of the at least one transistor (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65).
Regarding claim 18, Lim teaches the limitations of claim 16.
Lim further teaches the second contact pair of the one of the at least two memory cells that comprises the at least one transistor is connected to a front gate electrode of the at least one transistor and a back gate electrode of the at least one transistor (FIG. 1, front gate contact 60 and back gate contact 66; Col. 7, ll. 64-66).
Regarding claim 19, Lim teaches the limitations of claim 13.
Lim further teaches the at least two memory cells are each configured to either provide or block the electrical resistance corresponding to the stored resistance characteristic value via the first contact pair depending on a voltage applied across the second contact pair (It appears in p. 8, ll. 1-7 of the present application that “blocking” the resistance “provided” by the cell is to put the cell into a state in which the cell resistance is at least ten times the maximum resistance provided by the cell in an “unlocked” state (p.8, l. 5), and that this is done by manipulating the voltages applied to the second pair of contacts (p.8, ll. 8-18). Lim shows in FIGS. 20-23 the effect of adjusting the voltages applied to the second pair of contacts. For example, if Vg is 0V, the resistance of the cell will be several orders of magnitude higher when the substrate voltage is 0.3V (FIG. 22) than when the substrate voltage is 0.8V (FIG. 23); Col. 13, l. 56 – Col. 14, l. 14).
Regarding claim 20, Lim teaches the limitations of claim 13.
Lim further teaches the at least two memory cells are each configured to be switchable between at least three different memory states by the suitable electrical signals via the second contact pair (It appears in p. 3, ll. 12-35 of the present application that memory states may be assigned to different resistances provided by the cell. Lim shows in FIGS. 13-14 that the gate voltage at a specific Vds modifies the Ids at that gate voltage (applied to the “first contact” of the “second contact pair”). Each curve, therefore, indicates a different resistance (“state”) provided by the cell as controlled by the gate voltage for a given Vds. Therefore, Lim’s resistances as determined by gate voltage appear to equate to the “states” described in the present application.)
Regarding claim 21, Lim teaches the limitations of claim 13.
Lim further teaches the at least two memory cells are arranged in rows and columns of a grid (FIG. 40, cells 804, 904, 905, and 906 arranged in rows and columns of a grid; Col. 5, ll. 11-16).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lim, et al (US 6339238 B1), hereinafter Lim, in view of Nikonov, et al (US 20200194049 A1), hereinafter Nikonov.
Regarding claim 22, Lim teaches the limitations of claim 13.
Lim further teaches an integrated circuit (FIG. 1; Col. 8, ll. 8-9).
Lim does not teach the integrated circuit comprises an analog convolutional neural network layer or an analog matrix multiplier, the integrated circuit comprising at least one resistor network according to claim 13.
Nikonov teaches an integrated circuit (e.g., FIG. 3; ¶ [0021]) comprises an analog convolutional neural network layer or an analog matrix multiplier (¶ [0016] teaches “synapses are elements of the neural gate executing analog multiplication”), said circuit comprising at least one resistor network according to claim 13 (FIG. 4; ¶ [0024] teaches “A ferroelectric memory cell disclosed herein includes a ferroelectric FET”).
Because Nikonov implements neural synapses and analog multiplication with ferroelectric FETs, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the ferroelectric FET of Lim with the ferroelectric FET of Nikonov to yield predictable results. See MPEP § 2143(I)(B).
Regarding claim 23, Lim as modified by Nikonov teaches the limitations of claim 22.
Lim further teaches a first selection unit (FIG. 38, Gate Row Address 825) respectively connected to the first contacts of the second contact pairs of each of the at least two memory cells and adapted to connect, depending on a specification, a subset of the first contacts to a first activation contact and to connect a complementary set of the first contacts to a first deactivation contact (e.g., Col. 7, ll. 25-28 teach “FIG. 40 illustrates the signals applied to the terminals of the selected and non-selected ferroelectric FETs in the memory array of FIG. 38 when writing ‘1’ to a selected ferroelectric FET”; Col. 19, ll. 14-17 teach “The writing of a logic "1" to the first cell 804, i.e. the cell in the zeroth row and zeroth column is shown in FIG. 40 and is summarized in the writing ‘1’ portion of Table 2”; that is, the zeroth row subset is “activated” and the first row complementary set is “deactivated”).
8. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lim, et al (US 6339238 B1), hereinafter Lim, in view of Nikonov, et al (US 20200194049 A1), hereinafter Nikonov, and further in view of Fackenthal (US 20180101204 A1).
Regarding claim 24, Lim as modified by Nikonov teaches the limitations of claim 22.
Lim does not teach at least one temperature sensor configured to monitor a temperature of the at least one resistor network, and at least one actuator configured to adapt stored resistance characteristic values of the at least two memory cells of the at least one resistor network to a changed temperature.
Fackenthal teaches at least one temperature sensor (FIG. 2, 255) configured to monitor a temperature of the resistor network (Abstract), and at least one actuator configured to adapt stored resistance characteristic values of the memory cells of the resistor network to a changed temperature (In p. 12, ll. 9-22, of the present application, it appears the actual contents of the cells are not changed, but rather the reading or interpretation of the contents is adapted based on temperature. Fackenthal teaches in the Abstract, “A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature.” Fackenthal further teaches “A ferroelectric memory device may perform a temperature update to update voltages, power supplies, or other operating characteristics that may change with temperature or other operating parameters” (¶ [0013]), “a reference voltage may be changed according to different temperatures” (¶ [0014]), “at cold temperatures, the voltage of the cell may be increased based on at least one component or operation, while at hot temperatures, the voltage of the cell may be decreased based on at least one component or operation” (¶ [0015]), etc.).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Fackenthal into the method of Lim to include “reconfiguring” the memory based at least in part on a sampled temperature. The ordinary artisan would have been motivated to modify Lim in the above manner for the purpose of maximizing performance and minimizing power (Fackenthal ¶ [0015]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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