DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on November 14, 2022 has been fully considered by the examiner.
Specification
3. The disclosure is objected to because of the following informalities.
The Specification Title (“Resistor Network”) is different from the Application Title (“RESISTANCE NETWORK HAVING FOUR CONTACTS PER MEMORY CELL”). Examiner suggests using the more descriptive Application Title.
Appropriate correction is required.
Drawings
4. The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
Claim Objections
5. Claim 20 is objected to because of the following informalities.
Claim 20, lines 1-2, recite the limitation, “at least the two memory cells.” Because claim 13, line 1, recites, “at least two memory cells,” Examiner believes “at least the two memory cells” in claim 20 is a typographical error and should recite, “the at least [[the]] two memory cells.”
6. Claim 23 is objected to because of the following informalities.
Claim 23, lines 2-3, recite “the second contact pair of the memory cells (200)”. “(200)” appears to be extraneous text, likely referencing drawings that have not been provided.
In addition, “second contact pair” is applied to a plurality of memory cells. Therefore, Examiner believes line 2 should recite, “the first contacts of the second contact [[pair]] pairs of the memory cells.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8. Claims 13-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the two memory cells” in lines 5-7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the two memory cells” shall be interpreted as “two memory cells of the at least two memory cells,” antecedent basis for which is provided by “at least two memory cells” in line 1.
Claim 13 recites the limitation “the stored resistance characteristic value” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. It is also unclear if “the stored resistance characteristic value” in lines 3-4 refers to the “one resistance characteristic value” in line 2 or a stored resistance characteristic value specific to “at least one operating mode” (see line 4). Accordingly, the meaning of the limitations is indefinite. For the purpose of this action, “the stored resistance characteristic value in least one operating mode” in lines 3-4 shall be interpreted as “[[the]] a stored resistance characteristic value in at least one operating mode.”
Claim 13 recites the limitation “the respective memory cell” in line 10. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the respective memory cell” shall be interpreted as “[[the]] respective memory [[cell]] cells.”
Claim 13 recites the limitation “the respective first contact pair” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the respective first contact pair” shall be interpreted as “[[the]] respective first contact [[pair]] pairs.”
Claim 13 recites the limitation, “storing in each case” in line 1. The meaning of this limitation is not certain. It is possible “each case” is intended to reference each instance of the at least two memory cells. However, the specification describes “cases,” for example, as the configuration of the resistor network (page 10, lines 15-20) and the type of transistor used as a memory cell (page 16, lines 1-3). It is also possible “each case” alludes to each use case (see “operating mode” in line 4 of the claim). Accordingly, the meaning of the limitations is indefinite. For the purpose of this action, “storing in each case” shall be interpreted as “storing in each cell.” Claims 14-24 depend on claim 13.
9. Claim 17 recites the limitation “the transistor” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the transistor” shall be interpreted as “the at least one transistor,” which finds antecedent basis in claim 16.
10. Claim 18 recites the limitation “the transistor” in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the transistor” shall be interpreted as “the at least one transistor,” which finds antecedent basis in claim 16.
11. Claim 19 recites the limitation “the memory cells” in line 1, which finds antecedent basis in claim 13, lines 7-8. However, it is unclear if “the memory cells” refers to the set of “at least two memory cells” in claim 1, line 1, or “the two memory cells” in claim 1, line 5. Accordingly, the meaning of the limitation is indefinite. For the purpose of this action, “the memory cells” shall be interpreted as “the at least two memory cells.”
12. Claim 20 recites the limitation “suitable electrical signals” in line 3. Antecedent basis for “suitable electrical signals” has already been established in claim 13, line 11. For the purpose of this action, “suitable electrical signals” shall be interpreted as “the suitable electrical signals.”
13. Claim 21 recites the limitation, “the stored resistance characteristic value,” which finds antecedent basis in claim 13, lines 3-4. However, in claim 21, “the stored resistance characteristic value” appears to refer to “a plurality of further memory cells” (see lines 1-2), not the “at least two memory cells” of claim 13, line 1. Therefore, for the purpose of this action, “the stored resistance characteristic value” shall be interpreted as “a [[the]] stored resistance characteristic value.”
Claim 21 recites the limitation “the two memory cells” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the two memory cells” shall be interpreted as “two memory cells of the at least two memory cells,” antecedent basis for which is provided by “at least two memory cells” in claim 13, line 1.
14. Claim 22 recites the limitation “said circuit” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “said circuit” shall be interpreted as “said integrated circuit.”
15. Claim 23 recites the limitation “in response to a specification” in line 5. A typical understanding of “specification” may be a detailed description of the design and materials used to make something or requirements for the operation of a device. However, on page 20, line 26, through page 21, line 6, of the specification, “specification” appears to be part of a system or device (element 342) and may be generated by an actuator unit (element 340). In this context, and in the absence of the drawings, the meaning of “in response to a specification” is indefinite.
16. Claim 24 recites the limitation, “the resistor network,” which finds antecedent basis in claim 13, lines 3-4. However, in claim 24, based on the context of “the integrated circuit according to claim 22,” “the resistor network” appears to refer to the “at least one resistor network” of claim 22, not the “resistor network” of claim 13, though related. Therefore, for the purpose of this action, “the resistor network” shall be interpreted as “the at least one resistor network.”
Claim 24 recites the limitation “the memory cells of the resistor network” in line 4, which finds antecedent basis in claim 13, lines 7-8. However, it is unclear if “the memory cells” refers to the set of “at least two memory cells” in claim 13, line 1, “the two memory cells” in claim 1, line 5, or memory cells of the at least one resistor network (see claim 22). Accordingly, the meaning of the limitations is indefinite. For the purpose of this action, “the memory cells” shall be interpreted as “[[the]] memory cells of the at least one resistor network.”
Claim Rejections - 35 USC § 102
17. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
18. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
19. Claims 13-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim, et al (US 33 B1), hereinafter Lim.
Regarding independent claim 13, Lim teaches a resistor network having at least two memory cells (FIG. 40, 804, 905) for storing in each case one resistance characteristic value (FIGS. 3-4; Col. 8, ll. 33-39 teach the polarization of “on” and “off” states), which each have a first contact pair (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65) which is configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode (Col. 3, l. 62 – Col. 4, l. 2 teach “reading a ferroelectric memory including a plurality of ferroelectric FETs, the method comprising the steps of: sensing a first current through an electrical element of a first one of the FETs; sensing a second current through an electrical element of a second one of the FETs, the first current being greater than the second current; and associating a first logic state with the first current and a second logic state with the second current,” which indicates different resistances associated with each state) wherein first contacts of the respective first contact pair of the two memory cells are directly connected to one another (FIG. 40, source contacts of cells 804 and 905 are coupled to each other and bit line B0/820) and second contacts of the respective first contact pair of the two memory cells are electrically independent of one another (FIG. 40, drain contact of cell 804 is connected to drain line D0 and drain contact of cell 905 is connected to drain line D1, which are shown electrically independent from one another), characterized in that the memory cells each have a second contact pair which is electrically independent of the first contact pair (FIG. 1, “second contact pair”, front gate contact 60 and back gate contact 66, are shown electrically independent of “first contact pair”, source contact 62 and drain contact 64) and which is arranged in such a way that the stored electrical resistance characteristic value of the respective memory cell can be reversibly changed by suitable electrical signals via this second contact pair (Col. 18, l. 40 – Col. 19, l. 26 and Tables 2-3 discuss “writing” opposite polarities via “second contact pair” gate contact 60 (front gate) and substrate (back gate) contact 66).
Regarding claim 14, Lim teaches the limitations of claim 13.
Lim further teaches the first contacts of the respective second contact pair of the two memory cells are directly connected to each other (FIG. 40, substrate (back gate) contacts of cells 804 and 905 are coupled to each other and SB0/840) and second contacts of the respective second contact pair of the two memory cells are independent of each other (FIG. 40, gate contact of cell 804 is connected to W0/816 and gate contact of cell 905 is connected to W1/916, which are shown electrically independent of one another).
Regarding claim 15, Lim teaches the limitations of claim 13.
Lim further teaches at least one third memory cell (FIG. 40, e.g., cell 904) for storing a resistance characteristic value (FIGS. 3-4; Col. 8, ll. 33-39 teach the polarization of “on” and “off” states), comprising a first contact pair (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65) configured to provide an electrical resistance corresponding to the stored resistance characteristic value (Col. 3, l. 62 – Col. 4, l. 2 teach “reading a ferroelectric memory including a plurality of ferroelectric FETs, the method comprising the steps of: sensing a first current through an electrical element of a first one of the FETs; sensing a second current through an electrical element of a second one of the FETs, the first current being greater than the second current; and associating a first logic state with the first current and a second logic state with the second current”, which indicates different resistances associated with each state), wherein a first contact of the first contact pair of the third memory cell is independent of the first contacts of the first contact pair of the two memory cells (FIG. 40, e.g., source contact of “third” cell 904 is connected to B1/920 while source contacts of “first” and “second” cells 804 and 905 are coupled to each other and bit line B0/820, making the first contact of the first contact pair of the third cell independent from those of the first and second cells) and wherein a second contact of the first contact pair of the third memory cell is directly connected to the second contact of the first contact pair of one of the two memory cells (FIG. 40, drain contact of “third” cell 904 is connected to drain line D0 and drain contact of “first” cell 804) and is independent of the second contact of the first contact pair of the other of the two memory cells (FIG. 40, drain contact of “third” cell 904 is connected to drain line D0 while drain contact of “second” cell 905 is connected to drain line D1, the drain lines/contacts shown electrically independent from one another).
Regarding claim 16, Lim teaches the limitations of claim 13.
Lim further teaches at least one of the memory cells comprises at least one transistor configured as a ferroelectric field effect transistor (Abstract).
Regarding claim 17, Lim teaches the limitations of claim 16.
Lim further teaches the first contact pair is connected to a source electrode and a drain electrode of the transistor (FIGS. 1-2, source 42 (contact 62) and drain 44 (contact 64); Col. 7, ll. 52-65).
Regarding claim 18, Lim teaches the limitations of claim 16.
Lim further teaches the second contact pair is connected to a front gate electrode of the transistor and a back gate electrode of the transistor (FIG. 1, front gate contact 60 and back gate contact 66; Col. 7, ll. 64-66).
Regarding claim 19, Lim teaches the limitations of claim 13.
Lim further teaches the memory cells are each configured to either provide or block the electrical resistance corresponding to the stored resistance characteristic value via the first contact pair depending on a voltage applied across the second contact pair (It appears in p. 8, ll. 1-7 of the present application that “blocking” the resistance “provided” by the cell is to put the cell into a state in which the cell resistance is at least ten times the maximum resistance provided by the cell in an “unlocked” state (p.8, l. 5), and that this is done by manipulating the voltages applied to the second pair of contacts (p.8, ll. 8-18). Lim shows in FIGS. 20-23 the effect of adjusting the voltages applied to the second pair of contacts. For example, if Vg is 0V, the resistance of the cell will be several orders of magnitude higher when the substrate voltage is 0.3V (FIG. 22) than when the substrate voltage is 0.8V (FIG. 23); Col. 13, l. 56 – Col. 14, l. 14).
Regarding claim 20, Lim teaches the limitations of claim 13.
Lim further teaches at least the two memory cells are each configured to be switchable between at least three different memory states by suitable electrical signals via the respective second contact pair (It appears in p. 3, ll. 12-35 of the present application that memory states may be assigned to different resistances provided by the cell. Lim shows in FIGS. 13-14 that the gate voltage at a specific Vds modifies the Ids at that gate voltage (applied to the “first contact” of the “second contact pair”). Each curve, therefore, indicates a different resistance (“state”) provided by the cell as controlled by the gate voltage for a given Vds. Therefore, Lim’s resistances as determined by gate voltage appear to equate to the “states” described in the present application.)
Regarding claim 21, Lim teaches the limitations of claim 13.
Lim further teaches a plurality of further memory cells for storing resistance characteristics, each having a first contact pair configured to provide an electrical resistance corresponding to the stored resistance characteristic value in at least one operating mode and being arranged together with the two memory cells in rows and columns of a grid (FIG. 40, cells 804, 904, 905, and 906 arranged in rows and columns of a grid; Col. 5, ll. 11-16).
Claim Rejections - 35 USC § 103
20. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
21. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
23. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
24. Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lim, et al (US 6339238 B1), hereinafter Lim, in view of Nikonov, et al (US 20200194049 A1), hereinafter Nikonov.
Regarding claim 22, Lim teaches the limitations of claim 13.
Lim further teaches an integrated circuit (FIG. 1; Col. 8, ll. 8-9).
Lim does not teach the integrated circuit comprises an analog convolutional neural network layer or an analog matrix multiplier, said circuit comprising at least one resistor network according to claim 13.
Nikonov teaches an integrated circuit (e.g., FIG. 3; ¶ [0021]) comprises an analog convolutional neural network layer or an analog matrix multiplier (¶ [0016] teaches “synapses are elements of the neural gate executing analog multiplication”), said circuit comprising at least one resistor network according to claim 13 (FIG. 4; ¶ [0024] teaches “A ferroelectric memory cell disclosed herein includes a ferroelectric FET”).
Because Nikonov implements neural synapses and analog multiplication with ferroelectric FETs, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the ferroelectric FET of Lim with the ferroelectric FET of Nikonov to yield predictable results. See MPEP § 2143(I)(B).
Regarding claim 23, Lim as modified by Nikonov teaches the limitations of claim 22.
Lim further teaches a first selection unit (FIG. 38, Gate Row Address 825) respectively connected to the first contacts of the second contact pair of the memory cells and adapted to connect a subset of the first contacts to a first activation contact and to connect a complementary set of the first contacts to a first deactivation contact in response to a specification (e.g., Col. 7, ll. 25-28 teach “FIG. 40 illustrates the signals applied to the terminals of the selected and non-selected ferroelectric FETs in the memory array of FIG. 38 when writing ‘1’ to a selected ferroelectric FET”; Col. 19, ll. 14-17 teach “The writing of a logic "1" to the first cell 804, i.e. the cell in the zeroth row and zeroth column is shown in FIG. 40 and is summarized in the writing ‘1’ portion of Table 2”; that is, the zeroth row subset is “activated” and the first row complementary set is “deactivated”).
25. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lim, et al (US 6339238 B1), hereinafter Lim, in view of Nikonov, et al (US 20200194049 A1), hereinafter Nikonov, and further in view of Fackenthal (US 20180101204 A1).
Regarding claim 24, Lim as modified by Nikonov teaches the limitations of claim 22.
Lim does not teach at least one temperature sensor configured to monitor a temperature of the resistor network, and at least one actuator configured to adapt stored resistance characteristic values of the memory cells of the resistor network to a changed temperature.
Fackenthal teaches at least one temperature sensor (FIG. 2, 255) configured to monitor a temperature of the resistor network (Abstract), and at least one actuator configured to adapt stored resistance characteristic values of the memory cells of the resistor network to a changed temperature (In p. 12, ll. 9-22, of the present application, it appears the actual contents of the cells are not changed, but rather the reading or interpretation of the contents is adapted based on temperature. Fackenthal teaches in the Abstract, “A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature.” Fackenthal further teaches “A ferroelectric memory device may perform a temperature update to update voltages, power supplies, or other operating characteristics that may change with temperature or other operating parameters” (¶ [0013]), “a reference voltage may be changed according to different temperatures” (¶ [0014]), “at cold temperatures, the voltage of the cell may be increased based on at least one component or operation, while at hot temperatures, the voltage of the cell may be decreased based on at least one component or operation” (¶ [0015]), etc.).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Fackenthal into the method of Lim to include “reconfiguring” the memory based at least in part on a sampled temperature. The ordinary artisan would have been motivated to modify Lim in the above manner for the purpose of maximizing performance and minimizing power (Fackenthal ¶ [0015]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827