DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 are rejected under AIA 35 U.S.C. 103 as being unpatentable over US 2007/0289127 to Hurwitz hereinafter “Hurwitz(1)” in view of US 2013/0344628 to Hurwitz hereinafter “Hurwitz(2)” and US 2006/0131176 to Hsu.
As per claim 7, as best understood, Hurwitz(1) discloses A manufacturing method of a multilayer substrate, comprising:
S100: selecting an initial layer (see copper base 10 in Fig 3(a)), and manufacturing a first line layer (see layer comprising photoresist 24 and copper feature layer 22 in Fig 3(i)) with a plurality of first line patterns (see copper feature layer 22 including 4 line patterns each formed over the barrier layer 14 in Fig 3(c-i)) on the initial layer;
S200: manufacturing a first through hole layer (see layer comprising photoresist 24 and vias 25 and 26 in Fig 3(j)) on the initial layer and the first line layer, wherein the first through hole layer comprises a plurality of first through hole pillars (see central portion of the copper feature layer 22 formed over the central region 18 in Fig 3(g-j); also see below annotated Fig 3(ah) that specifically points out the first and second through hole pillars) and a plurality of second through hole pillars (see vias 25 and 26 in Fig 3(g-j); also see annotated Fig 3(ah) that specifically points out the first and second through hole pillars), the first through hole pillar is arranged in a trench provided between adjacent first line patterns (see central portion of copper feature layer 22 formed over the central region 18 formed in a trench of the photoresist 24 within the first line pattern provided between adjacent first line patterns of the copper feature layer 22 in Fig 3(g-j); also see annotated Fig 3(ah) that specifically points out the first and second through hole pillars), and each of the plurality of second through hole pillars is arranged on a respective one of the first line patterns (see Fig 3(g-j) that shows that the vias 25 and 26 are formed over the line patterns of the copper feature layer 22; also see annotated Fig 3(ah) that specifically points out the first and second through hole pillars);
S300: laminating a dielectric material (see insulating material 28 in Fig 3(l)) on the first through hole layer to obtain a semi-stack, and thinning the semi-stack to expose end portions of the first through hole pillar and the plurality of second through hole pillars (see Fig 3(m));
S400: separating the semi-stack from the initial layer (see Fig 3(ao) that shows an optional step of removing the copper base 10);
S500: selecting the semi-stack as a new initial layer, and repeating S100, S200, and S300 to form a plurality of layers (see Fig 3(o-ah)), wherein the first through hole pillar of the semi-stack of each layer is connected in cascade with the first through hole pillar of the semi-stack of a previous layer, and the plurality of second through hole pillars of the semi-stack of each layer is connected with the first line pattern of the semi-stack of next layer (see below annotated Fig 3ah that shows all of the first through hole pillars are connected in cascade and all of the second through hole pillars are connected in cascade); and
S600: manufacturing a second line layer (see layer comprising soldermask 56 and terminations 58 in Fig 3(ah)) with a second line pattern (see terminations 58 in Fig 3(ah)) on an outer surface of the semi-stack of a last layer, wherein the second line pattern includes a public line and a transmission line (see terminations 58 in Fig 3(ah), wherein the public line can be the central terminations 58 connected to the first through hole pillars, and the transmission line can the side terminations 58 connected to the second through hole pillars; Para 0114; also see below annotated Fig 3(ah) that specifically points out the first and second through hole pillars), the plurality of first through hole pillars of the semi-stack of the last layer is connected with the public and the plurality of second through hole pillars of the semi-stack of the last layer is connected with the transmission line (see below annotated Fig 3(ah)).
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As per claim 7, Hurwitz(1) discloses the elements of the current invention as detailed above with respect to claim 7. Hurwitz(1) further discloses that the first through hole pillar (i.e. the conductors formed over the central region 18) and the second through hole pillars (i.e. the conductors formed over the barrier layer 14 on the copper base 10) of each layer are aligned with each other respectively, but does not explicitly disclose that the first through hole pillar or the second through hole pillars of a specific layer are used as a positioning mark for positioning further layers. However, it would have been obvious choice for one of ordinary skill in the art to choose to use the through hole pillars as positioning marks for alignment as the through hole pillars would be easily identifiable and would ensure the proper positioning of the through hole pillars of the further layers as would be generally understood by one of ordinary skill in the art.
Hurwitz(2) discloses a similar manufacturing method of a multilayer substrate wherein the ends of the via posts (see via posts 118 in Fig 1 and/or via posts 410 in Fig 4) are used as registration marks for aligning subsequent layers (see step 6g in Fig 6; Abstract; Para 0082-0083, 0085 , and 0087-0088).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the disclosure of Hurwitz(1) as to specifically use the end portions of at least one of the through hole pillars as a positioning mark for alignments as taught by Hurwitz(2). One of ordinary skill in the art would recognize that the choice of what to use as a referencing mark for alignment purposes would be within the skill of ordinary skill in the art and therefore it would be a routine matter to choose to use the end portions of through hole pillars as positioning marks for alignment as taught by Hurwitz(2); the obvious advantages being that this would result in increased alignment accuracy up to +/- 3 microns (Hurwitz(2): Para 0077-0078 and 0085).
As per claim 7, Hurwitz(1) and Hurwitz (2) disclose the elements of the current invention as detailed above with respect to claim 7. Hurwitz(1) discloses that the first through hole pillar of each semi-stack layer made from repeating steps S100, S200, and S300 is arranged in a trench provided between adjacent first line patterns (see above annotated Fig 3(ah)), but neither Hurwitz(1) nor Hurwitz (2) explicitly disclose that each of the semi-stack layers made from repeating steps S100, S200, and S300 includes a plurality of first through hole pillars each arranged in a respective one of trenches provided between adjacent first line patterns. However, simply providing additional through hole pillars in the same arrangement as known in the prior art such as Hurwitz(1) would have been a simple duplication of parts that would have been an obvious choice for one of ordinary skill in the art since it has been held that a mere duplication of working parts of a device involves only routine skill in the art.
Hsu discloses a similar manufacturing method of a multilayer substrate wherein each layer of the multilayer substrate includes plural first pillars (see vias 92 connected with plated through holes 91 in Fig 9) and plural second pillars (see vias 92 not connected with plated through holes 91 and arranged on either side of the “first pillars” in Fig 9) each formed in tranches (see Fig 1-5 that goes into more detail into how the pillars are formed in trenches) and arranged alternatively such that each of the first pillars of each layer are connected in cascade and each of the second pillars of each layer are connected to each other via line patterns (see circuits 90 electrically connected to contact pads 81 in Fig 9) of the layers to allow for a built up multilayer substrate to be manufactured with finer pitches and higher density with a simplified fabrication process with low cost and increased yield (Para 0022-0023).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the above combination of Hurwitz(1) and Hurwitz(2) as to duplicate the first through hole pillar in each semi-stack layer such that each first through hole pillars are arranged in a respective trench provided between adjacent first line patterns as taught by Hsu. One of ordinary skill in the art would recognize that providing additional through hole pillars alternatively with the second through hole pillars in the same arrangement from Hurwitz(1) would have been a simple duplication of parts that would have been an obvious choice for one of ordinary skill in the art since it has been held that a mere duplication of working parts of a device involves only routine skill in the art depending on a desired layout of the final multilayer substrate product for a given circumstance; the obvious advantages being that this would allow for the multilayer substrate to be manufactured with finer pitches and higher density with a simplified fabrication process with low cost and increased yield (Hsu: Para 0022-0023).
As per claim 8, Hurwitz(1), Hurwitz(2), and Hsu disclose the elements of the current invention as detailed above with respect to claim 7. Hurwitz(1) further discloses that S100 includes: S110: selecting the initial layer (see copper base 10 in Fig 3(a); Para 0095), S120: manufacturing a first seed layer (see barrier layer 14 and/or seed layer 20 in Fig 3(c-f); Para 0095) on the initial layer, S130: machining a first photoresist layer (see photoresist 16 in Fig 3(e-f); Para 0095) on the first seed layer, S140: exposing and developing the first photoresist layer to form a first feature pattern (see photoresist 16 in Fig 3(e); Para 0095), S150: electroplating metal in the first feature pattern to form the first line layer (see copper feature 22 formed over the barrier layer 14 in Fig 3(c-i); Para 0095), and S160: removing the first photoresist layer (see Fig 3(h)).
As per claim 9, Hurwitz(1), Hurwitz(2), and Hsu disclose the elements of the current invention as detailed above with respect to claim 7. Hurwitz(1) further discloses that S200 comprises: S210: machining a second photoresist layer (see photoresist 24 in Fig 3(i); Para 0095) on the initial layer and the first line layer, S220: exposing and developing the second photoresist to form a second feature pattern (see photoresist 24 in Fig 3(i); Para 0095), S230: electroplating metal in the second feature pattern to form the first through hole layer (see copper feature layer 22, and vias 25 and 26 in Fig 3(j) formed by electroplating; Par 0095), and S240: removing the second photoresist layer (see Fig 3(k)).
As per claim 10, Hurwitz(1), Hurwitz(2), and Hsu disclose the elements of the current invention as detailed above with respect to claim 8. Hurwitz(1) further discloses that S120 comprises: S121: manufacturing a first adhesion metal layer (see barrier layer 14 in Fig 3(c)) on the initial layer, and S122: manufacturing the first seed layer (see seed layer 20 in Fig 3(f)) on the first adhesion metal layer.
Response to Arguments
Applicant's arguments filed 12/05/2025 regarding the AIA 35 U.S.C. 103 rejection of claim 7 as being unpatentable over US 2007/0289127 Hurwitz(1) in view of US 2013/0344628 Hurwitz(2) have been fully considered but they are not persuasive.
Applicant’s arguments, see Applicant’s remarks, filed 12/05/2025, with respect to the rejection(s) of claim(s) 7 under AIA 35 U.S.C. 103 as being unpatentable over US 2007/0289127 Hurwitz(1) in view of US 2013/0344628 Hurwitz(2) have been fully considered and are persuasive in view of the claim amendments filed. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 2006/0131176 to Hsu (see above 103 rejection for specific details.
The applicant argues that Hurwitz(1) fails to teach the concept of the present application being increasing the available area of transmission line wiring by avoiding the necessity of pads on the line layer.
However, none of the features of increasing the available area of transmission line wiring and/or reducing pads on the line layer are not present in claim 7, the prior art including Hurwitz(1) does not need to disclose these features in order to anticipate and/or render obvious claim 7; therefore these arguments are not persuasive.
The applicant argues that Hurwitz(1) discloses that the copper features (22, 40) serve as line patterns and the vias (26, 26, and 44) are always formed on the copper feature layers and therefore are always connected though the copper features rather than being directly embedded in the gaps between adjacent feature layers as shown at (N) on Page 14 of the applicant’s response.
However, similarly to the above argument. none of the features of not being directly embedded or specifically not including a copper feature or other pads in not present in claim 7 and therefore the prior art including Hurwitz(1) does not need to disclose these features in order to anticipate and/or render obvious claim 7; therefore these arguments are not persuasive.
The applicant argues that Hurwitz(1) discloses that the central copper features 22 should be interpreted as a line layer rather than the first through hole pillar as interpreted by the examiner.
However, a simple statement that the examiner should interpret the claims a certain way is not persuasive as the examiner is required to apply the broadest reasonable interpretation to the claim language for determining patentability. Therefore, since the central copper feature 22 is formed in two steps (see Fig 3g and Fig 3j) whereas the other copper features 22 in which the vias 25 and 26 are formed on are only formed in a single step of Fig 3g, it is reasonable to interpret these elements as different structures as claimed furthermore there is no claim language present in claim 7 that would prevent such an interpretation. therefore these arguments are not persuasive.
The applicant argues that the trench of the present invention is a gap for meeting electrical spacing requirements and does not carry any line functions and only serves as an embedded space for the first through hole pillars, thus the groove (M as shown in on Page 14 of the applicant’s remarks) of Hurwitz(1) is a surface area of the line layer and is therefore is not “between line patterns”.
However, the claim lacks a specific description of what a line layer is or what a line layer can or cannot be; therefore any conductive structure can be interpreted to be the line layer as claimed and/or it can be interpreted that conductive structures (that could otherwise be a line layer) are not the line layer as claimed. For example, the above 103 rejection of claim 7 interprets the four line patters of the copper feature layer 22 in which a via is formed is a line layer as shown in Fig 3j, whereas the central feature of the copper layer 22 is not interpreted as a line layer but rather as the first through hole pillar, because there is nothing in the claim that prevents such an interpretation. Therefore this argument is not persuasive.
The applicant argues that the interpretation of the first through hole pillars identified by the examiner has a fundamental error in that the copper feature layer 40 is not a first through hole pillar but is a first line layer.
However, similarly as above, the claim lacks a specific description of what a line layer is or what a line layer can or cannot be; therefore any conductive structure can be interpreted to be the line layer as claimed and/or it can be interpreted that conductive structures (that could otherwise be a line layer) are not the line layer as claimed. Therefore this argument is similarly not persuasive. It is noted that the interpretation of the first through hole pillars and the second through hole pillars has slightly changed from the previous office actions, please see annotated Fig 3ah provided in the 103 rejection above for specific details.
The applicant argues that Hurwitz(1) ‘s current technical solution still fails to overcome the technical defects associated with pads existing in the prior art which is current invention aims to improve by connecting the first through hole pillars together in cascade by directly through-connecting eliminating the need for pads.
However, the exclusion of a Pad or Pads is not present in the claimed limitations of claim 7, and therefore Hurwitz(1) does not need to disclose these features in order to anticipate and/or render obvious claim 7. Further, there are no limitations present in claim 1 that requires that the first through hole pillars are directly connected to each other, i.e. without the use of a pad or other connecting structure, and there are no specific limitations or special definition provided for “connected in cascade”, therefore since the first through hole pillars of Hurwitz(1) are electrically connected to each other, with or without the use of a pad, the first through hole pillars are considered to be connected in cascade as claimed. Therefore this argument is not persuasive.
The applicant further argues that the interpretation of the Hurwitz(1) reference to read on the first through hole pillars rather than as line layers is incorrect on pages 17-20 and specifically argues that the Hurwitz(1) reference does not achieve the specific technical solutions of the current invention (limitations of pads, electrical spacing requirements, increasing available wiring area of transmission lines, etc.) and therefore cannot be used to read on these specific technical solutions.
However, these specific technical solutions are not present in claim 7 and therefore are not required to be discussed or specifically taught by the prior art including Hurwitz(1) to anticipate and/or render obvious claim 1. Further, as discussed above, the claim lacks a specific description of what a line layer is or what a line layer can or cannot be; therefore any conductive structure can be interpreted to be the line layer as claimed and/or it can be interpreted that conductive structures (that could otherwise be a line layer) are not the line layer as claimed. Therefore these argument are similarly not persuasive.
The applicant argues that Hurwitz(1) requires the removing of the first through hole pillar for forming cavity 480 for placing IC die 490 which is an essential step of Hurwitz(1) and therefore is an exact opposite teaching than the claimed invention.
However, Hurwitz(1) explicitly discloses that the steps as shown in Fig 3(ai)-3(ao) of forming cavity 480 which an IC 490 can be connected within are optional steps, and are therefore not essential steps as argued by the applicant. Further, even if the steps of Hurwitz(1) for removing the first through hole pillar top form the cavity for placing the die was disclosed as essential steps of Hurwitz(1), which is not the case, since claim 7 is directed towards a method of manufacture, and there is no limitations in the claim that require the first through hole pillar to be provided in the final product, therefore even based on this argument from the applicant, Hurwitz(1) would still read on the claimed limitations of claim 7 as discussed above and in the above 103 rejection; therefore this argument is not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua D. Anderson, whose telephone number is (571) 270-0157. The examiner can normally be reached from Monday to Friday between 7 AM and 1 PM Arizona time.
If any attempt to reach the examiner by telephone is unsuccessful, the examiner’s supervisor, Thomas Hong, can be reached at (571) 272-0993.
Another resource that is available to applicants is the Patent Application Information Retrieval (PAIR). Information regarding the status of an application can be obtained from the (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAX. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, please feel free to contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Applicants are invited to contact the Office to schedule an in-person interview to discuss and resolve the issues set forth in this Office Action. Although an interview is not required, the Office believes that an interview can be of use to resolve any issues related to a patent application in an efficient and prompt manner.
/JOSHUA D ANDERSON/
Examiner, Art Unit 3729
/THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729