Prosecution Insights
Last updated: October 02, 2026
Application No. 17/907,245

PROCESS FOR MANUFACTURING A PIEZOELECTRIC STRUCTURE FOR A RADIOFREQUENCY DEVICE WHICH STRUCTURE CAN BE USED TO TRANSFER A PIEZOELECTRIC LAYER, AND PROCESS FOR TRANSFERRING SUCH A PIEZOELECTRIC LAYER

Non-Final OA §103
Filed
Mar 17, 2023
Priority
Mar 24, 2020 — FR FR2002833 +1 more
Examiner
CARLEY, JEFFREY T.
Art Unit
3729
Tech Center
3700 — Mechanical Engineering & Manufacturing
Assignee
Soitec
OA Round
3 (Non-Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
600 granted / 811 resolved
+4.0% vs TC avg
Strong +26% interview lift
Without
With
+26.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
32 currently pending
Career history
844
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
27.5%
-12.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 811 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/09/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 9-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Castex, in view of Deguet et al. (US 2009/0246933 A1). Regarding claim 1, Castex discloses method of manufacturing a piezoelectric structure (Abstract) for a radiofrequency device, the method comprising: providing a substrate of piezoelectric material (420) (fig. 4; col. 6, lines 6-8); providing a carrier substrate (410) (fig. 4; col. 6, line 20); providing a dielectric bonding layer (silicon oxide in recess 440, and/or bonding layer 460, also silicon oxide) comprising a layer of silicon oxide and/or silicon nitride directly on and in contact with the substrate of piezoelectric material by chemical vapor deposition (fig. 4; col. 6, lines 14-24); joining the substrate of piezoelectric material to the carrier substrate by way of the dielectric bonding layer (fig. 4; col. 6, lines 27-39); and after joining the substrate of piezoelectric material to the carrier substrate, thinning the substrate of piezoelectric material to form the piezoelectric structure comprising a layer of piezoelectric material joined to the carrier substrate by way of the dielectric bonding layer (fig. 4; col. 6, lines 40-46). Castex, however, does not explicitly disclose that the provision of a dielectric bonding layer is done by plasma-assisted chemical vapor deposition at a temperature less than or equal to 300°C. Deguet teaches that it is well known to perform a similar method of manufacturing a piezoelectric structure for a radiofrequency device, the method comprising: providing a substrate of piezoelectric material (“thin layer of piezoelectric material”, disclosed as being comprised of quartz) (figs. 4-5; pars. 0104-0105, 0108-0109); providing a carrier substrate (28) (fig. 5; par. 0109); providing a dielectric bonding layer (a deposited “oxide”) comprising a layer of silicon oxide and/or silicon nitride (SiO2) on the substrate of piezoelectric material by plasma-assisted chemical vapor deposition at a temperature less than or equal to 300°C (pars. 0084 and 0110: “a deposit of SiO2 at a temperature <200°C”). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to have modified the current invention of Castex to incorporate the plasma assisted chemical vapor deposition at or below 300°C of Deguet. POSITA would have realized that the chemical vapor deposition of Castex can be easily and readily modified to include a plasma assisted deposition to achieve the desired strength of adhesion, molecular bonding and reliable formation of layers, thus predictably decreasing costly rework. Moreover, there is no indication in the instant disclosure that any special plasma assisted CVD was devised or that any surprising results were derived from simply using the old method of Castex with the well-known plasma assisted CVD of Deguet. This combination would have been easily performed with knowledge of the commonly understood advantages and with reasonable expectations of success. Regarding claim 2, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Castex further discloses that the dielectric bonding layer comprises a layer of silicon oxide (col. 6, lines 14-24). Deguet also teaches that it is well known that the dielectric bonding layer comprises a layer of silicon oxide (SiO2) (par. 0110). Regarding claim 3, Castex in view of Deguet teaches the method of claim 2 as detailed above, and Castex further discloses that the dielectric bonding layer comprises a layer of silicon oxide (fig. 4; col. 6, lines 27-39). Deguet also teaches that it is well known that the joining step comprises a molecular bonding between the dielectric bonding layer and the carrier substrate (pars. 0059, 0084 and 0110). Regarding claim 4, Castex in view of Deguet teaches the method of claim 3 as detailed above, and Deguet further teaches that it is well known that the substrate of piezoelectric material has a *rough surface (2’ or 2”) designed to (capable of) reflect a radiofrequency wave (par. 0059). *Note: The term “rough” is not necessarily indefinite, but it is entirely subjectively defined. Virtually all, if not all known surfaces are understood to have some degree of roughness and are understood to naturally reflect at least one radiofrequency wave. Accordingly, the piezoelectric material of Deguet is understood to be rough to some degree and to be capable of reflecting at least one frequency of radio wave. Regarding claim 5, Castex in view of Deguet teaches the method of claim 4 as detailed above, and Castex further discloses forming the dielectric layer such that the thickness of the dielectric bonding layer is between 200 nm and 500 nm (100 nm to 20 µm includes the entire claimed range) (col. 6, lines 6-16). Regarding claim 6, Castex in view of Deguet teaches the method of claim 5 as detailed above, and Deguet further teaches that it is well known that the carrier substrate further comprises a trapping layer joined to the dielectric bonding layer (pars. 0060-0063). Regarding claim 9, Castex in view of Deguet teaches the method of claim 6 as detailed above, and Castex further discloses that the thinning step comprises etching and/or chemical mechanical polishing (col. 6, lines 40-46). Regarding claim 10, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Castex further discloses a method of transferring a piezoelectric layer to a final substrate (fig. 5), comprising: providing a piezoelectric structure obtained by implementing the method according to claim 1, forming a weakened zone (570) in the layer of piezoelectric material so as to delimit the piezoelectric layer to be transferred; providing the final substrate (510); bonding together the layer of piezoelectric material and the final substrate; and breaking and separating the piezoelectric structure along the weakened zone (fig. 5; cols. 6-7, lines 50-67 and 1-5). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to have modified the figure 4 embodiment of Castex to incorporate the weakened zone and material removal of the figure 5 embodiment. Clearly Castex would have been aware of and understood the obviousness of using the weakened zone of their own invention with the techniques of figure 4. Any POSITA would have realized that forming a weakened zone in the piezoelectric, separating at the weakened zone and applying a final substrate can be easily and readily employed to achieve the desired piezoelectric thickness and bonding to a preferred substrate material. Moreover, there is no indication in the instant disclosure that any special steps were devised or that any surprising results were derived from simply using the old method of Castex with the well-known additional steps of another embodiment of Castex. This combination would have been easily performed with knowledge of the commonly understood advantages and with reasonable expectations of success. Regarding claim 11, Castex in view of Deguet teaches the method of claim 10 as detailed above, and Castex further discloses that the weakened zone is formed by implanting atomic species in the layer of piezoelectric material (col. 6, lines 50-56). Regarding claim 12, Castex in view of Deguet teaches the method of claim 10 as detailed above, and Deguet further teaches that it is well known that the final substrate (20) and the carrier substrate (100) have identical coefficients of expansion. Both are disclosed as being made of silicon, and therefore are naturally expected to share identical coefficients of expansion properties (pars. 0062 and 0070). The applicant is respectfully advised that it has been held by the courts that where a prior art apparatus is identical or substantially identical in structure, claimed properties or functional characteristics are presumed to be inherent, and a prima facie case of either anticipation or obviousness has been established. Regarding claim 13, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Castex further discloses that the joining comprises a molecular bonding between the dielectric bonding layer and the carrier substrate (col. 6, lines 16-30). Regarding claim 14, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Deguet further teaches that it is well known that the substrate of piezoelectric material has a *rough surface (2’ or 2”) designed to (capable of) reflect a radiofrequency wave (par. 0059). *See “Note” applied to claim 4, above. Regarding claim 15, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Castex further discloses that the thickness of the dielectric bonding layer is between 200 nm and 500 nm (100 nm to 20 µm includes the entire claimed range) (col. 6, lines 6-16). Regarding claim 16, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Deguet further teaches that it is well known that the carrier substrate further comprises a trapping layer joined to the dielectric bonding layer (pars. 0060-0063). Regarding claim 19, Castex in view of Deguet teaches the method of claim 1 as detailed above, and Castex further discloses that the thinning step comprises etching and/or chemical mechanical polishing (col. 6, lines 40-46). Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Castex in view of Deguet, further in view of Block et al. (WO 2017/052646 A1). Regarding claims 7 and 17, Castex in view of Deguet teaches all of the elements of the current invention as detailed above with respect to claims 6 and 16, respectively. The modified Castex, however, does not appear to teach that the trapping layer is polycrystalline silicon. Block teaches that it is well known to perform a similar method (Title Abstract), including providing a carrier substrate (104) having a trapping layer (107), wherein the trapping layer is polycrystalline silicon (fig. 2; pg. 7, lines 22-24; pp. 7-8, lines 32-33 and 1-7). Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to have further modified the current inventions of Castex and Deguet to incorporate the trap material selected to be polycrystalline silicon of Block. POSITA would have realized that Deguet discloses that the trap layer is formed on a silicon substrate (pars. 0060-0063), which can be easily and readily provided with polycrystalline silicon to achieve the desired thinning depth. Moreover, there is no indication in the instant disclosure that any special trap layer was devised or that any surprising results were derived from simply using the old methods of Castex and Deguet with the well-known polycrystalline silicon material selection of Block. This combination would have been easily performed with knowledge of the commonly understood advantages and with reasonable expectations of success. Regarding claims 8 and 18, Castex in view of Deguet teaches all of the elements of the current invention as detailed above with respect to claims 6 and 16, respectively. Castex and Deguet, however, do not explicitly disclose or teach that the trapping layer is obtained by implanting heavy species such as argon. Block teaches that it is well known to perform a method (Title Abstract), including providing a carrier substrate (104) having a trapping layer (107), wherein the trapping layer is obtained by implanting heavy species such as argon (fig. 2; pp. 7-8, lines 32-33 and 1-7). Regarding the rationale for combination, please refer to claims 7/17, above. Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot because the arguments do not apply to the references as they are currently being used in the instant rejection. Each of the Applicant’s arguments against the applicability of Deguet in an anticipation rejection of claim 1 are based upon the newly added claim limitations, which Deguet is not relied upon to anticipate or teach. As such, according to the new prior art rejections above, all of the currently disclosed and argued limitations in the claims are held to be properly rejected. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to the concurrently mailed PTO-892, as all of those cited references are considered to be pertinent to the claimed invention. For example, JP 2019/526194 A (inventor name translation not found; hereinafter “JP-194”) is held to disclose all of the limitations of claim 1 that are disclosed by Castex. JP-194 discloses a method of manufacturing a piezoelectric structure, the method comprising: providing a substrate of piezoelectric material (10/11) (fig. 7-1 (a); pg. 6, lines 15-17); providing a carrier substrate (20) (fig. 7-1(c)); providing a dielectric bonding layer (50) comprising a layer of silicon oxide and/or silicon nitride directly on and in contact with the substrate of piezoelectric material (fig. 7-1(b)); joining the substrate of piezoelectric material to the carrier substrate by way of the dielectric bonding layer (fig. 7-2(d)); and after joining the substrate of piezoelectric material to the carrier substrate, thinning the substrate of piezoelectric material to form the piezoelectric structure comprising a layer of piezoelectric material joined to the carrier substrate by way of the dielectric bonding layer (fig. 7-2(e)) (All: pp. 10-11, lines 25-41 and 1-7). The JP-194 reference is not currently applied as an anticipation rejection due to the completeness of the above applied art, and in order to avoid an overly long Office Action or duplicative rejections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeffrey T Carley whose telephone number is (571)270-5609. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sunil Singh can be reached at (571)272-3460. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Mar 17, 2023
Application Filed
Sep 26, 2025
Non-Final Rejection mailed — §103
Jan 22, 2026
Response Filed
Apr 14, 2026
Final Rejection mailed — §103
Jul 02, 2026
Response after Non-Final Action
Jul 09, 2026
Request for Continued Examination
Jul 14, 2026
Response after Non-Final Action
Aug 26, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+26.5%)
3y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 811 resolved cases by this examiner. Grant probability derived from career allowance rate.

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