Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant’s response of 12/17/2025 has been entered in the record and considered. With respect to the rejection claim (10) under 35 USC 112(b) is withdrawn in view of applicants’ amendments. Claims 1-4, 6, 8-12 and 17 are allowed in view of applicants’ amendments (Applicant incorporated the limitations of claim 7 as claim 7 was objected to as being dependent upon a rejected claim (see NFR dated 09/22/2025). Claims 7, 14 and 16 are canceled. Claims 5 and 15 are withdrawn.
The following new rejection to claim 13 is made under 35 USC 102 (a)(1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2007-088334 to Yasushi English translation has been provided, see Foreign Reference dated 09/07/2022).
Regarding independent claim 13, Yasushi discloses method for manufacturing semiconductor device (Figs. 2A- 2F) comprising:
a step of selectively implanting an n type impurity into a front surface of a p type semiconductor substrate (Fig. 2A: 1) and thereafter forming a first n type epitaxial layer (Fig. 2B: 16) on the front surface of the p type semiconductor substrate (1) to form an n type embedded layer (Fig. 2B: 14) that extends across a boundary between the p type semiconductor substrate (1) and the first n type epitaxial layer (16) (see Fig. 2C);
a step of selectively implanting a p type impurity into a front surface of the first n type epitaxial layer (16) and thereafter forming a second n type epitaxial layer (Fig. 2C: 17) on the front surface of the first n type epitaxial layer (16) to form a p type embedded layer (Fig. 2C: 15) between the first n type epitaxial layer (16) and the second n type epitaxial layer (17);
a step of forming, in a surface layer portion of the second n type epitaxial layer (17), a p type well layer (Fig. 2E: 4) that is disposed above the p type embedded layer (15); and
a step of forming, in a surface layer portion of the p type well layer (4), an n type source contact region (Fig, 2F: 5) that is higher in impurity concentration (N+) than the second n type epitaxial layer (17, N-) and forming, in the surface layer portion of the second n type epitaxial layer (17), an n type drain contact region (Fig. 2F: 8) that is higher in impurity concentration (N+) than the second n type epitaxial layer (17, N-);
a step of forming, on a front surface of the second n type epitaxial layer (see Fig. 2D: 17), a gate insulating film (gate insulating film is inherent and is also disclosed but not shown, the gate insulating film is always formed under the gate electrode) to cover a channel region (see Examiner’s Mark-up below; channel region is also inherent for a LDMOS transistor) between the source contact region (5) and the drain contact region (8) and a step of forming, on the gate insulating film, a gate electrode (Fig. 2F: 10) that opposes the channel region via the gate insulating film (the gate insulating film is inherent and is also disclosed but not shown, in order to the transistor to operate there has to be a gate insulating film), wherein
in the step of forming the p type embedded layer (Fig. 2F: 15), the p type embedded layer (15) is formed just in a surface layer portion of the first n type epitaxial layer (see Fig. 2D: 16 with respect to Fig. 2F: 15).
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Allowable Subject Matter
Claims 1-4, 6, 8-12 and 17 are allowed.
The following is an examiner’s statement of reasons for allowance: The examiner’s reasons for independent claim 1 and its respective dependent claims are of record in the September 22, 2025 Office action.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
Applicant argued “In the Action, the Examiner alleges, with respect to the rejection of claim 14, that ... Yasushi discloses wherein in the step of forming the p type embedded layer (Fig. 2F: 15), the p type embedded layer (15) is formed just in a surface layer portion of the first n type epitaxial layer (see Fig. 2D: 16 with respect to Fig. 2F: 15) (Action, p.5).
Further, in the rejection of claim 16, the Examiner alleges that
... Yasushi discloses
a step of forming, on a front surface of the second n type epitaxial layer (see
Fig. 2D: 17), a gate insulating film (gate insulating film is inherent and is also disclosed but not shown, the gate insulating film is always formed under the gate electrode) such as to cover a channel region (see Examiner's Mark-up below; channel region is also inherent for a LDMOS transistor) between the source contact region (5) and the drain contact region (8) and
a step of forming, on the gate insulating film, a gate electrode (Fig. 2F: 10) that opposes the channel region via the gate insulating film (the gate insulating film is inherent and is also disclosed but not shown, in order to the transistor to operate there has to be a gate insulating film) (Action, p. 5).
The Examiner's mark-up of Fig. 2F is also reproduced below.
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Applicant respectfully disagrees. In Yasushi,
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However, Yasushi does not teach any "channel region," which, as defined in [[0046] of the specification, is "A region in which the gate electrode 19 opposes the p type well region 15 via the gate insulating film 18...," where "[f]orming of a channel in the channel region 20 is controlled by the gate electrode 19" ( ¶0046).
In the Action, the Examiner alleges that "channel region is ... inherent for a LDMOS transistor" in Yasushi (see Action, p. 5). He also alleges that "the gate insulating film is inherent
and is also disclosed but not shown, in order to the transistor to operate there has to be a gate insulating film" (see Action, p. 5).
Applicant respectfully disagrees. The fact that a certain result or characteristic may occur or be present in the prior art is not sufficient to establish the inherency of that result or characteristic. In re Rijckaert, 9 F.3d 1531, 1534, 28 USPQ2d 1955, 1957 (Fed. Cir. 1993). "In relying upon the theory of inherency, the examiner must provide a basis in fact and/or technical reasoning to reasonably support the determination that the allegedly inherent characteristic necessarily flows from the teachings of the applied prior art." Ex parte Levy, 17 USPQ2d 1461, 1464 (Bd. Pat. App. & Inter. 1990) (emphasis in original). Even if one were to agree with the Examiner that a MOSFET typically has a channel region and a gate insulating film, the spatial relationship defined in
a step of forming, on a front surface of the second n type epitaxial layer, a
gate insulating film to cover a channel region between the source contact region
and the drain contact region, and
a step of forming, on the gate insulating film, a gate electrode that opposes
the channel region via the gate insulating film,
does not necessarily flows from Yasushi, which shows neither a channel region nor a gate insulating film.
Therefore, Yasushi does not disclose, or even suggest, all of the features recited in claim 13, and thus does not anticipate the claim or otherwise render the claim obvious.”
However, in response, Applicant’s argument regarding inherency is not persuasive. The Examiner does not rely on a general assertion that LDMOS devices “typically” include a channel region. Rather, the inherency determination is based on the specific structural configuration expressly disclosed by Yasushi. The reference teaches a semiconductor substrate including a source region, a drain region, a gate electrode, and a gate insulating film disposed between the gate electrode and the semiconductor body.
Given this arrangement, operation of the disclosed transistor necessarily results in the formation of a carrier conduction region beneath the gate insulating film between the source and drain regions. This carrier conduction region corresponds to what Applicant refers to as a “channel region.” The claimed channel region is therefore not a separately fabricated structure, but an inevitable functional region that necessarily flows from the disclosed structural relationship of the gate, insulating film, and semiconductor body.
Accordingly, the presence of the channel region is not merely possible or probable, but is a physical consequence that necessarily flows from the disclosed structural configuration. For clarity, the claimed “channel region” merely denotes the carrier conduction area that inherently forms beneath the gate insulating film during normal operation of the disclosed device and is not a separately fabricated element. The rejection therefore properly relies on inherency arising from the expressly taught structure rather than from general assumptions about LDMOS devices.
It is for the above discussed reasons that the rejection as applied is considered proper.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2019/0326434 to Sekikawa et al., US Pub # 2019/0259749 to Ishii, US Pub # 2007/0246771 to McCormack et al., US Pub # 2007/0090451 to Lee and US Pub # 2006/0275980 to Sakakibara et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896