DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Objections
Claims 5 and 16 are objected to because of the following informalities:
Dependent Claim 5 recites “the first principle plane”. There is no “first principle plane” in Claim 1.
For purposes of compact prosecution, Claim 5 will be interpreted to instead recite “the first principal plane”. Appropriate correction is required.
Dependent Claim 16 recites “the first principle plane”. There is no “first principle plane” in Claim 12.
For purposes of compact prosecution, Claim 16 will be interpreted to instead recite “the first principal plane”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 11-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda, US 20130076934, in view of Park et al. (“Park”), US 2017/0207263.
Regarding Claim 1, Maeda discloses imaging apparatus (100; Fig. 1; ¶ 0034), comprising:
a semiconductor substrate (110; Fig. 7A; ¶ 0157);
a photoelectric conversion portion (1; Figs. 7A, 8; ¶ 0159) disposed inside the semiconductor substrate (Figs. 7A, 8; ¶ 0159); and
a vertical transistor (20, 2; Figs. 4, 7A-8; ¶ 0156) disposed on the semiconductor substrate (Figs. 7A-8) such that, in a cross-sectional view (Figs. 7A, 8), the vertical transistor is at least partially superimposed on the photoelectric conversion section (Figs. 7A, 8; ¶ 0159 “the side surface of the impurity layer 10 of the photodiode” 1 is “in contact with the gate insulating film 21 on the side surface of the embedded portion 121” (emphasis added), therefore the vertical transistor is at least partially superimposed on the photoelectric conversion section in the vertical direction, note that in the cross-sectional views shown in Figs. 7A and 8 the contact between photodiode 1 and the vertical transistor is not shown - only explained in ¶ 0159),
wherein the semiconductor substrate is provided with a hole portion (RC2; Figs. 7A-8; ¶ 0157) that extends in a direction perpendicular to (Figs. 7A and 8 in this instance hole portion RC2 extends in a vertical direction) a first principal plane (A1; Figs. 7A and 8; ¶ 0166 “"A1" in FIG. 8 represents a position of the surface of the semiconductor substrate 110” in this instance first principal plane A1 is in a horizontal direction, note the “channel length direction” label in Figs. 7A, 8; ¶ 0155 “FIG. 7A shows…the channel length direction of the transistor.”) of the semiconductor substrate (Figs. 4, 7A, 8; ¶ 0155 “FIG. 7A shows a cross section taken along line VIIA-VIIA in FIG. 4 and also shows a cross-sectional configuration of the transfer gate 2 along the channel length direction of the transistor.”), and
wherein the vertical transistor includes:
a first gate electrode (121; Fig. 7A; ¶ 0157) provided inside the hole portion (Fig. 7A; ¶ 0157); and
a first gate insulating film (leftmost vertical portion of 21; Figs. 7A, 8; ¶ 0157) provided between an inner wall of the hole portion and the first gate electrode (Figs. 7A, 8; ¶ 0157);
a second gate insulating film (rightmost vertical portion of 21; Figs. 7A, 8; ¶ 0157) disposed on the first principal plane of the semiconductor substrate (Figs. 7A, 8; ¶ 0157 in this instance second gate insulating film 21 is a portion of A1, therefore the second gate insulating film 21 is disposed on the first principal plane of the semiconductor substrate); and
a second gate electrode (120; Figs. 7A-8; ¶ 0156) which is in contact with the first gate electrode (Figs. 7A-8; ¶ 0156)
wherein the length of the first gate electrode and the length of the second gate electrode are perpendicular (Figs. 7A-8; ¶ 0162 “in the vertical direction with respect to the surface of the semiconductor substrate 110”) to a light-incident surface (Figs. 7A-8; ¶ 0162 “the surface of the semiconductor substrate 110”) of the imaging apparatus.
Maeda does not disclose wherein a length of the first gate electrode is greater than a length of the second gate electrode, wherein a cross section of the first gate electrode cut along a plane parallel to the first principal plane has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would be obvious to one of ordinary skill in the art for Maeda to have wherein a length of the first gate electrode is greater than a length of the second gate electrode, wherein the length is perpendicular to a light-incident surface of the imaging apparatus in order to optimize the location of the bottom surface of electrode 121 ”to be arranged at substantially the same position (depth) as the position of the center of the impurity concentration” (Maeda ¶0163 noting that the bottom surface of first gate electrode 121 is the bottom surface of element 20 in Figs. 7A-8 as stated in ¶ 0156) in order to have “nearly all of the electrical charges stored in the photodiode 1 in association with light from a subject…transferred to the floating diffusion 6” (Maeda ¶ 0164) to improve the performance of the imaging apparatus.
Maeda as modified does not disclose wherein a cross section of the first gate electrode cut along a plane parallel to the first principal plane has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate.
Park discloses wherein a cross section of the first gate electrode (Figs. 3-5; ¶ 0060) cut along a plane parallel to the first principal plane (130L_3; Fig. 5; ¶ 0060) has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate (¶ 0060 in this instance “a crystal plane of (100)”).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention for Maeda to have a cross section of the first gate electrode cut along a plane parallel to the first principal plane has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 2, Maeda does not disclose wherein the inner wall includes:
a first inner wall of which a crystallographic plane is a (100) plane; and
a second inner wall of which a crystallographic plane is a (110) plane,
wherein the first gate insulating film includes:
a first part positioned between the first inner wall and the first gate electrode; and
a second part positioned between the second inner wall and the first gate electrode,
wherein a film thickness of the second part is thicker than that of the first part.
Park discloses wherein the inner wall includes:
a first inner wall (Fig. 5; ¶ 0076 in this instance the inner wall corresponding to 130L_3) of which a crystallographic plane is a (100) plane (¶ 0076); and
a second inner wall (Fig. 5; ¶ 0076 in this instance the inner wall corresponding to 130L_2) of which a crystallographic plane is a (110) plane (¶ 0076),
wherein the first gate insulating film includes:
a first part (125; Fig. 5; ¶ 0064, 0076) positioned between the first inner wall and the first gate electrode (Fig. 5); and
a second part (125; Fig. 5) positioned between the second inner wall and the first gate electrode (Fig. 5),
wherein a film thickness (TH2; Fig. 5; ¶ 0076) of the second part is thicker (¶ 0076) than that of the first part (film thickness TH1; Fig. 5; ¶ 0062-0063, 0076).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the inner wall includes: a first inner wall of which a crystallographic plane is a (100) plane; a second inner wall of which a crystallographic plane is a (110) plane, wherein the first gate insulating film includes: a first part positioned between the first inner wall and the first gate electrode, and a second part positioned between the second inner wall and the first gate electrode, wherein a film thickness of the second part is thicker than that of the first part, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 3, Maeda does not disclose wherein the second part is positioned at an end in a long axis direction of the cross section of the first gate electrode.
Park discloses wherein the second part is positioned at an end (Fig. 5; ¶ 0060) in a long axis direction (Fig. 5; ¶ 0060) of the cross section of the first gate electrode (Fig. 5; ¶ 0060).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the second part positioned at an end in a long axis direction of the cross section of the first gate electrode, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 5, Maeda discloses
wherein the second gate insulating film (rightmost vertical portion of 21) is interposed between the second gate electrode and the first principle plane of the semiconductor substrate (Figs. 7A, 8 in this instance the rightmost vertical portion of 21 is interposed between A) the second gate electrode 120 and B) the first principal plane of the semiconductor substrate 110 that is located below hole portion RC2).
Regarding Claim 6, Maeda discloses
an electric charge holding portion (60; Figs. 7A, 8; ¶ 0120, 0159) which is provided on a side of the first principal plane of the semiconductor substrate (Figs. 7A, 8) and which is configured to hold an electric charge generated by the photoelectric conversion portion (¶ 0164-0165),
wherein an end in the long axis direction of the cross section of the first gate electrode is positioned on a side of the photoelectric conversion portion (¶ 0159) and another end in the long axis direction is positioned on a side of the electric charge holding portion (Figs. 7A, 8), and
wherein the vertical transistor is configured to transfer an electric charge created in the photoelectric conversion portion to the electric charge holding portion (¶ 0169).
Regarding Claim 7, Maeda discloses wherein in a plan view (Fig. 4; ¶ 0009) in a normal direction of the first principal plane of the semiconductor substrate (Fig. 4), a central part of the electric charge holding portion, a central part of the cross section of the first gate electrode, and a central part of the photoelectric conversion portion line up in a straight line (Fig. 4).
Regarding Claim 8, Maeda discloses wherein both ends in the long axis direction of the cross section of the first gate electrode are positioned under the second gate electrode (Figs. 7A, 8).
Regarding Claim 9, Maeda does not disclose wherein at least one of both ends in the long axis direction of the cross section of the first gate electrode protrudes from under the second gate electrode.
Park discloses wherein at least one of both ends in the long axis direction of the cross section of the first gate electrode protrudes from under the second gate electrode (¶ 0058).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have at least one of both ends in the long axis direction of the cross section of the first gate electrode protrudes from under the second gate electrode, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 11, Maeda does not disclose wherein the first principal plane is a plane of which a crystallographic plane is a (100) plane or equivalent to a (100) plane.
Park discloses wherein the first principal plane is a plane of which a crystallographic plane is a (100) plane or equivalent to a (100) plane (Fig. 5; ¶ 0076).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the first principal plane is a plane of which a crystallographic plane is a (100) plane or equivalent to a (100) plane, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 12, Maeda discloses an electronic device (900; Fig. 16; ¶ 0262), comprising:
an optical component (90; ¶ 0262);
an imaging apparatus (100; ¶ 0263) into which light transmitted through the optical component is incident (¶ 0263); and
a signal processing circuit (91; ¶ 0264) configured to process a signal output from the imaging apparatus (¶ 0264),
wherein the imaging apparatus (100; Fig. 1; ¶ 0034) includes:
a semiconductor substrate (110; Fig. 7A; ¶ 0157);
a photoelectric conversion portion (1; Figs. 7A, 8; ¶ 0159) disposed inside the semiconductor substrate (Figs. 7A, 8); and
a vertical transistor (20, 2; Figs. 4, 7A-8; ¶ 0156) disposed on the semiconductor substrate (Figs. 7A-8) such that, in a cross-sectional view (Figs. 7A, 8), the vertical transistor is at least partially superimposed on the photoelectric conversion section (Figs. 7A, 8; ¶ 0159 “the side surface of the impurity layer 10 of the photodiode” 1 is “in contact with the gate insulating film 21 on the side surface of the embedded portion 121” (emphasis added), therefore the vertical transistor is at least partially superimposed on the photoelectric conversion section in the vertical direction, note that in the cross-sectional views shown in Figs. 7A and 8 the contact between photodiode 1 and the vertical transistor is not shown - only explained in ¶ 0159),
wherein the semiconductor substrate is provided with a hole portion (RC2; Figs. 7A-7B; ¶ 0157) that extends in a direction perpendicular to (Figs. 7A and 8 in this instance hole portion RC2 extends in a vertical direction) a first principal plane (A1; Figs. 7A and 8; ¶ 0166 “"A1" in FIG. 8 represents a position of the surface of the semiconductor substrate 110” in this instance first principal plane A1 is in a horizontal direction, note the “channel length direction” label in Figs. 7A, 8; ¶ 0155 “FIG. 7A shows…the channel length direction of the transistor.”) of the semiconductor substrate (Figs. 4, 7A, 8; ¶ 0155 “FIG. 7A shows a cross section taken along line VIIA-VIIA in FIG. 4 and also shows a cross-sectional configuration of the transfer gate 2 along the channel length direction of the transistor.”); and
wherein the vertical transistor has:
a first gate electrode (121; Fig. 7A; ¶ 0157) provided inside the hole portion (Fig. 7A; ¶ 0157); and
a first gate insulating film (leftmost vertical portion of 21; Figs. 7A, 8; ¶ 0157) provided between an inner wall of the hole portion and the first gate electrode (Fig. 7A; ¶ 0157);
a second gate insulating film (rightmost vertical portion of 21; Figs. 7A, 8; ¶ 0157) disposed on the first principal plane of the semiconductor substrate (Figs. 7A, 8; ¶ 0157 in this instance second gate insulating film 21 is a portion of A1, therefore the second gate insulating film 21 is disposed on the first principal plane of the semiconductor substrate); and
a second gate electrode (120; Figs. 7A-8; ¶ 0156) which is in contact with the first gate electrode (Figs. 7A-8; ¶ 0156)
wherein the length of the first gate electrode and the length of the second gate electrode are perpendicular (Figs. 7A-8; ¶ 0162 “in the vertical direction with respect to the surface of the semiconductor substrate 110”) to a light-incident surface (Figs. 7A-8; ¶ 0162 “the surface of the semiconductor substrate 110”) of the imaging apparatus.
Maeda does not disclose wherein a length of the first gate electrode is greater than a length of the second gate electrode, wherein a cross section of the first gate electrode cut along a plane parallel to the first principal plane has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would be obvious to one of ordinary skill in the art for Maeda to have wherein a length of the first gate electrode is greater than a length of the second gate electrode in order to optimize the location of the bottom surface of electrode 121 ”to be arranged at substantially the same position (depth) as the position of the center of the impurity concentration” (Maeda ¶0163 noting that the bottom surface of first gate electrode 121 is the bottom surface of element 20 in Figs. 7A-8 as stated in ¶ 0156) in order to have “nearly all of the electrical charges stored in the photodiode 1 in association with light from a subject…transferred to the floating diffusion 6” (Maeda ¶ 0164) to improve the performance of the imaging apparatus.
Maeda as modified does not disclose wherein cross section of the first gate electrode cut along a plane parallel to the first principal plane has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate.
Park discloses wherein cross section of the first gate electrode (Figs. 3-5; ¶ 0060) cut along a plane parallel to the first principal plane (130L_3; Fig. 5; ¶ 0060) has a shape being elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate (¶ 0060 in this instance “a crystal plane of (100)”).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein cross section of the first gate electrode cut along a plane parallel to the first principal plane has a shape elongated in a direction of a crystallographic orientation <100> of the semiconductor substrate, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the electronic device.
Regarding Claim 13, Maeda does not disclose wherein the inner wall includes:
a first inner wall of which a crystallographic plane is a (100) plane; and
a second inner wall of which a crystallographic plane is a (110) plane,
wherein the first gate insulating film includes:
a first part positioned between the first inner wall and the first gate electrode; and
a second part positioned between the second inner wall and the first gate electrode,
wherein a film thickness of the second part is thicker than that of the first part.
Park discloses wherein the inner wall includes:
a first inner wall (Fig. 5; ¶ 0076 in this instance the inner wall corresponding to 130L_3) of which a crystallographic plane is a (100) plane (¶ 0076); and
a second inner wall (Fig. 5; ¶ 0076 in this instance the inner wall corresponding to 130L_2) of which a crystallographic plane is a (110) plane (¶ 0076),
wherein the first gate insulating film includes:
a first part (125; Fig. 5; ¶ 0064, 0076) positioned between the first inner wall and the first gate electrode (Fig. 5); and
a second part (125; Fig. 5) positioned between the second inner wall and the first gate electrode (Fig. 5),
wherein a film thickness (TH2; Fig. 5; ¶ 0076) of the second part is thicker (¶ 0076) than that of the first part (film thickness TH1; Fig. 5; ¶ 0062-0063, 0076).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the inner wall includes: a first inner wall of which a crystallographic plane is a (100) plane; a second inner wall of which a crystallographic plane is a (110) plane, wherein the first gate insulating film includes: a first part positioned between the first inner wall and the first gate electrode, and a second part positioned between the second inner wall and the first gate electrode, wherein a film thickness of the second part is thicker than that of the first part, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 14, Maeda does not disclose wherein the second part is positioned at an end in a long axis direction of the cross section of the first gate electrode.
Park discloses wherein the second part is positioned at an end (Fig. 5; ¶ 0060) in a long axis direction (Fig. 5; ¶ 0060) of the cross section of the first gate electrode (Fig. 5; ¶ 0060).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the second part positioned at an end in a long axis direction of the cross section of the first gate electrode, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Regarding Claim 16, Maeda discloses
wherein the second gate insulating film (rightmost vertical portion of 21) is interposed between the second gate electrode and the first principle plane of the semiconductor substrate (Figs. 7A, 8 in this instance the rightmost vertical portion of 21 is interposed between A) the second gate electrode 120 and B) the first principal plane of the semiconductor substrate 110 that is located below hole portion RC2).
Regarding Claim 17, Maeda discloses
an electric charge holding portion (60; Figs. 7A, 8; ¶ 0120, 0159) which is provided on a side of the first principal plane of the semiconductor substrate (Figs. 7A, 8) and which is configured to hold an electric charge generated by the photoelectric conversion portion (¶ 0164-0165),
wherein an end in the long axis direction of the cross section of the first gate electrode is positioned on a side of the photoelectric conversion portion (¶ 0159) and another end in the long axis direction is positioned on a side of the electric charge holding portion (Figs. 7A, 8), and
wherein the vertical transistor is configured to transfer an electric charge created in the photoelectric conversion portion to the electric charge holding portion (¶ 0169).
Regarding Claim 18, Maeda discloses wherein in a plan view (Fig. 4; ¶ 0009) in a normal direction of the first principal plane of the semiconductor substrate (Fig. 4), a central part of the electric charge holding portion, a central part of the cross section of the first gate electrode, and a central part of the photoelectric conversion portion line up in a straight line (Fig. 4).
Regarding Claim 20, Maeda does not disclose wherein the first principal plane is a plane of which a crystallographic plane is a (100) plane or equivalent to a (100) plane.
Park discloses wherein the first principal plane is a plane of which a crystallographic plane is a (100) plane or equivalent to a (100) plane (Fig. 5; ¶ 0076).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the first principal plane is a plane of which a crystallographic plane is a (100) plane or equivalent to a (100) plane, as taught by Park, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (¶ 0064, 0087) in order to increase the functionality of the imaging apparatus.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda, US 20130076934, in view of Park et al. (“Park”), US 2017/0207263, as applied to claim 1 above, and further in view of Lewis et al. (“Lewis”), “The Effect of Surface Orientation on Silicon Oxidation Kinetics”.
Regarding Claim 4, Maeda as modified does not disclose wherein the film thickness of the second part is 1.1 times or more and 2.0 times or less thicker than the film thickness of the first part.
Lewis discloses wherein the film thickness of the second part is 1.1 times or more and 2.0 times or less thicker than the film thickness of the first part (Table I; page 2335 in this instance the thickness at the temperature of 1000 °C is within the claimed range).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have the film thickness of the second part being 1.1 times or more and 2.0 times or less thicker than the film thickness of the first part, as taught by Lewis, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (Park ¶ 0064, 0087) in order to increase the functionality of the electronic device.
Regarding Claim 15, Maeda as modified does not disclose wherein the film thickness of the second part is 1.1 times or more and 2.0 times or less thicker than the film thickness of the first part.
Lewis discloses wherein the film thickness of the second part is 1.1 times or more and 2.0 times or less thicker than the film thickness of the first part (Table I; page 2335 in this instance the thickness at the temperature of 1000 °C is within the claimed range).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have the film thickness of the second part being 1.1 times or more and 2.0 times or less thicker than the film thickness of the first part, as taught by Lewis, to allow electrons to be more efficiently transferred from the photoelectric conversion portion to the electric charge holding portion (Park ¶ 0064, 0087) in order to increase the functionality of the electronic device.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda, US 20130076934, in view of Park et al. (“Park”), US 2017/0207263, as applied to claim 1 above, and further in view of Kawamura, US 2015/0069471.
Regarding Claim 10, Maeda as modified does not disclose wherein the vertical transistor has a plurality of the first gate electrodes, and wherein the plurality of the first gate electrodes are disposed lined up at intervals in a short axis direction of the cross section.
Kawamura discloses wherein the vertical transistor has a plurality of the first gate electrodes (43A; Fig. 4B; ¶ 0073-0074), and wherein the plurality of the first gate electrodes are disposed lined up at intervals in a short axis direction of the cross section (Fig. 4B).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the vertical transistor having a plurality of the first gate electrodes, and wherein the plurality of the first gate electrodes are disposed lined up at intervals in a short axis direction of the cross section, as taught by Kawamura, to prevent light sensitivity (¶ 0081) in order to increase the functionality of the electronic device.
Regarding Claim 19, Maeda as modified does not disclose wherein the vertical transistor has a plurality of the first gate electrodes, and wherein the plurality of the first gate electrodes are disposed lined up at intervals in a short axis direction of the cross section.
Kawamura discloses wherein the vertical transistor has a plurality of the first gate electrodes (43A; Fig. 4B; ¶ 0073-0074), and wherein the plurality of the first gate electrodes are disposed lined up at intervals in a short axis direction of the cross section (Fig. 4B).
It would have been obvious to one of ordinary skill in the art before the filing date of the present invention to have wherein the vertical transistor having a plurality of the first gate electrodes, and wherein the plurality of the first gate electrodes are disposed lined up at intervals in a short axis direction of the cross section, as taught by Kawamura, to prevent light sensitivity (¶ 0081) in order to increase the functionality of the electronic device.
Response to Arguments
In regards to the amendments and arguments filed 3/3/2026, all §112(b) rejections have been correctly addressed. Thank you for those corrections.
The applicant states (page 10) that “Maeda's channel length direction fails to equate to the claimed first principal plane.”
As explained supra, Maeda discloses a first principal plane (A1; Figs. 7A and 8; ¶ 0166 “"A1" in FIG. 8 represents a position of the surface of the semiconductor substrate 110” in this instance first principal plane A1 is in a horizontal direction, note the “channel length direction” label in Figs. 7A, 8 (see annotated Fig. 8 infra); ¶ 0155 “FIG. 7A shows…the channel length direction of the transistor.”) of the semiconductor substrate (Figs. 4, 7A, 8; ¶ 0155 “FIG. 7A shows a cross section taken along line VIIA-VIIA in FIG. 4 and also shows a cross-sectional configuration of the transfer gate 2 along the channel length direction of the transistor.”).
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The applicant states (page 10) that “Maeda fails to disclose, teach or suggest "wherein the semiconductor substrate is provided with a hole portion that extends in a direction perpendicular to a first principal plane of the semiconductor substrate" as claimed.”
As explained supra, Maeda discloses wherein the semiconductor substrate is provided with a hole portion (RC2; Figs. 7A-8; ¶ 0157) that extends in a direction perpendicular to (Figs. 7A and 8 in this instance hole portion RC2 extends in a vertical direction) a first principal plane (A1; Figs. 7A and 8; ¶ 0166 “"A1" in FIG. 8 represents a position of the surface of the semiconductor substrate 110” in this instance first principal plane A1 is in a horizontal direction).
The applicant states (page 11) that “Maeda fails to disclose, teach or suggest "a second gate insulating film disposed on the first principal plane of the semiconductor substrate" as claimed.”
As explained supra, Maeda discloses a second gate insulating film (rightmost vertical portion of 21; Figs. 7A, 8; ¶ 0157) disposed on the first principal plane of the semiconductor substrate (Figs. 7A, 8; ¶ 0157 in this instance second gate insulating film 21 is a portion of A1, therefore the second gate insulating film 21 is disposed on the first principal plane of the semiconductor substrate);
The applicant states (page 11) that “When addressing the comparisons of the lengths of the first and second gate electrodes, the Office Action at pages 6 and 7, the Office Action relies on MPEP 2144(IV)(A) and In re Rose, In re Rinehart, and Gardner v. TEC Systems.”
As explained supra, MPEP 2144.04(IV)( A) addresses changes in size/proportion. It would be obvious to one of ordinary skill in the art for Maeda to have wherein a length of the first gate electrode is greater than a length of the second gate electrode in order to optimize the location of the bottom surface of electrode 121 ”to be arranged at substantially the same position (depth) as the position of the center of the impurity concentration” (Maeda ¶0163 noting that the bottom surface of first gate electrode 121 is the bottom surface of element 20 in Figs. 7A-8 as stated in ¶ 0156) in order to have “nearly all of the electrical charges stored in the photodiode 1 in association with light from a subject…transferred to the floating diffusion 6” (Maeda ¶ 0164) to improve the performance of the imaging apparatus.
Independent Claims 1 and 12 are rejected for at least the reasons stated supra. In addition, dependent claims 2-11 and 13-20 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818