Detailed Action
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-22 are presented for examination.
Claims 1-22 are rejected.
This Action is Final.
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
Applicant’s representative on Pages 4-5 of the remark agues that, “Roberts does not teach or suggest the "intra-die port connected to the memory banks" on the memory die of claim 1. Dasari likewise omits this element. The combination of Roberts and Dasari thus fails to present a primafacie case of obviousness against claim 1. The rejection of claim 1 should therefore be withdrawn.”
Examiner respectfully disagree with the argument. Robert, Dasari and Franca-Neto teach, disclose or suggest "intra-die port connected to the memory banks". Robert teaches inter connection between memory die and integrated circuit dies [Robert,Fig.6; Paragraphs 0106, At block 401, a first stack 317 of integrated circuit dies 303 and 305 of a device 101 communicates, via a communication connection 309, with a second stack 319 of integrated circuit dies 311, 313 and 315 of the device 101.]. Dasari discloses interconnecting between identical dies in ASIC package [Dasari, Paragraph 0031, The challenges of using custom ASICs can be overcome by designing a standard die, which is configured for processing neural network tasks and interconnecting several such identical dies in a single ASIC chip package. The number of dies interconnected in a single chip package varies based on the complexity or number of layers of the neural network being processed by the host computing device.]. Franca-Neto suggests communication between multiple artificial intelligence processing dies (AIPDs) [Franca-Neto, Paragraph 0033, The AIPU 102 is configured to process computational tasks of a neural network. The AIPU 102 includes multiple artificial intelligence processing dies (AIPDs) 103a, 103b, 103c, 103d, 103e, 103f, collectively referred to herein as AIPDs 103. The AIPDs 103 are identical to each other.].
Therefore, Examiner respectfully submits that the combination Robert, Dasari and Franca-Neto fully teach the subject matter as recited.
7. Applicant’s representative on Pages 5-6 of the remark argues that, “Roberts does not teach or suggest the "intra-die port connected to the memory banks" on the memory die of claim 1. Dasari likewise omits this element. The combination of Roberts and Dasari thus fails to present a prima facie case of obviousness against claim 1.”
In response to applicant's argument that “The combination of Roberts and Dasari thus fails to present a prima facie case of obviousness against claim 1.”, the examiner recognizes that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992).
In this case, Roberts, Dasari and Franca-Neto are analogous art because they are from the same field of endeavor generally relates to integrated circuit device (IC) for supporting Deep Learning Accelerator for ANN and a method for processing neural network related tasks using a single-chip package; and also a device for performing computations of a neural network. At the time of invention, it would have been obvious to one of ordinary skill in the art, having the teaching of Dasari and Franca-Neto before him or her, to modify the teaching of Robert by adding an artificial intelligence processing unit for processing neural network related tasks using a single-chip package of Dasari and a device for performing computations of a neural network of Franca-Neto before. The motivation for doing so would ensure that the unit utilizes a design of a single artificial intelligence processing die in processing and execution of different neural networks with different requirements, thus resulting in reduction of design time related costs and efficient amortization of non-recurring engineering costs and the device eliminates need to find better manner to realize a hardware design for fully connected artificial neural networks without necessarily limiting design to processing according to a particular network architecture. Therefore it would have been obvious to combine Roberts, Dasari and Franca-Neto to obtain the invention as specified in the instant the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts (US Patent Application Pub. No: 20220188606 A1) in view of Dasari et al.(US Patent Application Pub. No: 20190156187 A1).
As per claim 1,Roberts teaches an integrated circuit (IC) device [Fig.1,an integrated circuit (IC) device.], comprising:
a processor die having at least one processing tile [Fig.1, the processing units 111.];
memory dies stacked with and bonded to the processor die, each memory die defining a memory-die plane and having: memory banks spaced in the memory-die plane by a memory-bank pitch [Abstract, Paragraphs 0044;0088, …, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory.];
an inter-die data port connected to at least one of the memory banks on the memory die [Paragraphs 0088;0092, The memory interface 117 of the Deep Learning Accelerator 103 can have a memory controller that is connected to the memory dies 305 using Through-Silicon Vias (TSV) for high bandwidth access.]; and
an intra-die data port connected to the memory banks on the memory die [Paragraphs 0088;0092, The memory interface 117 of the Deep Learning Accelerator 103 can have a memory controller that is connected to the memory dies 305 using Through-Silicon Vias (TSV) for high bandwidth access.].
Roberts does not explicitly disclose an inter-die data connection extended from the processing tile of the processor die to the inter-die data ports of the memory dies.
Dasari discloses an inter-die data connection extended from the processing tile of the processor die to the inter-die data ports of the memory dies [Dasari, Abstract ,Paragraphs 0002;0031-0032, … Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Dasari‘s method for processing neural network related tasks using a single-chip package into Roberts IC device for supporting Deep Learning Accelerator for ANN for the benefit of the unit utilizes a design of a single artificial intelligence processing die in processing and execution of different neural networks with different requirements, thus resulting in reduction of design time related costs and efficient amortization of non-recurring engineering costs (Dasari,[0030]) to obtain the invention as specified in claim 1.
As per claim 2, Roberts and Dasari teach all the limitations of claim 1 above, wherein Roberts and Dasari teach, a device, the processor die [Roberts, Fig.1, the processing units 111.], further including a memory interface divided into sub-interfaces, each sub-interface connected to the intra-die data port of a respective one of the memory dies [Dasari, Abstract ,Paragraphs 0002;0031-0032, … Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die.].
As per claim 3, Roberts and Dasari teach all the limitations of claim 1 above, wherein Roberts teaches, a device, wherein at least one of the inter-die data ports and the intra-die data ports comprises a via field [Roberts, Paragraphs 0088; 0092, The memory interface 117 of the Deep Learning Accelerator 103 can have a memory controller that is connected to the memory dies 305 using Through-Silicon Vias (TSV) for high bandwidth access.].
As per claim 4, Roberts and Dasari teach all the limitations of claim 1 above, wherein Roberts teaches, a device, the processor die further having a first via field electrically connected to the intra-die data port of a first of the memory dies and electrically isolated from the intra-die data port of a second of the memory dies [Roberts, Abstract, Paragraphs 0044;0088, …, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory.].
As per claim 5, Roberts and Dasari teach all the limitations of claim 4 above, wherein Roberts teaches, a device, the processor die further having a second via field electrically connected to the intra-die data port of the second of the memory dies and electrically isolated from the intra-die data port of the first of the memory dies [Roberts, Abstract, Paragraphs 0044;0088, …, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory.].
As per claim 6, Roberts and Dasari teach all the limitations of claim 1 above, wherein Dasari teaches, a device, further comprising a base die bonded to the processor die and the memory dies and communicatively coupled to the intra-die data ports [Dasari, Abstract ,Paragraphs 0002;0031-0032, … Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die.].
As per claim 7, Roberts and Dasari teach all the limitations of claim 1 above, wherein Roberts teaches, a device, wherein each of the memory banks occupies a bank area and one tile of the at least one processing tile occupies a tile area substantially equal to the area of a whole number of the bank areas [Roberts, Paragraphs 0101-0119, Preferably, the memory system provided in the integrated circuit device 101 is configured such that the memory controller in the memory interface 117 of the Deep Learning Accelerator 103 can access any of the memory dies 305, 311, 313, and 315 in any of the stacks 317 and 319, when the corresponding bank of memory in the die is not currently being used by a corresponding interface and buffer 307.].
As per claim 8, Roberts and Dasari teach all the limitations of claim 7 above, wherein Roberts teaches, a device, wherein the one tile has a tile boundary encompassing the area of the whole number of the bank areas from a perspective normal to the processor die [Roberts, Paragraphs 0101-0119, Preferably, the memory system provided in the integrated circuit device 101 is configured such that the memory controller in the memory interface 117 of the Deep Learning Accelerator 103 can access any of the memory dies 305, 311, 313, and 315 in any of the stacks 317 and 319, when the corresponding bank of memory in the die is not currently being used by a corresponding interface and buffer 307.].
As per claim 9, Roberts and Dasari teach all the limitations of claim 1 above, wherein Roberts teaches, a device, the processor die further having a controller to manage communication between the processing tile and inter-die data ports of the memory dies [Roberts, Abstract, Paragraphs 0044;0088, …, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory.].
As per claim 10, Roberts and Dasari teach all the limitations of claim 1 above, wherein Roberts teaches, a device, each memory die having a second inter-die data port connected to one of the memory banks different from the at least one of the memory banks to which the first-mentioned inter-die data port is connected [Roberts, Abstract, Paragraphs 0044;0088, …, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory.].
As per claim 11, Roberts and Dasari teach all the limitations of claim 10 above, wherein Dasari teaches, a device, wherein the intra-die data port on each of the memory dies is connected to the ones of the memory banks to which the first-mentioned and second inter-die data ports are connected [Dasari, Abstract, Paragraphs 0002;0031-0032, … Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die.].
9. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts (US Patent Application Pub. No: 20220188606 A1) in view of Franca-Neto et al.(US Patent Application Pub. No: 20190244106 A1).
As per claim 12, Roberts teaches all the limitations of claim 1 above, wherein Roberts teaches, a device, the processor die including an array of interconnected processing elements [Roberts, Paragraph 0125,The inter-connect interconnects the microprocessor(s) and the memory together and also interconnects them to input/output (I/O) device(s) via I/O controller(s).]
Roberts does not explicitly disclose including upstream processing elements and downstream processing elements, each processing element including:
a forward-propagation input port to receive a forward partial result;
a forward-propagation processor to update the forward partial result;
a forward-propagation output port to transmit the updated forward partial result;
a back-propagation input port to receive a back-propagation partial result;
a back-propagation processor to update the back-propagation partial result; and
a back-propagation output port to transmit the updated back-propagation partial result.
Franca-Neto discloses a device, including upstream processing elements and downstream processing elements [Franca-Neto, Paragraph 0195, … Each DPU is configured to independently compute a partial result as a function of the data received from an upstream DPU, store the result within itself, and pass the result downstream.], each processing element including:
a forward-propagation input port to receive a forward partial result [Franca-Neto, Paragraphs 0012;0064,FIGS. 6B to 6E depict diagrams representing forward propagation and backpropagation as implemented by the systolic neural network engine of FIG. 3 ….];
a forward-propagation processor to update the forward partial result [Franca-Neto, Paragraphs 0062;0064, …, systolically pulsing the first activation output to the second input systolic element can include forward propagating the first activation output to the second input systolic element.];
a forward-propagation output port to transmit the updated forward partial result [Franca-Neto, Paragraphs 0064;0067, wherein the plurality of processing nodes are configured to perform computations for forward propagation of the input values through layers of the neural network to generate predicted output values by at least,….];
a back-propagation input port to receive a back-propagation partial result [Franca-Neto, Paragraphs 0068-0069, In the device of any of the preceding paragraphs, the first processing units can be configured to accumulate partial derivatives based on values received from the second arrangement during the backward propagation.];
a back-propagation processor to update the back-propagation partial result [Franca-Neto, Paragraphs 0069-0081,…, systolically pulse data in a second direction through the plurality of processing units during the backward propagation, wherein the second direction is opposite the first direction.]; and
a back-propagation output port to transmit the updated back-propagation partial result [Franca-Neto, Paragraphs 0069-0081, …, the method can further comprise accumulating a weighted sum of the partial derivatives as data is propagated backwards through the first arrangement.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Franca-Neto‘s device for performing computations of a neural network into Roberts IC device for supporting Deep Learning Accelerator for ANN for the benefit of the device reduces a number of trainable weights, and increases applicability of a convolutional neural network to data sets outside of training data; and the device eliminates and reduces requirement by directly propagating inter-layer data between data processing units (DPUs), and eliminates and reduces wait time required for memory accesses (Franca-Neto,[0213]) to obtain the invention as specified in claim 12.
As per claim 13, Roberts and Franca-Neto teach all the limitations of claim 12 above, wherein Franca-Neto teaches, a device, wherein the forward-propagation processor and the back- propagation processor concurrently update the forward partial result and the back-propagation partial result, respectively [Franca-Neto, Paragraphs 0069-0081; 0195, … Each DPU is configured to independently compute a partial result as a function of the data received from an upstream DPU, store the result within itself, and pass the result downstream.].
Allowable Subject Matter
10. The prior art of record doesn’t teach or render obvious on all the limitation of claim 14, therefore independent claim14 will be allowable as it is.
11. Dependent claims 15-22 are would be also allowable as being dependent on claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
Liu et al. (US Patent Application Pub. No: 20250054911 A1) teaches a method for three-dimensional memory stacking may include providing a logic die including a circuit and a memory, providing a memory die including an additional memory having a same footprint as the circuit and memory in the logic die, and stacking the logic die and the memory die three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds. Various other methods, systems, and computer-readable media are also disclosed.
Vogelsang et al. (US Patent Application Pub. No: 20220137843 A1) teaches a memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Vogelsang discloses whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter; and counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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