Prosecution Insights
Last updated: July 17, 2026
Application No. 17/911,101

SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Sep 12, 2022
Priority
Mar 26, 2020 — JP 2020-055651 +1 more
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
742 granted / 907 resolved
+13.8% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
43 currently pending
Career history
944
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
73.6%
+33.6% vs TC avg
§102
10.7%
-29.3% vs TC avg
§112
2.6%
-37.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 907 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1 thru 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The new limitation “the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction.” is not described in the specification. Even though FIG. 3 shows an illustration that appears to show electrodes 33A in a first lead 10A being not aligned perfectly with the electrodes 33A in a first lead 10C, drawings are not drawn to scale and there is no description in the specification that describes “the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction.”. Further, the terms “staggered”, “row”, “first row”, “second row”, and “first direction” are never used in the specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In view of the 112 rejection above, claim(s) s 1 thru 9, 11, 12, and 14 thru 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsao et al US 2019/0164920 A1 in view of Takahashi US 2014/0264847 A1. Tsao discloses (see, for example, FIG. 14) a semiconductor device comprising a semiconductor element 15’, element first surface (i.e. bottom surface of element 15’), element second surface (i.e. top surface of element 15’), electrode 40’, conducting member 30, obverse surface (i.e. top surface of conducting member 30), reverse surface (i.e. bottom surface of conducting member 30), conductive bonding material 90, resin member 95, first barrier layer 25’, and protective film 60’. In FIG.14, Tsao discloses the element first surface being further provided with a protective film 60’ covering a part of the electrode 40’. Tsao does not disclose each of the plurality of electrodes the plurality of electrodes include electrodes arranged in a first row and electrodes arranged in a second row, the first row and the second row being adjacent to each other and each extending in a first direction perpendicular to the thickness direction, the first row and the second row being spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction. However, Takahashi discloses (see, for example, FIG. 2, 5, and 6) a semiconductor device comprising a plurality of electrodes 3 set in adjacent, vertical rows wherein each row contains electrodes that are staggered to the electrodes in the adjacent row. In paragraph [0013], Takahashi discloses how the electrodes are staggered to each other and no electrode is aligned with any electrode in the next column. It would have been obvious to one of ordinary skill in the art, at a time of prior to the effective filing date, to have each of the plurality of electrodes the plurality of electrodes include electrodes arranged in a first row and electrodes arranged in a second row, the first row and the second row being adjacent to each other and each extending in a first direction perpendicular to the thickness direction, the first row and the second row being spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction in order to increase density, and thereby downsize the semiconductor device. Regarding claim 2, see, for example, paragraph [0039] wherein Tsao discloses the electrode 40’ may include Cu. Regarding claim 3, see, for example, paragraph [0030] wherein Tsao discloses the conductive member 30 may be Cu. Regarding claim 4, see, for example, paragraph [0045] wherein Tsao discloses the conductive member 25’ may be Ni. Regarding claim 5, see, for example, paragraph [0057] wherein Tsao discloses the conductive bonding material 90 may be a solder joint, which contain Sn. Regarding claim 6, see, for example, FIG. 14 wherein Tsao discloses electrode 40’ and another first barrier layer 30’. Regarding claim 7, see, for example, FIG. 14 wherein Tsao discloses the conductive bonding material 90 and the first barrier layer 25’ being in contact with each other. Regarding claim 8, see, for example, FIG. 14 wherein Tsao discloses a second barrier layer 25 that is disposed between the conducting member 30 and the conductive bonding material 90 and prevents a reaction between the conducting member 30 and the conductive bonding material 90. Regarding claim 9, see, for example, paragraph [0045] wherein Tsao discloses the second barrier layer 25 may be Ni. Regarding claim 11, see, for example, FIG. 14 wherein Tsao discloses the conducting member 30 and the second barrier layer 25 being in contact with each other. Regarding claim 12, see, for example, FIG. 14 wherein Tsao discloses the conductive bonding material 90 and the second barrier layer 25 being in contact with each other. Regarding claim 14, see, for example, FIG. 14 wherein Tsao discloses the electrode 40’ including a lateral surface facing in a direction perpendicular to the thickness direction. Regarding claim 15, see, for example, FIG. 14 wherein Tsao discloses a conductive pad 20’, and the conductive pad 20’ being greater in size along a direction perpendicular to the thickness direction of the electrode 40’. Regarding claim 16, see, for example, the rejection for claim 1 above, and FIG. 2. wherein Takahashi discloses the electrode 3 having a circular cross section. In view of the 112 rejection above, claim(s) 1 thru 14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2016/0027751 A1 in view of Furman et al. US 2009/0075469 A1 in view of Takahashi US 2014/0264847 A1. Kim discloses (see, for example, FIG. 10) a semiconductor device comprising a semiconductor element 121, element first surface (i.e. bottom surface), element second surface (i.e. top surface), electrode 123, conducting member 42, obverse surface (i.e. top surface), reverse surface (i.e. bottom surface), conductive bonding material 51, and a first barrier layer 125. In FIG. 10, Kim discloses the element first surface (i.e. bottom surface of semiconductor element 121) being further provided with a protective film 127 covering a bottom portion of the electrode 123. Kim does not disclose a resin member that covers at least a portion of the conducting member, the semiconductor element and the conductive bonding material. However, Furman discloses (see, for example, FIG. 1, and paragraph [0067]) a semiconductor device 2a comprising a resin member 16, and being silica epoxy, a type of resin material. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a resin member that covers at least a portion of the conducting member, the semiconductor element and the conductive bonding material in order to protect and improve the overall stability and the mechanical connection within the semiconductor device. Kim in view of Furman does not disclose each of the plurality of electrodes the plurality of electrodes include electrodes arranged in a first row and electrodes arranged in a second row, the first row and the second row being adjacent to each other and each extending in a first direction perpendicular to the thickness direction, the first row and the second row being spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction. However, Takahashi discloses (see, for example, FIG. 2, 5, and 6) a semiconductor device comprising a plurality of electrodes 3 set in adjacent, vertical rows wherein each row contains electrodes that are staggered to the electrodes in the adjacent row. In paragraph [0013], Takahashi discloses how the electrodes are staggered to each other and no electrode is aligned with any electrode in the next column. It would have been obvious to one of ordinary skill in the art, at a time of prior to the effective filing date, to have each of the plurality of electrodes the plurality of electrodes include electrodes arranged in a first row and electrodes arranged in a second row, the first row and the second row being adjacent to each other and each extending in a first direction perpendicular to the thickness direction, the first row and the second row being spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction in order to increase density, and thereby downsize the semiconductor device. Regarding claim 2, see, for example, paragraph [0059] wherein Kim discloses the electrode may be Cu or Al. Regarding claim 3, see, for example, paragraph [0068] wherein Kim discloses the conducting member may include multiple materials such as Cu, etc. Further, it would have been obvious to one of ordinary skill in the art to have the conducting member containing Cu in order to have a material that prevents solder diffusion, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Regarding claim 4, see, for example, paragraph [0060] wherein Kim discloses the first barrier layer may contain Ni. Regarding claim 5, see, for example, paragraph [0071] wherein Kim discloses the first conductive bonding material may contain Sn. Regarding claim 6, see, for example, FIG. 10 wherein Kim discloses the electrode 123 and the first barrier layer 125 being in contact with each other. Regarding claim 7, see, for example, FIG. 10 wherein Kim discloses the conducting bonding material 51/155 and the first barrier layer 125 being in contact with each other. Regarding claim 8, see, for example, FIG. 10 wherein Kim discloses a second barrier layer 43/41. Regarding claim 9, see, for example, paragraph [0068] wherein Kim discloses the barrier layer may be multiple metals including Ni. Regarding claim 10, see, for example, FIG. 10 wherein Kim discloses a base layer 41, and auxiliary layer 43. Regarding claim 11, see, for example, FIG. 10 wherein Kim discloses the conductive member 42 and the second barrier layer 43/41 being in contact with each other. Regarding claim 12, see, for example, FIG. 10 wherein Kim discloses the conductive bonding material 51/57/55 and the second barrier layer 43/41 being in contact with each other. Regarding claim 13, see, for example, FIG. 10 wherein Kim discloses a semiconductor device comprising a semiconductor element 121, electrode 123, conducting member 23, conductive bonding material 31, first barrier layer 45, protective film 127, and second barrier 25. The second barrier 25 is greater in length in a direction perpendicular to the thickness direction than the first barrier layer 45. Also see the rejection for claim 1 above. Regarding claim 14, see, for example, FIG. 10 wherein Kim discloses the electrode 123 including a lateral surface facing in a direction perpendicular to the thickness direction. Regarding claim 16, see, for example, the rejection for claim 1 above, and FIG. 2. wherein Takahashi discloses the electrode 3 having a circular cross section. In view of the 112 rejection above, claim(s) 1, 2, 4 thru 6, 8 thru 10, 12 thru 14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2014/0264843 A1 in view of Furman et al. US 2009/0075469 A1 in view of Takahashi US 2014/0264847 A1. Lin discloses (see, for example, FIG. 3) a semiconductor device comprising a semiconductor element 10, element first surface (i.e. bottom surface), element second surface (i.e. top surface), electrode 14, conducting member 141, obverse surface (i.e. top surface), reverse surface (i.e. bottom surface), conductive bonding material 50, and a first barrier layer 20. In FIG. 3, Lin discloses the element first surface (i.e. bottom surface of semiconductor element 10) being further provided with a protective film 12 covering a portion of the electrode 14. Kim does not disclose a resin member that covers at least a portion of the conducting member, the semiconductor element and the conductive bonding material. However, Furman discloses (see, for example, FIG. 1, and paragraph [0067]) a semiconductor device 2a comprising a resin member 16, and being silica epoxy, a type of resin material. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a resin member that covers at least a portion of the conducting member, the semiconductor element and the conductive bonding material in order to protect and improve the overall stability and the mechanical connection within the semiconductor device. Lin in view of Furman does not disclose each of the plurality of electrodes the plurality of electrodes include electrodes arranged in a first row and electrodes arranged in a second row, the first row and the second row being adjacent to each other and each extending in a first direction perpendicular to the thickness direction, the first row and the second row being spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction. However, Takahashi discloses (see, for example, FIG. 2, 5, and 6) a semiconductor device comprising a plurality of electrodes 3 set in adjacent, vertical rows wherein each row contains electrodes that are staggered to the electrodes in the adjacent row. In paragraph [0013], Takahashi discloses how the electrodes are staggered to each other and no electrode is aligned with any electrode in the next column. It would have been obvious to one of ordinary skill in the art, at a time of prior to the effective filing date, to have each of the plurality of electrodes the plurality of electrodes include electrodes arranged in a first row and electrodes arranged in a second row, the first row and the second row being adjacent to each other and each extending in a first direction perpendicular to the thickness direction, the first row and the second row being spaced apart from each other in a second direction perpendicular to the thickness direction and the first direction, and the electrodes in the first row are staggered relative to the electrodes in the second row along the first direction in order to increase density, and thereby downsize the semiconductor device. Regarding claim 2, see, for example, paragraph [0017] wherein Lin discloses the electrode 14 may be Cu. Regarding claim 4, see, for example, paragraph [0020] wherein Lin discloses the first barrier layer 20 may contain Ni. Regarding claim 5, see, for example, paragraph [0030] wherein Lin discloses the first conductive bonding material 50 may be solder, which contain Sn. Regarding claim 6, see, for example, FIG. 3 wherein Lin discloses the electrode 14 and the first barrier layer 20 being in contact with each other. Regarding claim 8, see, for example, FIG. 3 wherein Lin discloses a second barrier layer 24/26. Regarding claim 9, see, for example, paragraph [0022] wherein Lin discloses the second barrier layer 24/26 may include Ni. Regarding claim 10, see, for example, FIG. 3 wherein Lin discloses a base layer 24, and auxiliary layer 26. Regarding claim 12, see, for example, FIG. 3 wherein Lin discloses the conductive bonding material 50 and the second barrier layer 24/26 being in contact with each other. Regarding claim 13, see, for example, FIG. 3 wherein Lin discloses the second barrier 24/26 being greater in length in a direction parallel to the thickness direction of the first barrier layer 20. Regarding claim 14, see, for example, FIG. 3 wherein Lin discloses the electrode 14 including a lateral surface facing in a direction perpendicular to the thickness direction. Regarding claim 16, see, for example, the rejection for claim 1 above, and FIG. 2. wherein Takahashi discloses the electrode 3 having a circular cross section. Response to Arguments Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached on 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee June 16, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Sep 12, 2022
Application Filed
Apr 21, 2025
Non-Final Rejection mailed — §103, §112
Jul 18, 2025
Response Filed
Sep 30, 2025
Final Rejection mailed — §103, §112
Dec 29, 2025
Request for Continued Examination
Jan 22, 2026
Response after Non-Final Action
Jun 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684826
AVALANCHE-PROTECTED TRANSISTORS USING A BOTTOM BREAKDOWN CURRENT PATH AND METHODS OF FORMING THE SAME
3y 12m to grant Granted Jul 14, 2026
Patent 12677650
SEMICONDUCTOR STRUCTURES AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
3y 0m to grant Granted Jul 07, 2026
Patent 12666995
PACKAGE STRUCTURE
2y 10m to grant Granted Jun 23, 2026
Patent 12652964
A-axis Josephson Junctions with Improved Contacts
2y 3m to grant Granted Jun 09, 2026
Patent 12641833
THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND CIRCUIT
3y 2m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+5.4%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 907 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month