DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 01/30/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 01/30/2026 in reply to the final rejection mailed on 11/07/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Applicant adds claims 24 & 25. Claims 14, 16, 17, 18, & 20 are canceled. Accordingly, claims 1-13, 15, 19, & 21-25 will be examined in this Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 4, 5, 8, 11 12, 13, 15, 21, 22, & 24 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Larisegger (US 20190304884) & Toyoda (JP 2003152015), and further in view of Shiraishi (US 20150069613).
Regarding Claim 1, Umeki (see, e.g., figs. 9-12, fig. 24, para.0378) shows a semiconductor package 201 comprising:
a semiconductor device 1 (see, e.g., figs. 9-12) also labeled as 202b (see, e.g., fig. 24, para.0378):
and a bonding wire 249f (see, e.g., para.0202, para.0423) that is electrically connected to the semiconductor device;
wherein the semiconductor device includes
a semiconductor layer 2 that has a first main surface 3 at one side and a second main surface 4 at another side (see, e.g., para.0013);
a first main surface electrode that includes
a first electrode 13 (see, e.g., para.0190) covering the first main surface
and a second electrode (see, e.g., para.0202) having a higher hardness than the first electrode and covering the first electrode;
wherein the bonding wire is electrically and mechanically connected to the second electrode of the first main surface electrode,
Umeki, however, fails to show,
and an oxide layer that covers the first main surface electrode.
wherein the bonding wire penetrates through the oxide layer and is electrically and mechanically connected to the second electrode of the first main surface electrode,
the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode,
and the first main surface electrode has a covered portion covered by the oxide layer
and the connected portion directly connected to the bonding wire.
Larisegger (see, e.g., fig. 4, para.0036, para.0055), in a similar device to Umeki, teaches that an oxide layer 400 that covers an electrode 300 during bonding between a wire 360 and the electrode would provide a reliable corrosion protection coating of the electrode.
Toyoda (see, e.g., fig. 9b, para.0104-0105), in a similar device to Umeki, teaches a configuration for bonding a wire 114 to an electrode 112, wherein the wire penetrates through an oxide layer 113 and is electrically and mechanically connected to the electrode.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Toyoda as evidenced by Larisegger, in the device of Umeki, as a suitable configuration for the bonding wire, the electrode, and the oxide layer to provide a reliable corrosion protection coating of the electrode.
Umeki, in view of Larisegger & Toyoda, fail to explicitly show
a front surface of the second electrode is higher in flatness than a surface of the first electrode,
and a difference between a highest position and a lowest position in a thickness direction of the second electrode is smaller than a difference between a highest position and a lowest position in a thickness direction of the first electrode
Shiraishi (see, e.g., fig. 2, annotated figure 2, para.0035), in a similar device to Umeki, in view of Larisegger & Toyoda, teaches a suitable and obvious configuration for the limitations:
a front surface of the second electrode 25b & 26 is higher in flatness than a surface of the first electrode 23, 24, 25a (see, e.g., annotated figure 3),
and a difference between a highest position and a lowest position in a thickness direction of the second electrode 25b & 26 (1 µm + 50 nm, see, e.g., para.0035, para.0045) is smaller than a difference between a highest position and a lowest position in a thickness direction of the first electrode 23, 24, 25a (8 µm, see, e.g., para.00035, para.0045)
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Shiraishi, in the device of Umeki, in view of Larisegger & Toyoda, as a suitable and obvious configuration for the flatness and difference in highest and lowest positions in a thickness direction of the first and second electrodes.
Regarding Claim 2, Umeki, in view of Larisegger (see, e.g., para.0038) & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 1,
wherein the oxide layer is constituted of a metal oxide layer 400 that includes a metal oxide.
Larisegger (see, e.g., para.0038) states metal oxide layer 400 is made of a copper oxide.
Regarding Claim 3, Umeki (see, e.g., para.0190), in view of Larisegger (see, e.g., para.0038) & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 1,
wherein the oxide layer includes an oxide of the first main surface electrode.
Umeki (see, e.g., para.0190) states the first main surface electrode can comprise copper, and Larisegger (see, e.g., para.0038) states the oxide layer can be copper oxide
Regarding Claim 4, Umeki, in view of Larisegger (see, e.g., para.0038) & Toyoda, and further in view of Shiraishi (see, e.g., para.0035, para.0045), shows the semiconductor package according to Claim 1,
wherein the oxide layer is thinner than the first main surface electrode.
Larisegger (see, e.g., para.0038) states the copper oxide layer can be 50 nm, and Shiraishi (see, e.g., para.0035, para.0045) states the second electrode of the first main surface electrode can be 1 µm + 50 nm. Thus the oxide layer is thinner than the first main surface electrode.
Regarding Claim 5, Umeki, in view of Larisegger (see, e.g., para.0038) & Toyoda, and further in view of Shiraishi (see, e.g., para.0035, para.0045), shows the semiconductor package according to Claim 1,
wherein the oxide layer is thinner than the second electrode.
Larisegger (see, e.g., para.0038) states the copper oxide layer can be 50 nm, and Shiraishi (see, e.g., para.0035, para.0045) states the second electrode of the first main surface electrode can be 1 µm + 50 nm.
Regarding Claim 8, Umeki, in view of Larisegger & Toyoda, and further in view of Shiraishi (see, e.g., para.0036), shows the semiconductor package according to Claim 1,
wherein the second electrode is constituted of a plating layer 25b (see, e.g., para.0036).
Regarding Claim 11, Umeki (see, e.g., fig. 9, para.0103), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 1,
wherein the semiconductor device further includes a functional device 35 that is formed in the semiconductor layer;
and wherein the first main surface electrode is electrically connected to the functional device (see, e.g., para.0192).
Regarding Claim 12, Umeki (see, e.g., fig. 9, para.0103), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 11,
wherein the functional device includes a transistor that has a source region 49
and the first main surface electrode includes a source electrode 91 that is electrically connected to the source region of the transistor (see, e.g., para.0192).
Regarding Claim 13, Umeki (see, e.g., fig. 11, para.0103), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 11,
wherein the functional device includes a transistor that has a gate electrode layer 41 & 41a
and the first main surface electrode includes a gate electrode 14 that is electrically connected to the gate electrode layer of the transistor (see, e.g., para.0172).
Regarding Claim 15, Umeki (see, e.g., para.0078), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 1,
wherein the semiconductor device further includes
a second main surface electrode 32 that covers the second main surface.
Regarding Claim 21, Umeki (see, e.g., figs. 9-12, para.0163), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to claim 1,
wherein the semiconductor device further includes
an interlayer insulating layer 79 that covers the first main surface,
and the first main surface electrode covers the interlayer insulating layer.
Regarding Claim 22, Umeki (see, e.g., fig. 24), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to claim 1 further comprising:
a pad portion 232 (see, e.g., para.0395);
a terminal 237 (see, e.g., para.0404) that is arranged at an interval from the pad portion
the semiconductor device that is arranged on the pad portion
the bonding wire 249f that is electrically connected to the terminal and the semiconductor device (see, e.g., para.0423);
and a sealing resin 204 that seals the pad portion, the terminal, the semiconductor device and the bonding wire (see, e.g., para.0379).
Regarding Claim 24, Umeki (see, e.g., para.0015), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the semiconductor package according to Claim 1,
wherein the semiconductor layer has a thickness of not more than 150 µm (see, e.g., para.0015).
Claims 6 & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Larisegger (US 20190304884), Toyoda (JP 2003152015), Shiraishi (US 20150069613), and further in view of Tatsumi (US 20140327018).
Regarding Claim 6, Umeki (see, e.g., para.0202), in view of Larisegger (see, e.g., pg. 6, col. 4, ll. 30-35), Toyoda, & Shiraishi, shows the semiconductor package according to Claim 1,
Umeki (see, e.g., para.0202) teaches the second electrode can be nickel.
Umeki, in view of Larisegger & Toyoda, however, fails to show
wherein the oxide layer includes an oxide of the second electrode.
Tatsumi (see, e.g., fig. 1, para.0036), in a similar device to Umeki, in view of Larisegger, Toyoda, & Shiraishi, teaches that nickel oxide can be used as a suitable and obvious material for the oxide layer covering a bonding wire and electrode.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the nickel oxide of Tatsumi, in the device of Umeki, in view of Larisegger, Toyoda, & Shiraishi, as a suitable and obvious material for the oxide layer covering a bonding wire and electrode.
Regarding Claim 7, Umeki (see, e.g., para.0202), in view of Larisegger (see, e.g., para.0038),Toyoda, & Shiraishi, and further in view of Tatsumi (see, e.g., fig. 1, para.0036), shows the semiconductor package according to Claim 6,
wherein the second electrode includes at least one among nickel and copper
and the oxide layer includes an oxide of at least one among nickel and copper.
Claims 9 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Larisegger (US 20190304884), Toyoda (JP 2003152015), & Shiraishi (US 20150069613) and further in view of Shimizu (US 20190067423).
Regarding Claim 9, Umeki, in view of Larisegger, Toyoda, & Shiraishi, shows the semiconductor package according to Claim 1,
Umeki, in view of Larisegger, Toyoda, & Shiraishi, however, fails to show
wherein the semiconductor layer includes a wide bandgap semiconductor as a main component.
Shimizu (see, e.g., para.0003, para.0024), in a similar device to Umeki, in view of Larisegger, Toyoda, & Shiraishi, teaches that a wide bandgap semiconductor as a main component would have a large breakdown field strength and a high thermal conductivity.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the wide bandgap semiconductor as a main component of Shimizu, in the device of Umeki, in view of Larisegger, Toyoda, & Shiraishi, to have a large breakdown field strength and a high thermal conductivity.
Regarding Claim 10, Umeki (see, e.g., para.0065), in view of Larisegger, Toyoda, & Shiraishi, shows the semiconductor package according to Claim 1,
wherein the semiconductor layer includes SiC as a main component.
Umeki, in view of Larisegger, Toyoda, & Shiraishi, however, fails to show
wherein the semiconductor layer includes SiC as a main component.
Shimizu (see, e.g., para.0003, para.0024), in a similar device to Umeki, in view of Larisegger, Toyoda, & Shiraishi, teaches that SiC as a main component would have a large breakdown field strength and a high thermal conductivity.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the SiC as a main component of Shimizu, in the device of Umeki, in view of Larisegger, Toyoda, & Shiraishi, to have a large breakdown field strength and a high thermal conductivity.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Larisegger (US 20190304884), Toyoda (JP 2003152015), & Shiraishi (US 20150069613) and further in view of Aketa (US 20160254357).
Regarding Claim 23, Umeki (see, e.g., fig. 24), in view of Larisegger, Toyoda & Shiraishi, shows the semiconductor package according to claim 22,
the semiconductor device is electrically connected to the pad portion (see, e.g., para.0402)
Umeki, in view of Larisegger, Toyoda & Shiraishi, however,
fails to show wherein the pad portion is made of a metal plate (see, e.g., para.0397),
Aketa (see, e.g., para.0060) in a similar device to Umeki, in view of Larisegger & Toyoda, teaches a metal plate would be a suitable and obvious material for forming the pad portion.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the metal plate of Aketa, in the device of Umeki, in view of Larisegger, Toyoda & Shiraishi, as a suitable and obvious material for forming the pad portion.
Claims 19 & 25 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Larisegger (US 20190304884) & Toyoda (JP 2003152015), and further in view of Shiraishi (US 20150069613).
Regarding Claim 19, Umeki (see, e.g., figs. 9-12, figs. 20a-20t. fig. 24, para.0378) shows a method for manufacturing a semiconductor package 201 comprising:
a step of manufacturing a semiconductor device 1 (see, e.g., figs. 9-12) also labeled as 202b (see, e.g., fig. 24, para.0378);
and a step of connecting a bonding wire to the semiconductor device 249f (see, e.g., para.0202, para.0423);
wherein the step of manufacturing the semiconductor device includes;
a step of preparing a semiconductor layer 2 having a main surface 3;
a step of forming a first main surface electrode that includes
a first electrode 13 (see, e.g., para.0190)
and a second electrode (see, e.g., para.0202) on the main surface,
by forming the first electrode on the main surface
and forming the second electrode having a higher hardness than the first electrode on the first electrode;
wherein the bonding wire is electrically and mechanically connected to the second electrode of the first main surface electrode in the step of connecting the bonding wire,
Umeki (see, e.g., para.0202) teaches a nickel electrode layer as “a second electrode” that is formed with the bonding wire 249f. The nickel electrode layer of Umeki is positioned such that it would comprise the outer surface of the first main surface electrode.
Umeki, however, fails to show,
and a step of forming an oxide layer that covers an outer surface of the first main surface electrode.
wherein the bonding wire penetrates through the oxide layer and is electrically and mechanically connected to the second electrode of the first main surface electrode in the step of connecting the bonding wire,
the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode in the step of connecting the bonding wire,
and the first main surface electrode has a covered portion covered by the oxide layer
and the connected portion directly connected to the bonding wire is formed in the step of connecting the bonding wire.
Larisegger (see, e.g., pg. 6, col. 4, ll. 35-39), in a similar method to Umeki, teaches that an oxide layer 400 that covers an electrode 300 during bonding between a wire 360 and the electrode would provide a reliable corrosion protection coating of the electrode.
Toyoda (see, e.g., fig. 9b, para.0104-0105), in a similar method to Umeki, teaches a configuration for bonding a wire 114 to an electrode 112, wherein the wire penetrates through an oxide layer 113 and is electrically and mechanically connected to the electrode.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Toyoda as evidenced by Larisegger, in the method of Umeki, as a suitable configuration for the bonding wire, the electrode, and the oxide layer to provide a reliable corrosion protection coating of the electrode.
Umeki, in view of Larisegger & Toyoda, however, fails to show
a front surface of the second electrode is higher in flatness than a surface of the first electrode,
and a difference between a highest position and a lowest position in a thickness direction of the second electrode is smaller than a difference between a highest position and a lowest position in a thickness direction of the first electrode
Shiraishi (see, e.g., fig. 2, annotated figure 2, para.0035), in a similar device to Umeki, in view of Larisegger & Toyoda, teaches a suitable and obvious configuration for the limitations:
a front surface of the second electrode 25b & 26 is higher in flatness than a surface of the first electrode 23, 24, 25a (see, e.g., annotated figure 3),
and a difference between a highest position and a lowest position in a thickness direction of the second electrode 25b & 26 (1 µm + 50 nm, see, e.g., para.0035, para.0045) is smaller than a difference between a highest position and a lowest position in a thickness direction of the first electrode 23, 24, 25a (8 µm, see, e.g., para.00035, para.0045)
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Shiraishi, in the method of Umeki, in view of Larisegger & Toyoda, as a suitable and obvious configuration for the flatness and difference in highest and lowest positions in a thickness direction of the first and second electrodes.
Regarding Claim 25, Umeki (see, e.g., para.0015), in view of Larisegger & Toyoda, and further in view of Shiraishi, shows the method according to Claim 19,
wherein the semiconductor layer has a thickness of not more than 150 µm (see, e.g., para.0015).
Response to Arguments
Applicant’s arguments, see pages 9-17, filed on 01/30/2026, with respect to the prior art rejections under 35 U.S.C. 103 have been considered but are moot because the new grounds of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814