Prosecution Insights
Last updated: October 02, 2026
Application No. 17/911,424

SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHODS FOR MANUFACTURING THESE

Final Rejection §103
Filed
Sep 14, 2022
Priority
May 08, 2020 — JP 2020-082702 +1 more
Examiner
RAMOS-DIAZ, FERNANDO JOSE
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
4 (Final)
82%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
14 granted / 17 resolved
+14.4% vs TC avg
Minimal +2% lift
Without
With
+1.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
44.5%
+4.5% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§103
DETAILED ACTION/EXAMINER’S COMMENT This Office action responds to the amendments filed on 05/12/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status Applicant’s response filed on 05/12/2026 in reply to the non-final rejection mailed on 02/19/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claim(s) 1-13, 15, 19, & 21-25. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 3, 4, 5, 6, 7, 8, 11 12, 13, 15, 21, 22, & 24 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Sugahara (JP 2016115735) and further in view of Haga (US 20180005981) Regarding Claim 1, Umeki (see, e.g., para.0378) states the semiconductor device 1 of the first embodiment (see, e.g., figs. 1 & 9-12) is applied to the semiconductor device 202b of the semiconductor package 201. Figs. 1, 9-12, & 24 are used in conjunction for the following rejection. The reference number 1/202b will be used to describe the semiconductor device. Umeki (see, e.g., figs. 9-12, fig. 24, para.0378) shows a semiconductor package comprising: a semiconductor device 1/202b (see, e.g., figs. 9-12, para.0378); and a bonding wire 249f (see, e.g., para.0202, para.0423) that is electrically connected to the semiconductor device; wherein the semiconductor device includes: a semiconductor layer 2 (see, e.g., para.0011) that has a first main surface 3 (see, e.g., para.0013) at one side and a second main surface 4 (see, e.g., para.0013) at another side; a first main surface electrode 13 (see, e.g., para.0190) Umeki, however, fails to show the first main surface electrode that includes a first electrode covering the first main surface and a second electrode having a higher hardness than that of the first electrode and covering the first electrode; and an oxide layer that covers the first main surface electrode; and wherein the bonding wire penetrates through the oxide layer and is electrically and mechanically connected to the second electrode of the first main surface electrode, the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode, the first main surface electrode has a covered portion covered by the oxide layer and the connected portion directly connected to the bonding wire, the first electrode has a front surface having an uneven portion with height variations, the second electrode covers the first electrode so as to embed the uneven portion of the first electrode, and has a front surface higher in flatness than the front surface of the first electrode, and a difference between a highest position and a lowest position on the front surface of the second electrode is smaller than a difference between a highest position and a lowest position on the front surface of the first electrode. Sugahara (see, e.g., fig. 3, para.0025, para.0027, para.0036, para.0135), in a similar device to Umeki, teaches the first main surface electrode 10 that includes a first electrode 52a (aluminum, see, e.g., para.0036) covering the first main surface and a second electrode 53a (nickel, see, e.g., para.0027) having a higher hardness than that of the first electrode and covering the first electrode (nickel has a higher Mohs hardness and Vickers hardness than aluminum); the first electrode has a front surface (hereinafter referred to as “FS1”) having an uneven portion with height variations (see, e.g., annotated figure 1), the second electrode covers the first electrode so as to embed the uneven portion of the first electrode (see, e.g., annotated figure 1), and has a front surface (hereinafter referred to as “FS2”) higher in flatness than the front surface of the first electrode FS1, PNG media_image1.png 685 1559 media_image1.png Greyscale and a difference between a highest position and a lowest position on the front surface FS2 of the second electrode is smaller than a difference between a highest position and a lowest position on the front surface FS1 of the first electrode (see, e.g., annotated figure 1). The first main surface electrode 10 of Sugahara (see, e.g., para.0025) and the first main surface electrode 13 of Umeki (see, e.g., para.0013) both serve the purpose of providing an electrical connection to the transistors of a semiconductor device. The configuration of the first main surface electrode 10 of Sugahara is incorporated into the device of Umeki. It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Sugahara in the device of Umeki because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of one surface electrode for another for the purpose of providing electrical connection to the transistors of a semiconductor device. Umeki, in view of Sugahara, however, fails to show and an oxide layer that covers the first main surface electrode; and wherein the bonding wire penetrates through the oxide layer and is electrically and mechanically connected to the second electrode of the first main surface electrode, the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode, Haga (see, e.g., fig. 208, para.1565, para.1594), in a similar device to Umeki, in view of Sugahara, teaches and an oxide layer 37q that covers the first main surface electrode 33q & 25q (see, e.g., para.1565); and wherein the bonding wire 54q, 55q, & 56q (see, e.g., para.1594) penetrates through the oxide layer and is electrically and mechanically connected to the second electrode 33q of the first main surface electrode, the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode (see, e.g., annotated figure 2), PNG media_image2.png 720 1113 media_image2.png Greyscale Haga (see, e.g., fig. 208, para.1568) in a similar device to Umeki, in view of Sugahara, states the copper oxide layer 37q would naturally form as a result of the copper second electrode 33q being exposed. Therefore connection between the bonding wire and the second electrode would require penetrating the copper oxide layer. Sugahara (see, e.g.., fig. 3, para.0135) shows the second electrode 53a of the first main surface electrode 10 exposed with no layer covering it. Sugahara states the materials for the main surface electrode 10, aluminum for first electrode 52a and nickel for second electrode 53a, are not limited to aluminum and nickel and can be made of copper. Examiner interprets the second nickel electrode 53a to be made of copper. Copper, still satisfies the limitation “a second electrode 53a having a higher hardness than that of the first electrode 52a” since copper has a higher Mohs hardness and Vickers hardness than aluminum. Umeki (see, e.g., para.0423) states the bonding wire 249f is connected to the first main surface electrode 13 of the semiconductor device 1/202b. The oxide layer of Haga is incorporated into the device of Umeki, in view of Sugahara, for the purpose of providing protection to the exposed area of the second electrode other than the connected portion between the bonding wire and the second electrode It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the oxide layer of Haga in the device of Umeki, in view of Sugahara, for the purpose of providing protection to the exposed area of the second electrode other than the connected portion between the bonding wire and the second electrode. Additionally, the combination is a simple substitution of one known element for another – a simple substitution of an interface of an electrode connected to a bonding wire for the purpose of providing electrical connection. Regarding Claim 2, Umeki, in view of Sugahara and further in view of Haga (see, e.g., para.1568), shows the semiconductor package according to Claim 1, wherein the oxide layer 37q is constituted of a metal oxide layer (copper oxide layer) that includes a metal oxide (copper oxide, see, e.g., para.1568). Regarding Claim 3, Umeki, in view of Sugahara (see, e.g., para.0135) and further in view of Haga (see, e.g., para.1568), shows the semiconductor package according to Claim 1, wherein the oxide layer includes an oxide (copper oxide, see, e.g., para.1568) of the first main surface electrode (second electrode 53a is selected to be copper, see, e.g., para.0135, paragraph 15 of claim 1 rejection). Regarding Claim 4, Umeki, in view of Sugahara (see, e.g., fig. 3, fig. 12, fig. 15, para.0084, para.0087) and further in view of Haga (see, e.g., para.1568), shows the semiconductor package according to Claim 1, wherein the oxide layer 37q is thinner (10-50 nm, see, e.g., para.1568) than the first main surface electrode (see, e.g., fig. 3, fig. 12, fig. 15, para.0084, para.0087). Sugahara (see, e.g., fig. 12, fig. 15, para.0084, para.0087) shows the formation of the first electrode 52a and the second electrode 53a of the first main surface electrode 10 embodiment in fig. 3 used in the rejection of Claim 1. Sugahara states the first electrode 52a has a thickness of 3.5 µm and the second electrode 53a has thickness of 10 µm. The thickness of the oxide layer 37q as recited in Haga (see, e.g., para.1568) is between 10-50 nm and is therefore thinner than the first main surface electrode. Regarding Claim 5, Umeki, in view of Sugahara (see, e.g., fig. 3, fig. 15, para.0087) and further in view of Haga (see, e.g., para.1568), shows the semiconductor package according to Claim 1, wherein the oxide layer is thinner (10-50 nm, see, e.g., para.1568) than the second electrode (see, e.g., fig. 3, fig. 15, para.0087). Sugahara (see, e.g., fig. 15, para.0087) shows the formation of the second electrode 53a of the first main surface electrode 10 embodiment in fig. 3 used in the rejection of Claim 1. Sugahara states the second electrode 53a has thickness of 10 µm. The thickness of the oxide layer 37q as recited in Haga (see, e.g., para.1568) is between 10-50 nm and is therefore thinner than the second electrode. Regarding Claim 6, Umeki, in view of Sugahara (see, e.g., para.0135) and further in view of Haga (see, e.g., para.1568), shows the semiconductor package according to Claim 1, wherein the oxide layer (copper oxide, see, e.g., para.1568) includes an oxide of the second electrode (second electrode 53a is selected to be copper, see, e.g., para.0135, paragraph 15 of claim 1 rejection). Regarding Claim 7, Umeki, in view of Sugahara (see, e.g., para.0135) and further in view of Haga (see, e.g., para.1568), shows the semiconductor package according to Claim 6, wherein the second electrode 53a includes at least one among nickel and copper (second electrode 53a is selected to be copper, see, e.g., para.0135, paragraph 15 of claim 1 rejection) and the oxide layer includes an oxide of at least one among nickel and copper (copper oxide, see, e.g., para.1568). Regarding Claim 8, Umeki, in view of Sugahara (see, e.g., fig. 3, fig. 15, para.0087) and further in view of Haga, shows the semiconductor package according to Claim 8, wherein the second electrode 53a is constituted of a plating layer (see, e.g., para.0087). Sugahara (see, e.g., fig. 15, para.0087) shows the formation of the second electrode 53a of the first main surface electrode 10 embodiment in fig. 3 used in the rejection of Claim 1. Sugahara states the second electrode 53a is formed from electroless plating and therefore is interpreted to be constituted of a plating layer. Regarding Claim 11, Umeki (see, e.g., fig. 9, para.0103, para.0192), in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 1, wherein the semiconductor device further includes a functional device 35 (see, e.g., para.0103) that is formed in the semiconductor layer 2, and the first main surface electrode is electrically connected to the functional device (through 49 & 91, see, e.g., para.0192). Regarding Claim 12, Umeki (see, e.g., fig. 9, para.0110, para.0192), in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 11, wherein the functional device includes a transistor that has a source region 49 (see, e.g., para.0110), and the first main surface electrode includes a source electrode 91 that is electrically connected to the source region of the transistor (see, e.g., para.0192). Regarding Claim 13, Umeki (see, e.g., fig. 1, para.0112, para.0172, para.0295), in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 11, wherein the functional device includes a transistor that has a gate electrode layer 41 & 41a (see, e.g., para.0112, para.0172), and the first main surface electrode includes a gate electrode 14 (see, e.g., fig. 1, para.0295) that is electrically connected to the gate electrode layer of the transistor. Regarding Claim 15, Umeki (see, e.g., para.0078), in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 1, wherein the semiconductor device further includes a second main surface electrode 32 (see, e.g., para.0078) that covers the second main surface 4. Regarding Claim 21, Umeki (see, e.g., fig. 9, para.0163), in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 1, wherein the semiconductor device further includes an interlayer insulating layer 79 (see, e.g., para.0163) that covers the first main surface 3, and the first main surface electrode covers the interlayer insulating layer. Regarding Claim 22, Umeki, in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 1, further comprising: a pad portion 232 (see, e.g., para.0395); a terminal 237 (see, e.g., para.0404) that is arranged at an interval from the pad portion the semiconductor device that is arranged on the pad portion the bonding wire 249f that is electrically connected to the terminal (249f electrically connected to 233 which is electrically connected to 237) and the semiconductor device (see, e.g., para.0423); and a sealing resin 204 that seals the pad portion, the terminal, the semiconductor device and the bonding wire (see, e.g., para.0379). Regarding Claim 24, Umeki (see, e.g., para.0015), in view of Sugahara and further in view of Haga, shows the semiconductor package according to Claim 1, wherein the semiconductor layer 2 has a thickness of not more than 150 µm (50 µm, see, e.g., para.0015). Claims 9 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Sugahara (JP 2016115735) & Haga (US 20180005981) and further in view of Shimizu (US 20190067423). Regarding Claim 9, Umeki, in view of Sugahara & Haga, shows the semiconductor package according to Claim 1, Umeki, in view of Sugahara & Haga, however, fails to show wherein the semiconductor layer includes a wide bandgap semiconductor as a main component. Shimizu (see, e.g., para.0003, para.0024), in a similar device to Umeki, in view of Sugahara & Haga, teaches that a wide bandgap semiconductor as a main component would have a large breakdown field strength and a high thermal conductivity. It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the wide bandgap semiconductor as a main component of Shimizu, in the device of Umeki, in view of Sugahara & Haga, to have a large breakdown field strength and a high thermal conductivity. Regarding Claim 10, Umeki, in view of Sugahara & Haga, shows the semiconductor package according to Claim 1, Umeki, in view of Sugahara & Haga, however, fails to show wherein the semiconductor layer includes SiC as a main component. Shimizu (see, e.g., para.0003, para.0024), in a similar device to Umeki, in view of Sugahara & Haga, teaches that SiC as a main component would have a large breakdown field strength and a high thermal conductivity. It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the SiC as a main component of Shimizu, in the device of Umeki, in view of Sugahara & Haga, to have a large breakdown field strength and a high thermal conductivity. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Sugahara (JP 2016115735) & Haga (US 20180005981) and further in view of Aketa (US 20160254357). Regarding Claim 23, Umeki (see, e.g., fig. 24, para.0402), in view of Sugahara & Haga, shows the semiconductor package according to Claim 22, and the semiconductor device 1/202b is electrically connected to the pad portion (see, e.g., para.0402). Umeki, in view of Sugahara & Haga, however, fails to show wherein the pad portion 232 is made of a metal plate, Aketa (see, e.g., para.0060) in a similar device to Umeki, in view of Sugahara & Haga, teaches a metal plate would be a suitable material for forming a pad portion 203. The metal plate is incorporated into the device of Umeki, in view of Sugahara & Haga, as the material for the pad portion 232. It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the metal plate of Aketa, in the device of Umeki, in view of Sugahara & Haga because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the material of one know pad portion for another. Claims 19 & 25 are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (WO 2020080476) in view of Sugahara (JP 2016115735) and further in view of Haga (US 20180005981). Umeki (see, e.g., para.0378) states the semiconductor device 1 of the first embodiment (see, e.g., figs. 1 & 9-12, 20a-t) is applied to the semiconductor device 202b of the semiconductor package 201. Figs. 20a-t show the manufacturing steps for the semiconductor of Figs. 1, 9-12, & 24. Figs. 1, 9-12, 20a-20t & 24 are used in conjunction for the following rejection. The reference number 1/202b will be used to describe the semiconductor device. Regarding Claim 19. (Currently Amended) A method for manufacturing a semiconductor package comprising: a step of manufacturing a semiconductor device 1/202b (see, e.g., figs. 20a-t); and a step of connecting a bonding wire 249f to the semiconductor device (see, e.g., para.0202); wherein the step of manufacturing the semiconductor device includes: a step of preparing a semiconductor layer having a main surface 163 (corresponds to 3 of fig. 9, see, e.g., fig. 20a, para.0013); a step of forming a first main surface electrode 13 (see, e.g., fig. 20q) Umeki, however, fails to show the step of forming the first main surface electrode that includes a first electrode and a second electrode on the main surface, by forming the first electrode on the main surface and forming the second electrode having a higher hardness than that of the first electrode on the first electrode; and a step of forming an oxide layer that covers an outer surface of the first main surface electrode; and wherein the bonding wire penetrates through the oxide layer and is electrically and mechanically connected to the second electrode of the first main surface electrode in the step of connecting the bonding wire, the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode in the step of connecting the bonding wire, the first main surface electrode that has a covered portion covered by the oxide layer and the connected portion directly connected to the bonding wire is formed in the step of connecting the bonding wire, the first electrode has a front surface having an uneven portion with height variations, the second electrode covers the first electrode so as to embed the uneven portion of the first electrode, and has a front surface higher in flatness than the front surface of the first electrode, and a difference between a highest position and a lowest position on the front surface of the second electrode is smaller than a difference between a highest position and a lowest position on the front surface of the first electrode. Sugahara (see, e.g., fig. 3, para.0025, para.0027, para.0036, para.0135), in a similar method to Umeki, teaches the step of forming the first main surface electrode 10 that includes a first electrode 52a (aluminum, see, e.g., para.0036) and a second electrode 53a (nickel, see, e.g., para.0027) on the main surface, by forming the first electrode on the main surface and forming the second electrode having a higher hardness than that of the first electrode on the first electrode (nickel has a higher Mohs hardness and Vickers hardness than aluminum); the first electrode has a front surface (hereinafter referred to as “FS1”) having an uneven portion with height variations (see, e.g., annotated figure 1), the second electrode covers the first electrode so as to embed the uneven portion of the first electrode (see, e.g., annotated figure 1), and has a front surface (hereinafter referred to as “FS2”) higher in flatness than the front surface of the first electrode FS1, and a difference between a highest position and a lowest position on the front surface FS2 of the second electrode is smaller than a difference between a highest position and a lowest position on the front surface FS1 of the first electrode (see, e.g., annotated figure 1). The first main surface electrode 10 of Sugahara (see, e.g., para.0025) and the first main surface electrode 13 of Umeki (see, e.g., para.0013) both serve the purpose of providing an electrical connection to the transistors of a semiconductor device. The configuration of the first main surface electrode 10 of Sugahara is incorporated into the method of Umeki. It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Sugahara in the method of Umeki because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of one surface electrode for another for the purpose of providing electrical connection to the transistors of a semiconductor device. Umeki, in view of Sugahara, however, fails to show and a step of forming an oxide layer that covers an outer surface of the first main surface electrode; and wherein the bonding wire penetrates through the oxide layer and is electrically and mechanically connected to the second electrode of the first main surface electrode in the step of connecting the bonding wire, the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode in the step of connecting the bonding wire, the first main surface electrode that has a covered portion covered by the oxide layer and the connected portion directly connected to the bonding wire is formed in the step of connecting the bonding wire, Haga (see, e.g., fig. 208, para.1565, para.1594), in a similar method to Umeki, in view of Sugahara, teaches and a step of forming an oxide layer 37q that covers an outer surface of the first main surface electrode 33q & 25q (see, e.g., para.1565); and wherein the bonding wire 54q, 55q, & 56q (see, e.g., para.1594) penetrates through the oxide layer and is electrically and mechanically connected to the second electrode 33q of the first main surface electrode in the step of connecting the bonding wire, the oxide layer remains in an area other than a connected portion between the bonding wire and the first main surface electrode in the step of connecting the bonding wire (see, e.g., annotated figure 2), the first main surface electrode that has a covered portion covered by the oxide layer and the connected portion directly connected to the bonding wire is formed in the step of connecting the bonding wire (the connected portion and the covered portion, same as the “area other than a connected portion,” are formed during the connection of the bond wire), Haga (see, e.g., fig. 208, para.1568) in a similar method to Umeki, in view of Sugahara, states the copper oxide layer 37q would naturally form as a result of the copper second electrode 33q being exposed. Therefore connection between the bonding wire and the second electrode would require penetrating the copper oxide layer. Sugahara (see, e.g.., fig. 3, para.0135) shows the second electrode 53a of the first main surface electrode 10 exposed with no layer covering it. Sugahara states the materials for the main surface electrode 10, aluminum for first electrode 52a and nickel for second electrode 53a, are not limited to aluminum and nickel and can be made of copper. Examiner interprets the second nickel electrode 53a to be made of copper. Copper, still satisfies the limitation “a second electrode 53a having a higher hardness than that of the first electrode 52a” since copper has a higher Mohs hardness and Vickers hardness than aluminum. Umeki (see, e.g., para.0423) states the bonding wire 249f is connected to the first main surface electrode 13 of the semiconductor device 1/202b. The oxide layer of Haga is incorporated into the method of Umeki, in view of Sugahara, for the purpose of providing protection to the exposed area of the second electrode other than the connected portion between the bonding wire and the second electrode It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the oxide layer of Haga in the method of Umeki, in view of Sugahara, for the purpose of providing protection to the exposed area of the second electrode other than the connected portion between the bonding wire and the second electrode. Additionally, the combination is a simple substitution of one known element for another – a simple substitution of an interface of an electrode connected to a bonding wire for the purpose of providing electrical connection. Regarding Claim 25, Umeki (see, e.g., para.0015), in view of Sugahara and further in view of Haga, shows the method according to Claim 19, wherein the semiconductor layer 2 has a thickness of not more than 150 µm (50 µm, see, e.g., para.0015). Response to Arguments Applicant’s arguments with respect to claim(s) 1-13, 15, 19, & 21-25 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /F.R.D./ Examiner, Art Unit 2818 Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Show 1 earlier event
Jul 01, 2025
Non-Final Rejection mailed — §103
Oct 01, 2025
Response Filed
Nov 07, 2025
Final Rejection mailed — §103
Jan 30, 2026
Request for Continued Examination
Feb 10, 2026
Response after Non-Final Action
Feb 19, 2026
Non-Final Rejection mailed — §103
May 12, 2026
Response Filed
Aug 11, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
82%
Grant Probability
84%
With Interview (+1.5%)
3y 3m (~0m remaining)
Median Time to Grant
High
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