DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/7/2026 and 2/2/2026 has been entered.
Claims 1, 5-12 and 14-19 are pending. Claims 2-4 and 13 have been canceled. Claim 5 has been withdrawn. Claims 1, 7-9, and 15-16 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6-12, and 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “such that the H ions can passivate a P-type doping ion Mg of the first P-type semiconductor layer so that Mg does not generate holes” renders the claim indefinite. Firstly, it is unclear if recitation to “a P-type doping ion Mg” is requiring Mg as the P-type doping or is Mg merely recited as an exemplary P-type doping ion. Thus, it is unclear if the first P-type semiconductor layer is required to include Mg as the P-type doing ions. Furthermore, “H ions can passivate” is indefinite because if it is unclear if the claim in intended to positively recite the H ions as passivating the P-type doping ion or is merely suggestive in nature. Furthermore, it is unclear how does Mg element itself “generate holes” or “not generate holes” as recited in the claim.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-12, and 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen US 2020/0119085 A1 (Chen’085) in view of Chen US 2013/0032776 A1 (Chen’776).
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In re claim 1, as best understood, Chen’085 discloses (e.g. FIGs. 12A-12B) a semiconductor structure comprising:
a substrate 10;
a heterojunction structure 120 (¶ 105) disposed on the substrate 10, wherein the heterojunction structure 120 comprises a source region (a region including source electrode 132), a drain region (a region including drain electrode 134), and a gate region (a region including gate electrode 136) disposed between the source region (region of 132) and the drain region (region of 134), and wherein the heterojunction structure 120 comprises a channel layer 124 and a potential barrier layer 126 (¶ 105);
a quantum well structure 20 disposed on the potential barrier layer 126, wherein the quantum well structure 20 (including a select portion of located in the drain region, ¶ 43, see FIG. 12A annotated above) is disposed on the drain region of the potential barrier layer 126, and the quantum well structure 20 (FIG. 12B) comprises an N-type semiconductor layer 804 (¶ 28), a first P-type semiconductor layer 1140,1150,1160 (¶ 50-51), and a quantum well layer 1110,1120,1130 disposed between the N-type semiconductor layer 804 and the first P-type semiconductor layer 1140,1150,1160; and
a first drain electrode 30,192 disposed on the quantum well structure (no specific “drain electrode” claimed that would structurally distinguish over metal 30,192 that is connected to the drain region of the HEMT).
Chen’085 discloses the claimed invention including MQW LED structure 20 comprising a P-type semiconductor layer 1150,1160 including p-doped GaN (¶ 50,51) under transparent conductive oxide 964 and electrode 966 (¶ 53-54). Chen’085 does not explicitly disclose the P-type semiconductor layer comprises a hole passivation layer away from the quantum well layer, and the hole passivation layer is formed by injecting H ions into the first P-type semiconductor layer “such that the H ions can passivate a P-type doping ion Mg of the first P-type semiconductor layer so that Mg does not generate holes”.
However, Chen’776 discloses (FIG. 1F) a MQW LED structure 120 comprising a quantum well layer 124 between N-type semiconductor layer 122 and P-type semiconductor layer 126, wherein the P-type semiconductor layer 126 comprises Mg doped GaN (¶ 19), and the P-type semiconductor layer 126 comprises a hole passivation layer 140 away from the quantum well layer 124, and the hole passivation layer 140 is formed by injecting H ions into the first P-type semiconductor layer 126 “such that the H ions can passivate a P-type doping ion Mg of the first P-type semiconductor layer 126 so that Mg does not generate holes” (as best understood, the Mg bond with H to form Mg-H complex would not generate would not contribute to electric hole concentration, ¶ 21-22). Chen’776 teaches the hole passivation layer 140 forms a current blocking layer under the transparent conductive oxide 150 and electrode to evenly distribute current in the LED structure and improve light emitting efficiency (¶ 24).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a hole passivation layer in Chen’085’s P-type GaN layer 1150,1160 to provide a current blocking layer under the transparent conductive oxide 964 and electrode 966 as taught by Chen’776 by injecting H ions into the first P-type semiconductor layer 1150,1160 “such that the H ions can passivate a P-type doping ion Mg of the first P-type semiconductor layer so that Mg does not generate holes”. It would be obvious to provide a hole passivation layer in Chen’085’s P-type GaN layer to efficiently block current under the electrode and achieve even current distribution in the LED structure for improving light emitting efficiency as taught by Chen’776.
In re claim 6, Chen’085 discloses (e.g. FIG. 12A) wherein a material combination of the channel layer 124 and the potential barrier layer 126 comprises (¶ 105): GaN and AIN, GaN and InN, GaN and InAlGaN, GaAs and AlGaAs, GaN and InAIN, or InN and InAIN. Chen’085 teaches (¶ 105) the channel layer 124 can include GaN or InGaAs, and the barrier layer 126 can include AlGaN, InAlAs or AlGaAs. As such, Chen’085 teaches the material combination can be, e.g. GaN and AlGaN (which comprises GaN and AlN as claimed) or InGaAs and AlGaAs (which comprises GaAs and AlGaAs as claimed).
In re claim 7, Chen’085 discloses (e.g. FIGs. 12A & 12B) wherein the gate region (region of the device including gate electrode 136, see annotated in FIG. 12A above) is provided with a dielectric layer 140,170,190 (dielectric layer provided in the “gate region”, ¶ 116). Alternatively, dielectric layer may be 42 (see FIG. 1D) as part of structure 20 in the “gate region”.
In re claim 8, Chen’085 discloses (e.g. FIG. 12B) wherein the quantum well layer 1110,1120,1130 is a single quantum well layer or a multiple quantum well layer.
In re claim 9, Chen’085 discloses (e.g. FIG. 12B) wherein a material of the first P-type semiconductor layer 1140,1150,1160 (¶ 49-51) comprises at least one of GaN, AlGaN, InGaN, or AlInGaN.
In re claim 10, Chen’085 discloses (e.g. FIG. 12A, see annotated above) wherein the source region is provided with a source electrode 132 and the gate region is provided with a gate electrode 136; the source electrode 132 is in ohmic contact with the heterojunction structure 120 (¶ 107), and the first drain electrode 30,192 is in ohmic contact with the quantum well structure (30,192 provide ohmic contact to p-doped side (see FIG. 12B) of the quantum well structure corresponding to the portion annotated in FIG. 12A above), and the gate electrode 136 is in Schottky contact with the heterojunction structure 120 (¶ 105).
In re claim 11, Chen’085 discloses (e.g. FIG. 12A, see annotated above) wherein the drain region is further provided with a second drain electrode 134, and the second drain electrode 134 is in ohmic contact with the heterojunction structure 120 (¶ 107).
In re claim 12, Chen’085 discloses (e.g. FIG. 12A) wherein the first drain electrode 30,192 and the quantum well structure (select portion of 20, see annotated in FIG. 12A above) are electrically insulated from the second drain electrode 134 by an insulating layer (isolation layer 140 in FIG. 12A or dielectric layer 42 shown in FIG. 1D). For example, 30,192 is electrically insulated from 134 by isolation layer 140 (¶ 108). Alternatively, the dielectric layer 42 (¶ 58, see FIG. 1D) insulates 30,192 from 134.
In re claim 14, Chen’085 discloses (e.g. FIG. 1D and 12A) wherein a material of the dielectric layer 42 (provided in the “gate region”) comprises at least one of silicon dioxide or silicon nitride (¶ 58).
In re claim 15, Chen’085 discloses (e.g. FIG. 12B) wherein a material of the N-type semiconductor layer 804 (¶ 28) comprises at least one of GaN, AIGaN, InGaN, or AlInGaN.
In re claim 16, Chen’085 discloses (e.g. FIGs. 12A & 12B) wherein the N-type semiconductor layer 804 is close to the heterojunction structure 120 and the first P-type semiconductor layer 1140,1150,1160 is away from the heterojunction structure 120.
In re claim 17, Chen’085 disclose (e.g. FIG. 12A) wherein the first drain electrode 30,192 and the second drain electrode 134 are “connected in parallel”. The phrase “connected in parallel” is broadly understood to mean a connection between the electrodes and the electrodes are structurally parallel. Chen’085 teaches electrodes 30,192,134 are electrically connected and they are arranged as parallel layers.
In re claim 18, Chen’085 discloses (e.g. FIG. 1D) wherein a material of the insulating layer 42 comprises at least one of silicon dioxide or silicon nitride (¶ 58).
In re claim 19, Chen’085 discloses (e.g. FIGs. 12A-12B) wherein the gate region is further provided with a second P-type semiconductor layer 1140,1150, and the second P-type semiconductor layer 1140,1150 is disposed on the dielectric layer 140. Alternatively, Chen’085 discloses (e.g. FIG. 1D) the second P-type semiconductor layer (lower portion of 1260) is disposed on the dielectric layer 42.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 6-12, and 14-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights