The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2020/0143772).Regarding claims 1 and 15, Lee et al. teach in figure 1 and related text a display substrate comprising:
a base substrate 110,
a plurality of data lines 111, and a crack detection circuit that are disposed on the base substrate;
wherein the base substrate 110 comprises a display region DA and a peripheral region PA surrounding the display region, at least part of the plurality of data lines 171 are disposed on the display region, and
the crack detection circuit comprises a first line being 700-TVL-DT1-N1-DT2-700 and at least one second line 700-DR1-N2-HCD;
wherein two ends of the first line are connected to a controller 700, one end of the at least one second line is connected to the controller 700, and the other end of the at least one second line is connected to at least one of the plurality of data lines HCD.
Lee et al. do not explicitly state that the other end of the second line is connected to at least one of the plurality of data lines.
Lee et al. teach in related text (see e.g. paragraph [0008] that the first detection receiving line is connected to at least one of the plurality of data lines.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect the other end of the second line to at least one of the plurality of data lines, in Lee et al.’s device, in order to be able to operate the device in its intended use.
Regarding claims 2 and 16, Lee et al. teach in figure 6 and related text that the crack detection circuit comprises a first trace, a second trace, and a third trace (arbitrarily chosen), wherein two ends of the first trace and two ends of the second trace are connected to the controller, and the first trace is connected to the second trace via the third trace;
the at least one of the plurality of data lines 171 comprises at least one first data line and at least one second data line, wherein the first trace is connected to the at least one first data line, and the second trace is connected to the at least one second data line (see analysis above);
wherein a first connection portion (arbitrarily chosen) between the first trace and the third trace is proximal to one end of the first trace, and a second connection portion between the first trace and the at least one first data line is proximal to the other end of the first trace; and
a third connection portion between the second trace and the third trace is proximal to one end of the second trace, and a fourth connection portion between the second trace and the at least one second data line is proximal to the other end of the second trace;
the first line successively passes through the other end of the first trace, the first connection portion, the third trace, the third connection portion, and the other end of the second trace (inherently therein); and
the at least one second line comprises two second lines, wherein one of the two second lines successively passes through the one end of the first trace, the first connection portion, and the second connection portion, and the other of the two second lines successively passes through the one end of the second trace, the third connection portion, and the fourth connection portion.
Regarding claims 3 and 17, Lee et al. teach in figure 1 and related text the controller 700 disposed on the peripheral region PA of the base substrate 110;
wherein the at least one of the plurality of data lines 171 extends from the display region to the peripheral region and is connected to the controller 700; and
the controller is configured to: in a first detection phase, detect a resistance in the first line, and determining, based on the resistance, whether a crack is present in a position where the first line passes through in the display substrate; and/or in a second detection phase, provide a data signal to the at least one of the plurality of data lines via the at least one second line (inherently therein).
Regarding claims 4 and 18, Lee et al. teach in figure 1 and related text that the controller 700 disposed on the peripheral region PA of the base substrate;
wherein the at least one of the plurality of data lines 171 extends from the display region to the peripheral region and is connected to the controller; and
the controller is configured to: in the first detection phase, control the one end of the first trace and the one end of the second trace to be in a high resistance state, detect a resistance in the first line from the other end of the first trace and the other end of the second trace, and determine, based on the resistance, whether a crack is present in a position where the first line passes through in the display substrate (see e.g. paragraphs [0080]-[0082]).
Regarding claims 5 and 19, Lee et al. teach in figure 1 and related text that the controller disposed on the peripheral region of the base substrate; wherein the at least one of the plurality of data lines extends from the display region to the peripheral region and is connected to the controller; and the controller is configured to: in the second detection phase, control the other end of the first trace and the other end of the second trace to be in a high resistance state, and provide a data signal to the one end of the first trace and the one end of the second trace (see e.g. paragraphs [0080]-[0082]).
Regarding claims 6 and 20, Lee et al. teach in figure 1 and related text that the first trace passes through a first side and a second side of the display region, the second trace passes through the second side and a third side of the display region, and the third trace is disposed on a fourth side of the display region, wherein the first side is opposite to the third side, and the second side is opposite to the fourth side.
Regarding claim 7, Lee et al. teach in figure 1 and related text that an orthogonal projection of the first trace on a reference plane (arbitrarily chosen) is overlapped with an orthogonal projection of the second trace on the reference plane, wherein the reference plane is intersected with a direction from the second side to the fourth side.
Regarding claim 8, Lee et al. teach in figure 1 and related text that a control line (one of lines connected to pixel PX), a first switch TRa (see figure 2) assembly corresponding to the first data line, and a second switch assembly TRd corresponding to the second data line; wherein the control line, the first switch assembly, and the second switch assembly are disposed on the base substrate, the first data line is connected to the first trace through the corresponding first switch assembly, and the second data line is connected to the second trace through the corresponding second switch assembly; and the control line is connected to both the first switch assembly and the second switch assembly, and two ends of the control line are connected to the controller; and the controller is configured to: in the first detection phase, provide a first signal to the control line, wherein the first signal is configured to control a switch assembly connected to the control line to be in a closed state; in the second detection phase, provide a second signal to the control line, wherein the second signal is configured to control the switch assembly connected to the control line to be in an open state (inherently therein).
Regarding claim 9, Lee et al. teach in figure 1 and related text that the plurality of data lines further comprise: at least one third data line other than the at least one of the plurality of data lines (another 171), wherein at least part of the at least one third data line is disposed on the display region; and the display substrate further comprises: a third switch assembly corresponding to the third data line, wherein the third switch assembly is disposed on the base substrate.
Regarding claim 10, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form each of the first switch assembly, the second switch assembly, and the third switch assembly as a thin-film transistor, in Lee et al.’s device, in order to improve the device characteristics by using conventional thin film transistors.
Regarding claim 11, Lee et al. teach in figure 1 and related text that wherein the controller is a driver integrated circuit IC.
Response to Arguments
1. Applicants argue that “Lee fails to disclose at least the following distinguishing features of amended claim 1: the crack detection circuit comprises a first line and at least one second line; wherein two ends of the first line are connected to a controller, one end of the at least one second line is connected to the controller, and the other end of the at least one second line is connected to at least one of the plurality of data lines”, because “the first loop comprises: P1 -> DT1--N1-> [HCD line body] -- N2 -> DR1-- test controller 700” and “the second loop comprises: P2 - DT2 --N1-[HCD line body] -- N2 -> DR2 -- test controller 700” and thus “no detection loop has both its ends connected to the test controller 700, and no detection loop has one end connected to the test controller 700 and the other end connected to a data line”.
1. Lee teaches that the first loop comprises a first line being 700-TVL-DT1-N1-DT2-700 and at least one second line 700-DR1-N2-HCD, such that the second detection loop has one end connected to the test controller 700 and the other end connected to a data line HCD, as required by the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
2/2/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800