DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2, lines 1-2 recite “materials of the gate line fixing portion and the common electrode are identical metal materials”. Claim 1, from which this line depends, requires that “materials of both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO)” which is a metal oxide material, and not just a “metal material”. It is unclear how both of these limitations can be true simultaneously. This renders the claim indefinite. For the purposes of examination, the examiner will interpret the limitation as “materials of the gate line fixing portion and the common electrode are identical materials which contain metal”.
Claim 12, lines 1-2 recite “materials of the gate line fixing portion and the common electrode are identical metal materials”. Claim 1, from which this line depends, requires that “materials of both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO)” which is a metal oxide material, and not just a “metal material”. It is unclear how both of these limitations can be true simultaneously. This renders the claim indefinite. For the purposes of examination, the examiner will interpret the limitation as “materials of the gate line fixing portion and the common electrode are identical materials which contain metal”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7 and 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935).
Regarding claim 1, AHN discloses an array substrate, along a thickness direction, comprises:
a base substrate (substrate 142, see fig 15-16, para 103);
a gate line fixing portion (portion 101 of the gate line 102, see fig 15-16, para 48) and a common electrode (common electrode 122A and 122B, see fig 15-16, para 53) which are arranged on the base substrate and insulated from each other (102 and 122 are insulated from each other, see fig 16), wherein materials of the gate line fixing portion and the common electrode are identical conductive materials (102 and 122 can be the same material, see para 53), and the gate line fixing portion and the common electrode are located in one structural layer (101 and 122 are directly on 142, see fig 16);
wherein materials of both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO) (122 can be made of 102, and 102 can be ITO, see fig 15-16, para 53 and 48);
a gate line arranged on the gate line fixing portion (conductive line 103 of gate line 102, see fig 15-16, para 48) and a common electrode line (conductive line 103 of common line 120, see fig 15-16, para 52 and 48) arranged on the common electrode, wherein the gate line fixing portion fixes the gate line to the base substrate (101 connects 103 to 142 in line 102, see fig 16), materials of the gate line and the common electrode line are identical materials (both can be formed of 103 which can be Cu, see fig 15-16, para 48), and the gate line and the common electrode line are located in another structural layer (103 in 102 and 120A are on top of 101, see fig 16) and are arranged to be insulated from each other (the lines 103 in 102 and 120A are insulated from each other, see fig 15-16);
a first insulating layer located on the base substrate (insulator 144, see fig 15-16, para 46), wherein the first insulating layer covers the gate line, the common electrode line and the common electrode (144 covers top surface of 101, 122 and 103 in line 102 and 120A, see fig 16); and
a second insulating layer (150 is on a top surface of 144, see fig 16, 150, para 102) located on the first insulating layer, and a pixel electrode located on the second insulating layer (pixel electrode 118 is on a bottom surface of 150, see fig 16, para 55);
wherein the common electrode is between the pixel electrode and the base substrate (122A is between 118 and 142, see fig 16); an orthogonal projection of the pixel electrode on the base substrate is overlapped with an orthogonal projection of the common electrode on the base substrate (fig 15 shows orthogonal projections of pixel electrode 118 and common electrode which overlap, see fig 15); and both of the orthogonal projection of the pixel electrode on the base substrate and the orthogonal projection of the common electrode on the base substrate are between an orthogonal projection of the gate line and an orthogonal projection of the common electrode line on the base substrate (pixel electrode 118 and common electrode 122 are between gate line 102 and common line 120 in fig 15); thicknesses of the common electrode and the gate line fixing portion are identical (both are parts of 101 with a common thickness, see fig 16, para 48-52).
AHN fails to explicitly disclose a device wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 um - 0.07 um; and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 um - 0.60 um.
TAKAHASHI teaches a device wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 um - 0.07 um (the thickness of ITO layer 12 in the gate 22 and common electrode 20 can be 50 nm which is .05 um, see fig 1, para 69); and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 um - 0.60 um (the Cu layer 12a and 22a in the gate 22 and common line 21 can be 400 nm thick which is 0.4 um, see fig 1, para 70).
AHN and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN with the specific layer thicknesses of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN with the specific layer thicknesses of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thicknesses of the electrode layers in the device of AHN in order to simplify the process (see AHN para 19).
Regarding claim 2, AHN and TAKAHASHI disclose, as best as the examiner is able to ascertain the claimed invention, the array substrate of claim 1.
AHN further discloses a device, wherein materials of the gate line fixing portion and the common electrode are identical metal materials (both 101 in 102 and 122 can be ITO which comprises Indium, a metal, see fig 15-16, para 53 and 48).
Regarding claim 3, AHN and TAKAHASHI disclose the array substrate of claim 1.
AHN further discloses a device, wherein materials of the gate line fixing portion and the common electrode are identical transparent conductive materials (both 101 in 102 and 122 can be ITO, a transparent conductive oxide, see fig 15-16, para 53 and 48).
Regarding claim 4, AHN and TAKAHASHI disclose the array substrate of claim 1.
AHN fails to explicitly disclose a device, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate.
TAKAHASHI teaches a device, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate (ITO layer 12 and Cu layer 22 have the same width, see fig 1).
AHN and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN with the specific layer thicknesses of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN with the specific layer thicknesses of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thicknesses of the electrode layers in the device of AHN in order to simplify the process (see AHN para 19).
Regarding claim 5, AHN and TAKAHASHI disclose the array substrate of claim 1.
AHN further discloses a device, wherein
a material of the pixel electrode comprises a transparent conductive material, wherein the transparent conductive material comprises ITO (118 can be ITO, see fig 15-16 and 8C, para 80).
Regarding claim 7, AHN and TAKAHASHI disclose the array substrate of claim 1.
AHN further discloses a device, wherein both the gate line and the common electrode line are of a single-layer metal structure (103 can be a Cu metal layer, see fig 15-16, para 48).
Regarding claim 9, AHN and TAKAHASHI disclose the array substrate according to claim 1.
AHN further discloses a display panel (the device is a display panel, see para 5), comprising the array substrate according to claim 1.
Regarding claim 10, AHN and TAKAHASHI disclose the display panel according to claim 9.
AHN further discloses a display device (the device is a display panel, see para 5), comprising the display panel according to claim 9.
Regarding claim 11, AHN and TAKAHASHI disclose a method of manufacturing an array substrate, for manufacturing the array substrate according to claim1, the method of manufacturing the array substrate comprising:
forming a first conductive layer on the base substrate (101 is formed on 142, see fig 5B, para 66);
forming a second conductive layer on the first conductive layer (103 is formed on 101, see fig 5B, para 66);
patterning the second conductive layer to form the gate line and the common electrode line (102 and 120 including 103 are patterned into their shapes, see fig 7B, para 73), wherein the common electrode line and the gate line are arranged to be insulated from each other (102 and 120 are insulated from each other, see fig 7, para 73);
patterning the first conductive layer to form the common electrode and the gate line fixing portion located underneath the gate line (102 and 120 including 101 are patterned into their shapes, see fig 7B, para 73), wherein the gate line fixing portion fixes the gate line to the base substrate (101 is between 103 and 142, see fig 7B), a part of the common electrode is located under the common electrode line (101 is under 103 in 120A, see fig 7B), and the common electrode and the gate line fixing portion are arranged to be insulated from each other (102 and 120 are insulated from each other, see fig 7, para 73);
wherein materials of both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO) (122 can be made of 102, and 102 can be ITO, see fig 15-16, para 53 and 48);
forming the first insulating layer on the base substrate (fig 7B, 144, para 73), wherein the first insulating layer covers the gate line, the common electrode line and the common electrode (144 covers 102, 122 and 120, see fig 7B);
forming the second insulating layer on the first insulating layer (150 is formed on 144, see fig 16, para 102); and
forming the pixel electrode on the second insulating layer (118 is formed on a bottom side of 150, see fig 16);
wherein the common electrode is between the pixel electrode and the base substrate (122A is between 118 and 142, see fig 16); an orthogonal projection of the pixel electrode on the base substrate is overlapped with an orthogonal projection of the common electrode on the base substrate (fig 15 shows orthogonal projections of pixel electrode 118 and common electrode which overlap, see fig 15); and both of the orthogonal projection of the pixel electrode on the base substrate and the orthogonal projection of the common electrode on the base substrate are between an orthogonal projection of the gate line and an orthogonal projection of the common electrode line on the base substrate (pixel electrode 118 and common electrode 122 are between gate line 102 and common line 120 in fig 15); thicknesses of the common electrode and the gate line fixing portion are identical (both are parts of 101 with a common thickness, see fig 16, para 48-52).
AHN fails to explicitly disclose a method wherein thicknesses of the common electrode and the gate line fixing portion are identical, and the thicknesses of both the common electrode and the gate line fixing portion are 0.03 pm - 0.07 pm; and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 pm - 0.60 pm.
TAKAHASHI teaches a method wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 um - 0.07 um (the thickness of ITO layer 12 in the gate 22 and common electrode 20 can be 50 nm which is .05 um, see fig 1, para 69); and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 um - 0.60 um (the Cu layer 12a and 22a in the gate 22 and common line 21 can be 400 nm thick which is 0.4 um, see fig 1, para 70).
AHN and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN with the specific layer thicknesses of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN with the specific layer thicknesses of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thicknesses of the electrode layers in the device of AHN in order to simplify the process (see AHN para 19).
Regarding claim 12, AHN and TAKAHASHI disclose, as best as the examiner is able to ascertain the claimed invention, the method of manufacturing the array substrate according to claim 11.
AHN further discloses a method, wherein a material of the first conductive layer comprises a metal material (both 101 in 102 and 122 can be ITO which comprises Indium, a metal, see fig 15-16, para 53 and 48).
Regarding claim 13, AHN and TAKAHASHI disclose the method of manufacturing the array substrate according to claim 11.
AHN further discloses a method, wherein a material of the first conductive layer comprises a transparent conductive material (both 101 in 102 and 122 can be ITO, a transparent conductive oxide, see fig 15-16, para 53 and 48).
Regarding claim 14, AHN and TAKAHASHI disclose the method of manufacturing the array substrate according to claim 11.
AHN fails to explicitly disclose a method, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate.
TAKAHASHI teaches a method, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate (ITO layer 12 and Cu layer 22 have the same width, see fig 1).
AHN and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN with the specific layer thicknesses of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN with the specific layer thicknesses of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thicknesses of the electrode layers in the device of AHN in order to simplify the process (see AHN para 19).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of ZHANG (US 20160139443).
Regarding claim 6, AHN and TAKAHASHI disclose the array substrate of claim 1.
AHN and TAKAHASHI fails to explicitly disclose a device, wherein,
a thickness of the first insulating layer is 0.35 pm - 0.45 pm;
a thickness of the second insulating layer is 0.55 pm - 0.65 pm; and
a thickness of the pixel electrode is 0.03 pm - 0.07 pm.
TAKAHASHI teaches a device, wherein,
a thickness of the first insulating layer is 0.35 pm - 0.45 pm (202 can be 300 nm thick, see fig 9, para 40);
a thickness of the second insulating layer is 0.55 pm - 0.65 pm (30 can be 600 nm thick, see fig 9, para 56); and
a thickness of the pixel electrode is 0.03 pm - 0.07 pm (pixel electrode 205 can be 50 nm, see fig 9, para 49).
AHN, ZHANG and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN and TAKAHASHI with the specific layer thicknesses of ZHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN and TAKAHASHI with the specific layer thicknesses of ZHANG in order to improve the display effect of the display device (see ZHANG para 66).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thicknesses of the electrode layers in the device of AHN in order to simplify the process (see AHN para 19).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of KIM (US 20060131581).
Regarding claim 8, AHN and TAKAHASHI disclose the array substrate of claim 1.
AHN and TAKAHASHI fails to explicitly disclose a device, wherein the array substrate comprises a plurality of pixel units, each of the plurality of pixel units comprises a thin film transistor, the pixel electrode, the common electrode and the common electrode line, the thin film transistor comprises a gate electrode, a source electrode and a drain electrode, and the gate electrode is a part of the gate line.
KIM teaches a device, wherein the array substrate comprises a plurality of pixel units (the array panel has a plurality of pixel units, see fig 1, para 36), each of the plurality of pixel units comprises a thin film transistor (the TFT shown in fig 3), the pixel electrode (the pixel includes pixel electrode 190, see fig 1-3), the common electrode and the common electrode line (the pixel includes 131, see fig 1-3), the thin film transistor comprises a gate electrode (fig 3, 124, para 37), a source electrode (fig 3, 173, para 44) and a drain electrode (fig 3, 175, para 44), and the gate electrode is a part of the gate line (124 protrudes from 121, see para 37).
AHN, TAKAHASHI and KIM are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN and TAKAHASHI with the device comprising a plurality of pixel units of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN and TAKAHASHI with the device comprising a plurality of pixel units of KIM in order to increase display area (see KIM para 38).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of CHOI (US 20150200383).
Regarding claim 15, AHN and TAKAHASHI disclose the method of manufacturing the array substrate according to claim 11.
AHN and TAKAHASHI fails to explicitly disclose a method, wherein for forming the first conductive layer on the base substrate, the first conductive layer is formed by rotating a target.
CHOI teaches a method, wherein for forming the first conductive layer on the base substrate, the first conductive layer is formed by rotating a target (the deposition target 131 can be rotating, see fig 2, para 57).
AHN, TAKAHASHI and CHOI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN and TAKAHASHI with the specific formation method of CHOI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN and TAKAHASHI with the specific formation method of CHOI in order so that the entire surface of the rotating target can be used (see CHOI para 75).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of SAKAKIMA (US 6256222).
Regarding claim 16, AHN and TAKAHASHI disclose the method of manufacturing the array substrate according to claim 11.
AHN further discloses a method, wherein a structure of the second conductive layer is a single-layer metal structure (103 can be a Cu layer, see para 48).
AHN and TAKAHASHI fails to explicitly disclose a method wherein for forming the second conductive layer on the first conductive layer, the second conductive layer is formed by using a multi-cavity coating device, and each cavity forms a layer structure with a partial thickness of the single-layer metal structure.
SAKAKIMA teaches a method wherein for forming the second conductive layer on the first conductive layer, the second conductive layer is formed by using a multi-cavity coating device (the metal layer 1-2-3 can be formed with a multi-target sputtering apparatus, see fig 1, para 64), and each cavity forms a layer structure with a partial thickness of the single-layer metal structure (the different targets are used to form the layers of metal structure 1-2-3, see fig 1, para 64).
AHN, TAKAHASHI and SAKAKIMA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN and TAKAHASHI with the specific formation method of SAKAKIMA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN and TAKAHASHI with the specific formation method of SAKAKIMA in order to make a device with high reliability (see SAKAKIMA para 319).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of PARK (US 20060278606).
Regarding claim 17, AHN and TAKAHASHI disclose the method of manufacturing the array substrate according to claim 11.
AHN and TAKAHASHI fails to explicitly disclose a method, comprises at least one of:
for patterning the second conductive layer to form the gate line and the common electrode line, etching is performed by using etchant with a high selectivity for the second conductive layer; or
for patterning the first conductive layer to form the common electrode and the gate line fixing portion located underneath the gate line, etching is performed by using etchant with a high selectivity for the first conductive layer.
PARK teaches a method which, comprises at least one of:
for patterning the second conductive layer to form the gate line and the common electrode line, etching is performed by using etchant with a high selectivity for the second conductive layer (2 can be etched using a selective etch, see fig 1-3 and 5, para 59-66); or
for patterning the first conductive layer to form the common electrode and the gate line fixing portion located underneath the gate line, etching is performed by using etchant with a high selectivity for the first conductive layer.
AHN, TAKAHASHI and PARK are analogous art because they both are directed towards methods of making semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of AHN and TAKAHASHI with the specific formation method of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of AHN and TAKAHASHI with the specific formation method of PARK in order to achieve superior etching uniformity, a side profile having good tapered acute angle can be formed without degrading adhesion of the triple-layered wire to the substrate (see PARK para 59).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of KIMURA (US 20100224880).
Regarding claim 18, AHN and TAKAHASHI method the method of manufacturing the array substrate according to claim 11.
AHN and TAKAHASHI fails to explicitly disclose a method, wherein
the gate line and the common electrode line are formed by using a mask; and
the common electrode and the gate line fixing portion located underneath the gate line are formed by patterning the first conductive layer with another mask.
KIMURA teaches a device, wherein
the gate line and the common electrode line are formed by using a mask (104a and 104b are both formed by a different mask 162, see fig 3D, para 177); and
the common electrode and the gate line fixing portion located underneath the gate line are formed by patterning the first conductive layer with another mask (102a and 102b are formed by patterning 102 with a mask 161, see fig 3B, para 172).
AHN, TAKAHASHI and KIMURA are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN and TAKAHASHI with the specific formation method of KIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN and TAKAHASHI with the specific formation method of KIMURA in order to prevent the formation of a hillock (see KIMURA para 176).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN (US 20060146213) in view of TAKAHASHI (US 20080284935) and further in view of SHIEH (US 20140138673) and LIN (US 20050079264.
Regarding claim 19, AHN and TAKAHASHI method the method of manufacturing the array substrate according to claim 11.
AHN and TAKAHASHI fails to explicitly method a method, wherein
for forming the first insulating layer on the base substrate, the first insulating layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a temperature of the PECVD process is 350 "C - 370 "C; and
a crystallization process for the common electrode and the gate line fixing portion is completed in the process of forming the first insulating layer through the PECVD process.
SHIEH teaches a method for forming the first insulating layer on the base substrate, the first insulating layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a temperature of the PECVD process is 350 "C - 370 "C (the gate dielectric 32 can be deposited by PECVD at 350 degrees centigrade, see fig 10, para 5); and
AHN, TAKAHASHI, and SHIEH are analogous art because they both are directed towards methods for making semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of AHN and TAKAHASHI with the specific formation method of SHIEH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of AHN and TAKAHASHI with the specific formation method of SHIEH in order to lower power consumption (see SHIEH para 60).
AHN, SHIEH and TAKAHASHI fails to explicitly disclose a method a crystallization process for the common electrode and the gate line fixing portion is completed in the process of forming the first insulating layer through the PECVD process.
LIN teaches a method comprising a crystallization process for the common electrode and the gate line fixing portion is completed in the process of forming the first insulating layer through the PECVD process (the gate insulator can be formed by PECVD with recrystallization of the layer below it, see fig 3, para 39).
AHN, SHEIH, TAKAHASHI and LIN are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of AHH and TAKAHASHI with the specific formation method of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of AHH and TAKAHASHI with the specific formation method of LIN in order to improve efficiency (see LIN para 44).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811