DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 4-11 and 13-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, lines 7-8 recite “the gate line fixing portion and the common electrode are made of Cu or Al”. These materials for the gate line fixing portion and common electrode are not disclosed in the applicant’s specification or other parts of the disclosure. Paragraph 61 of the applicant’s specification requires that the gate line fixing portion and common electrode “are identical transparent conductive materials … Indium Tin Oxide”. The gate line and the common electrode line, which are above the gate line fixing portion and the common electrode, can be made of Cu or Al as discussed in the same paragraph, but these are the upper layers of the electrodes and not the gate line fixing portion, which must fix the gate line to the substrate. This issue means that the limitation is new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 13-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11, lines 13-14 recite “both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO)”. These layers are required, in claim 1 from which this claim depends, to be Al or Cu. These layers cannot be both materials at once. This issue renders the claim indefinite.
Claim 11, line 31 recites “a thickness of the second insulating layer” and line 32 recites “a thickness of the pixel electrode”. It is not clear, from these limitations, whether or not these are intended to be the same as the elements of the same name in claim 1. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559) and ZHANG (US 20160139443).
Regarding claim 1, KIM discloses an array substrate, along a thickness direction, comprises:
a base substrate (substrate 110, see fig 1-3, para 41);
a gate line fixing portion (portion 121p of the gate line 121, see fig 1-3, para 41) and a common electrode (lower electrode portion 131p, see fig 1-3, para 41) which are arranged on the base substrate and insulated from each other (121p and 131p are both on 110, and have an insulator between them, see fig 2),
wherein materials of the gate line fixing portion and the common electrode are identical conductive materials (lower films 121p and 131p can be Al, see fig 1-3, para 39), and the gate line fixing portion and the common electrode are located in one structural layer (131p and 121p are both on a layer over 110, see fig 2);
wherein the gate line fixing portion and the common electrode are made of Cu or Al (121p and 131p can be Al, see para 30);
a gate line (121q is on 121p, see fig 1-3, 121q, para 40) arranged on the gate line fixing portion and a common electrode line (131q is on 131p, see fig 1-3, 131q, para 40) arranged on the common electrode,
wherein the gate line fixing portion fixes the gate line to the base substrate (121p attaches 121q to 110, see fig 2), materials of the gate line and the common electrode line are identical materials (121q and 131q can both be Mo, see fig 2, para 40), and the gate line and the common electrode line are located in another structural layer (121q and 131q are both above 121p and 131p, see fig 2) and are arranged to be insulated from each other (131q and 121q have insulator between them, see fig 2);
a first insulating layer (insulator 140, see fig 1-3, para 42) located on the base substrate, wherein the first insulating layer covers the gate line, the common electrode line and the common electrode (140 covers 121 and 131, see fig 2); and
a second insulating layer located on a surface of the first insulating layer facing away from the substrate (insulator 180 is on a top surface of 140, see fig 2, para 50), and a pixel electrode (190, see fig 1-3, para 52) located on a surface of the second insulating layer facing away from the substrate (190 is on a top surface of 180, see fig 2);
wherein the common electrode is between the pixel electrode and the base substrate (131p is between 190 and 110, see fig 2); an orthogonal projection of the pixel electrode on the base substrate is overlapped with an orthogonal projection of the common electrode on the base substrate (190 and 131p overlap along the vertical direction, see fig 2); and
both of the orthogonal projection of the pixel electrode on the base substrate and the orthogonal projection of the common electrode on the base substrate are between an orthogonal projection of the gate line and an orthogonal projection of the common electrode line on the base substrate (at least a portion of the common electrode 131p and the pixel electrode 190 are horizontally between the gate line 121q and 131q, see fig 1-2);
thicknesses of the common electrode and the gate line fixing portion are identical (131p and 131p can both be 2000 ANG thick, see para 39), and
a thickness of the pixel electrode is 0.03 microns - 0.07 microns (190 can be .05 microns, see fig 2, para 86).
KIM fails to explicitly disclose a device wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 microns - 0.07 microns; and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 microns - 0.60 microns.
PARK teaches a device wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 microns - 0.07 microns (the lower gate metal layers can be 500 ANG, which is .05 microns, see fig 6B, para 27); and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 microns - 0.60 microns (the upper gate metal line can be 4000 ANG which is .4 microns, see fig 6B, para 27).
KIM and PARK are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the specific layer thicknesses of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the specific layer thicknesses of PARK in order to improve the opening ratio of the device (see PARK para 104).
KIM and PARK fails to explicitly disclose a device wherein a thickness of the second insulating layer is 0.55 microns - 0.65 microns.
ZHANG teaches a device wherein a thickness of the second insulating layer is 0.55 microns - 0.65 microns (30 can be 600 nm thick, see fig 9, para 56).
KIM, PARK and ZHANG are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM and PARK with the specific layer thickness of ZHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM and PARK with the specific layer thickness of ZHANG in order to improve the display effect of the display device (see ZHANG para 66).
Additionally, parameters such as the thicknesses of layers in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the layer thicknesses in the device of KIM in order to increase the display area (see KIM para 8).
Regarding claim 5, KIM, PARK and ZHANG discloses the array substrate of claim 1.
KIM further discloses a device, wherein
a material of the pixel electrode comprises a transparent conductive material, wherein the transparent conductive material comprises ITO (190 can be ITO, see para 52).
Regarding claim 6, KIM, PARK and ZHANG discloses the array substrate of claim 1.
KIM further discloses a device, wherein,
a thickness of the first insulating layer is 0.35 microns - 0.45 microns (140 can be 4000 A, which is .4 microns thick, see fig 2, para 58).
Regarding claim 7, KIM, PARK and ZHANG discloses the array substrate of claim 1.
KIM further discloses a device, wherein both the gate line and the common electrode line are of a single-layer metal structure (upper layers 121q and 131q can both me Mo layers, see fig 2, para 40).
Regarding claim 8, KIM, PARK and ZHANG discloses the array substrate of claim 1.
KIM further discloses a device, wherein the array substrate comprises a plurality of pixel units (the device comprises a plurality of 121 and 131 each forming pixel units, see para 53 and 37-38), each of the plurality of pixel units comprises a thin film transistor (the TFT shown in fig 3, see fig 1-3, para 45), the pixel electrode (190 is part of the pixel unit defined by 121 and 131, see fig 1-3), the common electrode and the common electrode line (131 is located in the unit formed by 121 and 131, see fig 1-3), the thin film transistor comprises a gate electrode (gate electrode 124, see fig 3, para 37), a source electrode (source electrode 173, see fig 3, para 44) and a drain electrode (drain electrode 175, see fi g3, para 44), and the gate electrode is a part of the gate line (124 protrudes from 121, see para 37).
Regarding claim 9, KIM, PARK and ZHANG discloses the array substrate according to claim 1.
KIM further discloses a display panel, comprising the array substrate according to claim 1 (the device in fig 1-3 can be part of a display panel, see para 36).
Regarding claim 10, KIM, PARK and ZHANG discloses the display panel according to claim 9.
KIM further discloses a device a display device, comprising the display panel according to claim 9 (the device of fig 1-3 can be a display device, see para 38).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559) and ZHANG (US 20160139443) and further in view of (TAKAHASHI (US 20080284935)
Regarding claim 4, KIM, PARK and ZHANG discloses the array substrate of claim 1.
KIM, PARK and ZHANG fail to explicitly disclose a device, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate.
TAKAHASHI teaches a device, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate (ITO layer 12 and Cu layer 22 have the same width, see fig 1).
KIM, PARK, ZHANG and TAKAHASHI are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM, PARK and ZHANG with the electrode shapes of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM, PARK and ZHANG with the electrode shapes of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Claim(s) 11 and 13-14, is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559) and ZHANG (US 20160139443) further in view of TAKAHASHI (US 20080284395), SHIEH (US 20140138673) and H PARK (US 20060118788).
Regarding claim 11, as best as the examiner is able to ascertain the claimed invention, KIM, PARK and ZHANG discloses a method of manufacturing an array substrate, for manufacturing the array substrate according to claim1, the method of manufacturing the array substrate comprising:
forming a first conductive layer (the lower conductive layer comprising 121p and 131p, see fig 5A, para 39) on the base substrate (substrate 110, see fig 1-3, para 41);
forming a second conductive (the upper conductive layer comprising 121q and 131q, see fig 5A, para 40) layer on the first conductive layer;
patterning the second conductive layer to form the gate line (121q is on 121p, see fig 1-3, 121q, para 40) and the common electrode line (131q is on 131p, see fig 1-3, 131q, para 40), wherein the common electrode line and the gate line are arranged to be insulated from each other (121p and 131p can be insulated from each other, see fig 5A and 1-3);
patterning the first conductive layer to form the common electrode (lower electrode portion 131p, see fig 1-3, para 41) and the gate line fixing portion (portion 121p of the gate line 121, see fig 1-3, para 41) located underneath the gate line, wherein the gate line fixing portion fixes the gate line to the base substrate (121p attaches 121q to 110, see fig 2), a part of the common electrode is located under the common electrode line (131p is located under 131q, see fig 2), and the common electrode and the gate line fixing portion are arranged to be insulated from each other (121 and 131 can be insulated from each other, see fig 2 and 5A);
forming the first insulating layer (insulator 140, see fig 1-3, para 42) on the base substrate, wherein the first insulating layer covers the gate line, the common electrode line and the common electrode (140 covers 121 and 131, see fig 2);
forming the second insulating layer (insulator 180 is on a top surface of 140, see fig 2, para 50) on the first insulating layer; and
forming the pixel electrode (190, see fig 1-3, para 52) on the second insulating layer;
wherein the common electrode is between the pixel electrode and the base substrate (131p is between 190 and 110, see fig 2); an orthogonal projection of the pixel electrode on the base substrate is overlapped with an orthogonal projection of the common electrode on the base substrate (190 and 131p overlap along the vertical direction, see fig 2); and both of the orthogonal projection of the pixel electrode on the base substrate and the orthogonal projection of the common electrode on the base substrate are between an orthogonal projection of the gate line and an orthogonal projection of the common electrode line on the base substrate (at least a portion of the common electrode 131p and the pixel electrode 190 are horizontally between the gate line 121q and 131q, see fig 1-2);
thicknesses of the common electrode and the gate line fixing portion are identical (131p and 131p can both be 2000 ANG thick, see para 39), and
a thickness of the pixel electrode is 0.03 microns - 0.07 microns (190 can be .05 microns, see fig 2, para 86).
KIM fails to explicitly disclose a device wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 microns - 0.07 microns; and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 microns - 0.60 microns.
PARK teaches a device wherein the thicknesses of both the common electrode and the gate line fixing portion are 0.03 microns - 0.07 microns (the lower gate metal layers can be 500 ANG, which is .05 microns, see fig 6B, para 27); and
thicknesses of the common electrode line and the gate line are identical, and the thicknesses of both the common electrode line and the gate line are 0.35 microns - 0.60 microns (the upper gate metal line can be 4000 ANG which is .4 microns, see fig 6B, para 27).
KIM and PARK are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM with the specific layer thicknesses of PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM with the specific layer thicknesses of PARK in order to improve the opening ratio of the device (see PARK para 104).
KIM and PARK fails to explicitly disclose a device wherein a thickness of the second insulating layer is 0.55 microns - 0.65 microns.
ZHANG teaches a device wherein a thickness of the second insulating layer is 0.55 microns - 0.65 microns (30 can be 600 nm thick, see fig 9, para 56).
KIM, PARK and ZHANG are analogous art because they both are directed towards TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM and PARK with the specific layer thickness of ZHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM and PARK with the specific layer thickness of ZHANG in order to improve the display effect of the display device (see ZHANG para 66).
KIM, PARK and ZHANG fail to explicitly disclose a method wherein materials of both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO).
TAKAHASHI teaches a method wherein materials of both the gate line fixing portion and the common electrode comprise Indium Tin Oxide (ITO) (12 under 21 and 22 can be ITO, see fig 1, para 40 and 46).
KIM, PARK, ZHANG and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM, PARK, ZHANG with the material of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM, PARK, ZHANG with the material of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
KIM, PARK and ZHANG fail to explicitly disclose a method wherein the first insulating layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a temperature of the PECVD process is 350 "C - 370 "C.
SHIEH teaches a method wherein the first insulating layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a temperature of the PECVD process is 350 "C - 370 "C (the gate dielectric 32 can be deposited by PECVD at 350 degrees centigrade, see fig 10, para 5).
KIM, PARK, ZHANG and SHIEH are analogous art because they both are directed towards methods of making TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM, PARK and ZHANG with the specific deposition process and temperature of SHIEH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM, PARK and ZHANG with the specific deposition process and temperature of SHIEH in order to lower power consumption (see SHIEH para 60).
KIM, PARK and ZHANG fail to explicitly disclose a method wherein a crystallization process for the common electrode and the gate line fixing portion is completed in the process of forming the first insulating layer through the PECVD process.
H PARK teaches a method wherein a crystallization process for the common electrode and the gate line fixing portion is completed in the process of forming the first insulating layer through the PECVD process (the upper layer 124BR of the electrode can be ITO which is formed as amorphous and crystallized during the insulator 140, see fig 7, para 116).
KIM, PARK, ZHANG and H PARK are analogous art because they both are directed towards methods of making TFT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM, PARK and ZHANG with the specific electrode formation process of H PARK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM, PARK and ZHANG with the specific electrode formation process of H PARK in order to increase contact adhesiveness (see H PARK para 116).
Additionally, parameters such as the thicknesses of layers and the temperature of processes in the art of methods of making semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the thickness and temperature of semiconductor device manufacturing devices in the method of KIM in order to increase the display area (see KIM para 8).
Regarding claim 13, as best as the examiner is able to ascertain the claimed invention, KIM, PARK and ZHANG discloses the method of manufacturing the array substrate according to claim 11.
KIM, PARK and ZHANG fail to explicitly disclose a method, wherein a material of the first conductive layer comprises a transparent conductive material.
TAKAHASHI teaches a method, wherein a material of the first conductive layer comprises a transparent conductive material (12 under 21 and 22 can be ITO, see fig 1, para 40 and 46).
KIM, PARK, ZHANG and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM, PARK, ZHANG with the material of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM, PARK, ZHANG with the material of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Regarding claim 14, as best as the examiner is able to ascertain the claimed invention, KIM, PARK and ZHANG discloses the method of manufacturing the array substrate according to claim 11.
KIM, PARK and ZHANG fail to explicitly disclose a method, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate.
TAKAHASHI teaches a method, wherein an orthographic projection of the gate line fixing portion on the base substrate coincide exactly with an orthographic projection of the gate line on the base substrate (ITO layer 12 and Cu layer 22 have the same width, see fig 1).
KIM, PARK, ZHANG and TAKAHASHI are analogous art because they both are directed towards semiconductor TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KIM, PARK, ZHANG with the material of TAKAHASHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KIM, PARK, ZHANG with the material of TAKAHASHI in order to improve productivity in mass production to use materials and processing processes in common for the image signal line and the scanning signal line in the liquid crystal display device (see TAKAHASHI para 67).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559), ZHANG (US 20160139443), TAKAHASHI (US 20080284395), SHIEH (US 20140138673) and H PARK (US 20060118788) and further in view of CHOI (US 20150200383).
Regarding claim 15, as best as the examiner is able to ascertain the claimed invention, KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK discloses the method of manufacturing the array substrate according to claim 11.
KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK fail to explicitly disclose a method, wherein for forming the first conductive layer on the base substrate, the first conductive layer is formed by rotating a target.
CHOI teaches a method, wherein for forming the first conductive layer on the base substrate, the first conductive layer is formed by rotating a target (the deposition target 131 can be rotating, see fig 2, para 57).
KIM, PARK, ZHANG, TAKAHASHI, SHIEH, PARK and CHOI are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the rotating target of CHOI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the rotating target of CHOI in order so that the entire surface of the rotating target can be used (see CHOI para 75).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559), ZHANG (US 20160139443), TAKAHASHI (US 20080284395), SHIEH (US 20140138673) and H PARK (US 20060118788) and further in view of SAKAKIMA (US 6256222).
Regarding claim 16, as best as the examiner is able to ascertain the claimed invention, KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK discloses the method of manufacturing the array substrate according to claim 11.
KIM further discloses a method, wherein a structure of the second conductive layer is a single-layer metal structure (upper layers 121q and 131q can both me Mo layers, see fig 2, para 40).
KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK fail to explicitly disclose a method for forming the second conductive layer on the first conductive layer, the second conductive layer is formed by using a multi-cavity coating device, and each cavity forms a layer structure with a partial thickness of the single-layer metal structure.
SAKAKIMA teaches a method for forming the second conductive layer on the first conductive layer, the second conductive layer is formed by using a multi-cavity coating device (the metal layer 1-2-3 can be formed with a multi-target sputtering apparatus, see fig 1, para 64), and each cavity forms a layer structure with a partial thickness of the single-layer metal structure (the different targets are used to form the layers of metal structure 1-2-3, see fig 1, para 64).
KIM, PARK, ZHANG, TAKAHASHI, SHIEH, PARK and SAKAKIMA are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the sputtering apparatus of SAKAKIMA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the sputtering apparatus of SAKAKIMA in order to make a device with high reliability (see SAKAKIMA para 319).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559), ZHANG (US 20160139443), TAKAHASHI (US 20080284395), SHIEH (US 20140138673) and H PARK (US 20060118788) and further in view of CHOI (US 20150200383).
Regarding claim 17, as best as the examiner is able to ascertain the claimed invention, KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK discloses the method of manufacturing the array substrate according to claim 11.
KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK fail to explicitly disclose a method, comprises at least one of:
for patterning the second conductive layer to form the gate line and the common electrode line, etching is performed by using etchant with a high selectivity for the second conductive layer; or
for patterning the first conductive layer to form the common electrode and the gate line fixing portion located underneath the gate line, etching is performed by using etchant with a high selectivity for the first conductive layer.
CHOI teaches a method, comprises at least one of:
for patterning the second conductive layer to form the gate line and the common electrode line, etching is performed by using etchant with a high selectivity for the second conductive layer (2 can be etched using a selective etch, see fig 1-3 and 5, para 59-66); or
for patterning the first conductive layer to form the common electrode and the gate line fixing portion located underneath the gate line, etching is performed by using etchant with a high selectivity for the first conductive layer.
KIM, PARK, ZHANG, TAKAHASHI, SHIEH, PARK and PARK 2006 are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the pattering process of PARK 2006 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the pattering process of PARK 2006 in order to achieve superior etching uniformity, a side profile having good tapered acute angle can be formed without degrading adhesion of the triple-layered wire to the substrate (see PARK para 59).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20060131581) in view of PARK (US 6380559), ZHANG (US 20160139443), TAKAHASHI (US 20080284395), SHIEH (US 20140138673) and H PARK (US 20060118788) and further in view of KIMURA (US 20100224880).
Regarding claim 18, as best as the examiner is able to ascertain the claimed invention, KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK discloses the method of manufacturing the array substrate according to claim 11.
KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK fail to explicitly disclose a method, wherein
the gate line and the common electrode line are formed by using a mask; and
the common electrode and the gate line fixing portion located underneath the gate line are formed by patterning the first conductive layer with another mask.
KIMURA teaches a method, wherein
the gate line and the common electrode line are formed by using a mask (104a and 104b are both formed by a different mask 162, see fig 3D, para 177); and
the common electrode and the gate line fixing portion located underneath the gate line are formed by patterning the first conductive layer with another mask (102a and 102b are formed by patterning 102 with a mask 161, see fig 3B, para 172).
KIM, PARK, ZHANG, TAKAHASHI, SHIEH, PARK and KIMURA are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the pattering process of KIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KIM, PARK, ZHANG, TAKAHASHI, SHIEH and PARK with the pattering process of KIMURA in order to prevent the formation of a hillock (see KIMURA para 176)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-11 and 13-18 regarding AHN, TAKAHASHI, LIN and SHIEH have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 6/17, 2026 regarding the ZHANG reference have been fully considered but they are not persuasive.
The applicant argues that layer 30 of ZHANG, see fig 9, does not disclose a second insulating layer as in the claims. This argument is unpersuasive because the insulating layer 30 of ZHANG is the insulating layer above the TFT channel 203 and below the pixel electrode 60. It is also on a top surface of the lower insulator layer 202 which is on the substrate 10. Thus 30 satisfies the requirements in the claim for the second insulating layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights