Prosecution Insights
Last updated: April 19, 2026
Application No. 17/915,522

DISPLAY DEVICE, AND DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Non-Final OA §103§112
Filed
Sep 29, 2022
Examiner
PATEL, REEMA
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
95%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
971 granted / 1097 resolved
+20.5% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1135
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
40.8%
+0.8% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1097 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species 1 in the reply filed on 12/12/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 1-6 and 11-20 correspond to the elected invention. Examiner notes claims 7-10 correspond to unelected species 2, as embodied by Fig. 3 because the through hole within the color filter planarization layer (32, Fig. 3) is only present within species 2/Fig. 3. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 3/28/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6 and 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the blocking groove” in lines 18-19. There is insufficient antecedent basis for this limitation in the claim. The claim only makes prior reference to “a plurality of blocking grooves” (line 15) and “at least one of the plurality of blocking grooves” arranged “between the transistor row and the device row adjacent in the column direction” (lines 16-18). It is unclear to the examiner whether “the blocking groove” in line 18 refers to each of the plurality of blocking grooves or the at least one of the plurality of blocking grooves arranged between the transistor row and the device row adjacent in the column direction, or any other subset of the plurality of blocking grooves. For the purposes of examination, the examiner interprets “the blocking groove” in lines 18-19 as - - each blocking groove of the plurality of blocking grooves - -. However, appropriate correction and/or clarification is requested. Claims 2-6 and 11-19 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1. Claim 2 recites the limitation “the blocking groove” in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 2 depends on claim 1. Claim 1 only makes prior reference to “a plurality of blocking grooves” (line 15) and “at least one of the plurality of blocking grooves” arranged “between the transistor row and the device row adjacent in the column direction” (lines 16-18). Consequently, it is unclear to the examiner whether “the blocking groove” in line 2 of claim 2 refers to each of the plurality of blocking grooves or the at least one of the plurality of blocking grooves arranged between the transistor row and the device row adjacent in the column direction, or any other subset of the plurality of blocking grooves. For the purposes of examination, the examiner interprets “the blocking groove” in line 2 as - - each blocking groove of the plurality of blocking grooves - -. However, appropriate correction and/or clarification is requested. Claim 3 recites the limitation “the blocking groove” in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 3 depends on claim 2, which depends on claim 1. Claim 1 only makes prior reference to “a plurality of blocking grooves” (line 15) and “at least one of the plurality of blocking grooves” arranged “between the transistor row and the device row adjacent in the column direction” (lines 16-18). Consequently, it is unclear to the examiner whether “the blocking groove” in line 2 of claim 3 refers to each of the plurality of blocking grooves or the at least one of the plurality of blocking grooves arranged between the transistor row and the device row adjacent in the column direction, or any other subset of the plurality of blocking grooves. For the purposes of examination, the examiner interprets “the blocking groove” in line 2 as - - each blocking groove of the plurality of blocking grooves - -. However, appropriate correction and/or clarification is requested. Claim 4 recites the limitation “the blocking groove” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Claim 4 depends on claim 1. Claim 1 only makes prior reference to “a plurality of blocking grooves” (line 15) and “at least one of the plurality of blocking grooves” arranged “between the transistor row and the device row adjacent in the column direction” (lines 16-18). Consequently, it is unclear to the examiner whether “the blocking groove” in lines 1-2 of claim 4 refers to each of the plurality of blocking grooves or the at least one of the plurality of blocking grooves arranged between the transistor row and the device row adjacent in the column direction, or any other subset of the plurality of blocking grooves. For the purposes of examination, the examiner interprets “the blocking groove” in lines 1-2 as - - each blocking groove of the plurality of blocking grooves - -. However, appropriate correction and/or clarification is requested. Claim 5 recites the limitation “the light-emitting device” in line 1. There is insufficient antecedent basis for this limitation in the claim. Claim 5 depends on claim 1. Claim 1 only makes prior reference to “a plurality of light-emitting devices” (line 9). Consequently, it is unclear to the examiner whether “the light-emitting device” in line 1 of claim 5 refers to each of the plurality of light-emitting devices or the at least one of the plurality of light-emitting devices, or any other subset of the plurality of light-emitting devices. For the purposes of examination, the examiner interprets “the light-emitting device” in line 1 as - - each light-emitting device of the plurality of light-emitting devices - -. However, appropriate correction and/or clarification is requested. Claim 6 states “the light-emitting control layer further comprises: a color filter layer, arranged on a surface of the driving layer away from the substrate, and comprising a plurality of filter parts arranged in a one-to-one correspondence with the light- emitting devices; and a color filter planarization layer, covering the color filter layer, wherein the light-emitting control layer is arranged on a surface of the color filter planarization layer away from the substrate.” As written, the preamble (the light-emitting control layer further comprises…” is confusing with the rest of the claim because the color filter layer (3, Fig. 2) appears separate from the light control layer (2, Fig. 2) ([0082]) and the plurality of filter parts (31, Fig. 2) and color planarization layer (32, Fig. 2) appear to be parts of the color filter layer ([00117]) according to the Specification and Drawings. As a result, it is unclear to the examiner if Applicant intended the claim as-written and that the light-emitting control layer comprises a color filter layer and a color filter planarization layer or whether Applicant intended the color filter layer and the color filter planarization layer as separate from the light-emitting control layer, as supported by the Specification and Drawings. For the purposes of examination, the examiner interprets the latter interpretation and interprets claim 6 as: 6. (original) The display panel according to claim 1, comprising: a color filter layer, arranged on a surface of the driving layer away from the substrate, and comprising a plurality of filter parts arranged in a one-to-one correspondence with the light- emitting devices; and a color filter planarization layer, covering the color filter layer, wherein the light-emitting control layer is arranged on a surface of the color filter planarization layer away from the substrate. However, appropriate correction and/or clarification is requested. Claims 11-13 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 6. Claim 11 recites the limitation "the filter strip" in line 5. There is insufficient antecedent basis for this limitation in the claim. It is unclear to the examiner whether “the filter strip” in line 5 refers to each of the plurality of filter strips or at least one of the plurality of filter strips, or any other subset of the plurality of filter strips. For the purposes of examination, the examiner interprets “the filter strip” in line 5 as - - each filter strip of the plurality of filter strips - -. However, appropriate correction and/or clarification is requested. Claims 12-13 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 11. Claim 12 recites the limitation "the filter strip" in line 2. There is insufficient antecedent basis for this limitation in the claim. It is unclear to the examiner whether “the filter strip” in line 2 refers to each of the plurality of filter strips or at least one of the plurality of filter strips, or any other subset of the plurality of filter strips. For the purposes of examination, the examiner interprets “the filter strip” in line 2 as - - a filter strip of the plurality of filter strips - -. However, appropriate correction and/or clarification is requested. Claim 13 recites the limitation "the filter strip" in line 4. There is insufficient antecedent basis for this limitation in the claim. It is unclear to the examiner whether “the filter strip” in line 4 refers to each of the plurality of filter strips or at least one of the plurality of filter strips, or any other subset of the plurality of filter strips. For the purposes of examination, the examiner interprets “the filter strip” in line 4 as - - the filter strips - -. However, appropriate correction and/or clarification is requested. Claim 20 recites the limitation “the blocking groove” in lines 17. There is insufficient antecedent basis for this limitation in the claim. The claim only makes prior reference to “a plurality of blocking grooves” (line 14) and “at least one of the plurality of blocking grooves” arranged “between the transistor row and the device row adjacent in the column direction” (lines 15-17). It is unclear to the examiner whether “the blocking groove” in line 17 refers to each of the plurality of blocking grooves or the at least one of the plurality of blocking grooves arranged between the transistor row and the device row adjacent in the column direction, or any other subset of the plurality of blocking grooves. For the purposes of examination, the examiner interprets “the blocking groove” in line 17 as - - each blocking groove of the plurality of blocking grooves - -. However, appropriate correction and/or clarification is requested. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2020/0075704 A1; “Liu”) in view of Minami et al. (U.S. 2018/0342204 A1; “Minami”). Regarding claim 1, Liu discloses a display panel, comprising: A substrate (100, Fig. 4); A driving layer (30, 40, 50, Fig. 4), arranged on the substrate and having a pixel area (non-open region, Fig. 1) and a peripheral area (open region, Fig. 1) outside the pixel area, the pixel area (non-open region, Fig. 1) being provided with a pixel circuit (90, Fig. 1, 4), the pixel circuit comprising a plurality of driving transistors ([0047], [0062]), the plurality of driving transistors being arranged in at least a transistor row (non-open regions, Fig. 1) in a column direction, and the transistor row comprising multiple driving transistors (corresponding to each or R, G, and B sub-pixels, Fig. 1) arranged in a row direction ([0047]); A light-emitting control layer (70, 210, Fig. 4), arranged on (as in “on top of”) a surface of the driving layer (30, 40, 50, Fig. 4) away from the substrate and comprising a pixel-defining layer (70, Fig. 4) and a plurality of light-emitting devices defined by the pixel-defining layer ([0062]), the plurality of light-emitting devices (corresponding to R, G, and B sub-pixels, Fig. 3) being arranged into at least a device row in the column direction, the device row comprising multiple light-emitting devices (corresponding to R, G, and B sub-pixels, Fig. 1) arranged in the row direction, the device row being spaced apart by the transistor row in the column direction, the transistor row being spaced apart by the device row in the column direction (Fig. 1), Wherein the pixel-defining layer (70, Fig. 4) is provided with a plurality of blocking grooves (10, Fig. 4) recessed toward the substrate (100, Fig. 4), the plurality of blocking grooves (10, Fig. 4) are arranged in the column direction, at least one of the plurality of blocking grooves is arranged between the transistor row and the device row adjacent in the column direction, and a light-shielding layer (20, Fig. 4) is arranged in the blocking groove (10, Fig. 4). Yet, Liu does not disclose there are a plurality of transistor rows in a column direction and a plurality of device rows in the column direction. However, Minami discloses a display panel comprising a plurality of transistor rows (containing 220R, 220B or 220G, Fig. 12) in a column direction and a plurality of device rows (corresponding to the R, G, or B sub-pixel, Fig. 12) in the column direction. This has the advantage of forming a larger display panel with a greater number of sub-pixels. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Liu with a plurality of transistor rows in a column direction and a plurality of device rows in the column direction, as taught by Minami, so as to form a larger display panel. Regarding claim 2, Liu discloses the light-shielding layer (20, Fig. 4) covers at least a sidewall of the blocking groove (10, Fig. 4). Regarding claim 3, Liu discloses the light-shielding layer (20, Fig. 4) further covers a bottom surface of the blocking groove (10, Fig. 4). Regarding claim 20, Liu discloses a method for manufacturing a display panel, comprising: Forming a driving layer (30, 40, 50, Fig. 4), arranged on a substrate (100, Fig. 4) and having a pixel area (non-open region, Fig. 1) and a peripheral area (open region, Fig. 1) outside the pixel area, the pixel area (non-open region, Fig. 1) being provided with a pixel circuit (90, Fig. 1, 4), the pixel circuit comprising a plurality of driving transistors ([0047], [0062]), the plurality of driving transistors being arranged in at least a transistor row (non-open regions, Fig. 1) in a column direction, and the transistor row comprising multiple driving transistors (corresponding to each or R, G, and B sub-pixels, Fig. 1) arranged in a row direction ([0047]); Forming a light-emitting control layer (70, 210, Fig. 4), arranged on (as in “on top of”) a surface of the driving layer (30, 40, 50, Fig. 4) away from the substrate and comprising a pixel-defining layer (70, Fig. 4) and a plurality of light-emitting devices defined by the pixel-defining layer ([0062]), the plurality of light-emitting devices (corresponding to R, G, and B sub-pixels, Fig. 3) being arranged into at least a device row in the column direction, the device row comprising multiple light-emitting devices (corresponding to R, G, and B sub-pixels, Fig. 1) arranged in the row direction, the device row being spaced apart by the transistor row in the column direction, the transistor row being spaced apart by the device row in the column direction (Fig. 1), Wherein the pixel-defining layer (70, Fig. 4) is provided with a plurality of blocking grooves (10, Fig. 4) recessed toward the substrate (100, Fig. 4), the plurality of blocking grooves (10, Fig. 4) are arranged in the column direction, at least one of the plurality of blocking grooves is arranged between the transistor row and the device row adjacent in the column direction, and a light-shielding layer (20, Fig. 4) is arranged in the blocking groove (10, Fig. 4). Yet, Liu does not disclose there are a plurality of transistor rows in a column direction and a plurality of device rows in the column direction. However, Minami discloses a display panel comprising a plurality of transistor rows (containing 220R, 220B or 220G, Fig. 12) in a column direction and a plurality of device rows (corresponding to the R, G, or B sub-pixel, Fig. 12) in the column direction. This has the advantage of forming a display panel with a greater number of sub-pixels to form a larger display panel. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Liu with a plurality of transistor rows in a column direction and a plurality of device rows in the column direction, as taught by Minami, so as to form a larger display panel. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2020/0075704 A1; “Liu”) as modified by Minami et al. (U.S. 2018/0342204 A1; “Minami”) as applied to claim 1 above, and further in view of Hu et al. (U.S. 2022/0085259 A1; “Hu”). Regarding claim 4, Liu and Minami disclose a blocking groove (Liu: 10, Fig. 4) but do not disclose sidewalls of the blocking groove get closer in a direction toward the substrate. However, Hu discloses a blocking groove (opening filled in by 700, Fig. 9), wherein sidewalls of the blocking groove get closer in a direction toward a substrate (100, Fig. 9). Because both Lu as modified by Minami and Hu teach methods of forming blocking grooves filled with a light-shielding layer, it would have been obvious to one skilled in the art at the time the invention was effectively filed to substitute one method for the other to achieve the predictable result of forming the blocking groove, wherein sidewalls of the blocking groove get closer in a direction toward a substrate. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. 2020/0075704 A1; “Liu”) as modified by Minami et al. (U.S. 2018/0342204 A1; “Minami”) as applied to claim 1 above, and further in view of Li et al. (U.S. 2018/0261663 A1; “Li”). Regarding claim 6, Liu and Minami disclose a light-emitting control layer (Liu: 70, 210, Fig. 4) arranged on (as in “on top of”) a surface of the driving layer (Liu: 30, 40, 50, Fig. 4) but do not disclose a color filter layer and a color filter planarization layer. However, Li discloses a color filter layer (70, Fig. 7) and a color filter planarization layer (62, Fig. 7) covering the color filter layer ([0056], [0060]). This has the advantage of allowing the display panel to display different colors. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Liu as modified by Minami with a color filter layer and a color filter planarization layer, as taught by Li, so as to enable the display panel to display different colors. Allowable Subject Matter Claims 5 and 11-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REEMA PATEL/Primary Examiner, Art Unit 2812 3/16/26
Read full office action

Prosecution Timeline

Sep 29, 2022
Application Filed
Mar 16, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12599042
CARRIER STRUCTURE AND METHODS OF FORMING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12598937
EPITAXIAL FORMATION WITH TREATMENT AND SEMICONDUCTOR DEVICES RESULTING THEREFROM
2y 5m to grant Granted Apr 07, 2026
Patent 12598976
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12593489
SEMICONDUCTOR STRUCTURE INCLUDING GATE SPACER LAYER AND DIELECTRIC LAYER HAVING PORTION LOWER THAN TOP SURFACE OF GATE SPACER LAYER
2y 5m to grant Granted Mar 31, 2026
Patent 12588245
METHOD FOR MANUFACTURING FOR FORMING SOURCE/DRAIN CONTACT FEATURES AND DEVICES MANUFACTURED THEREOF
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
95%
With Interview (+6.3%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1097 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month