DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 10/03/2022. Claims 1-20 are currently pending, of which claims 1-3 and 5-20 are currently rejected. Claim 4 is currently objected.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an output circuit coupled to the digital logic circuitry” as separate components as disclosed in claim 3 must be shown or the feature(s) canceled from the claim(s). Closest figures showing these features are figures 2 and 3, which show an output circuit 210, and digital logic circuitry 310 inside the output circuit. However, there is no figure that shows the digital logic circuitry as a separate component coupled to the output circuit. No new matter should be entered.
Figure 4A should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Paragraph 0007 and 0033 describe Figure 4A as conventional.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
This application does not contain an abstract of the disclosure as required by 37 CFR 1.72(b). An abstract on a separate sheet is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-9, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Best (U.S. Patent Application Publication No.: US 20170344343 A1), (cited in IDS on 03/08/2024) hereinafter “Best”, in view of Margittai (U.S. Patent Application Publication No.: US 20090243734 A1) (cited in IDS on 10/03/2022), hereinafter “Margittai”.
Regarding Claim 1, Best teaches:
An integrated circuit comprising:
a set of latches organized to form a ring oscillator in a transparent mode (Fig. 1, e.g., shows a chain of chaotic pattern generators (CGs) 102 receiving pass signal (transparent mode); ¶0017, e.g., CGs include internal latches, and are organized in a ring topology; ¶0018, e.g., internal latch in CG is transparent when Pass signal is active), wherein the ring oscillator comprises an [even] number of signal inversions (Fig. 1, e.g., there are 9 CGs in the ring oscillator; Fig. 3, e.g., each CG contains a pair of inverters); and
digital logic circuitry coupled to the set of latches (Fig. 1, e.g., shows pair of inverters 106 and Flip-Flop 104 (digital logic circuitry)), wherein the digital logic circuitry is configured to determine a unpredictable output value of a state of outputs of the set of latches and generate a random digital number sample in a latch mode (¶0018, e.g., capture signal (latch mode) causes the Flip-Flop 104 to capture the current state of the CGs; ¶0017, e.g., random digital value 103 is outputted).
Best does not teach:
wherein the ring oscillator comprises an odd number of signal inversions
However, Margittai teaches using inverting D latches in a ring oscillator, where the number of inverting elements is an odd number. Margittai explains “The ring oscillator circuit has an odd number of ordered inverting elements. The ring oscillator circuit 200 may contain any number or order of inverting elements such as: NAND gates, NOR gates, NOT gates, or inverting memory elements as long as the total number of inverting elements is odd.” (Margittai: ¶0027)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the latches in each CG as taught by Best for the inverting D latches as taught by Margittai. One would have been motivated to perform the substitution using these references because both references disclose ring oscillators using latches, and Margittai enhances the model of Best because “due to the odd number of inverting elements, a sequence of logic 101010 . . . propagates through the ring oscillator. Thus, the starter may cause the output ports of the inverting elements to oscillate.” (Margittai: ¶0025). Combination would cause for each latch in the CGs taught by Best to output an inverted signal, cause for an odd number of signal inversions in the ring.
Regarding Claim 2, Best in view of Margittai teach:
The integrated circuit of claim 1, wherein the set of latches comprises a first latch, a second latch, and a third latch (Best: Fig. 1, e.g., shows plurality of CGs (first, second, and third latches)), and wherein the first latch comprises:
a first input coupled to a second inverting output of the second latch (Best: Fig. 1, e.g., shows CGs receiving, as inputs, outputs from a previous CG; Margittai: Fig. 2, e.g., Latches invert output before being input to next latch);
a first inverting output coupled to a third input of the third latch (Best: Fig. 1, e.g., shows CGs receiving, as inputs, outputs from a previous CG; Margittai: Fig. 2, e.g., Latches invert output before being input to next latch);
an enable input configured to receive a capture signal (Best: ¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs; Fig. 1, e.g., shows CGs receiving capture signal (enable input)); and
a first non-inverting output, the first latch to propagate a state of the first input to the first non-inverting output directly and an inverted state of the first input to the first inverting output when the capture signal is inactive in the transparent mode and to stop propagating the state of the first input to the first non-inverting output and the first inverting output when the capture signal is active in the latch mode, wherein the state of the first input is one bit for generating the random digital number sample (Best: ¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs when the capture signal is active; ¶0017, e.g., random digital value 103 is outputted).
The motivation to combine provided with respect to claim 1 applies equally to claim 2.
Regarding Claim 3, Best in view of Margittai teach:
The integrated circuit of claim 2, further comprising an output circuit coupled to the digital logic circuitry and configured to sample and hold the random digital number sample (Best: ¶0018, e.g., captured state is sampled by FFs 104 (digital logic circuitry)).
Regarding Claim 7, Best teaches:
An integrated circuit comprising:
a ring oscillator comprising a set of latches arranged in a looping sequence (Fig. 1, e.g., shows a chain of chaotic pattern generators (CGs) 102; ¶0017, e.g., CGs include internal latches, and are organized in a looping sequence ring topology), the ring oscillator to operate as a free-running oscillator (FRO) in a first mode and to capture a ring state of the free-running oscillator in a second mode (Fig. 1, e.g., shows a chain of chaotic pattern generators (CGs) 102 receiving pass signal (first mode), or a capture signal (second mode); ¶0018, e.g., internal latch in CG is transparent (free-running oscillator) when Pass signal (first mode) is active, and capture signal (second mode) causes the Flip-Flop 104 to capture the current state of the CGs ), wherein an input of a first latch of the set of latches is coupled to an … output of a second latch of the set of latches that is earlier in the looping sequence (Fig. 1, e.g., shows CGs receiving, as inputs, outputs from a previous CG), and wherein an … output of the first latch is coupled to an input of a third latch that is later in the looping sequence (Fig. 1, e.g., shows CGs receiving, as inputs, outputs from a previous CG); and
an output circuit coupled to the ring oscillator (Fig. 1, e.g., shows pair of inverters 106 and Flip-Flop 104 (output circuit)), wherein the output circuit is configured to receive the ring state, determine a unpredictable output value of the ring state, and output a random digital value based on the unpredictable output value ((¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs; ¶0017, e.g., random digital value 103 is outputted).
Best does not teach:
wherein an input of a first latch of the set of latches is coupled to an inverted output of a second latch of the set of latches that is earlier in the looping sequence ), and wherein an inverted output of the first latch is coupled to an input of a third latch that is later in the looping sequence;
However, Margittai teaches using inverting D latches in a ring oscillator, where the number of inverting elements is an odd number. Margittai explains “The ring oscillator circuit has an odd number of ordered inverting elements. The ring oscillator circuit 200 may contain any number or order of inverting elements such as: NAND gates, NOR gates, NOT gates, or inverting memory elements as long as the total number of inverting elements is odd.” (Margittai: ¶0027)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the latches in each CG as taught by Best for the inverting D latches as taught by Margittai. One would have been motivated to perform the substitution using these references because both references disclose ring oscillators using latches, and Margittai enhances the model of Best because “due to the odd number of inverting elements, a sequence of logic 101010 . . . propagates through the ring oscillator. Thus, the starter may cause the output ports of the inverting elements to oscillate.” (Margittai: ¶0025).
Regarding Claim 8, Best in view of Margittai teach:
The integrated circuit of claim 7, wherein the set of latches comprises an odd number of signal inversions (Margittai: Fig. 2, e.g., Latches invert output before being input to next latch; Combination would cause for each CG to include an inverter on the output of the latch, resulting in an odd number of signal inversions in the ring topology).
The motivation to combine provided with respect to claim 7 applies equally to claim 8.
Regarding Claim 9, Best in view of Margittai teach:
The integrated circuit of claim 7, wherein the ring oscillator is configured to receive a capture signal, wherein the ring oscillator is configured to permit cyclic pattern generation when the capture signal is not active and to stop the cyclic pattern generation when the capture signal is active (Best: ¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs when the capture signal is active. Internal latch in CG is transparent (cyclic pattern generation) when Pass signal is active (capture signal not active)).
Regarding Claim 14, Best teaches:
An integrated circuit comprising:
a ring oscillator comprising a set of latches arranged in a looping sequence (Fig. 1, e.g., shows a chain of chaotic pattern generators (CGs) 102; ¶0017, e.g., CGs include internal latches, and are organized in a looping sequence ring topology), the ring oscillator to generate a random digital value (¶0022, e.g., current state of the CGs are captured as random digital values), wherein a first latch of the set of latches is coupled to a second latch of the set of latches that is earlier in the looping sequence and to a third latch that is later in the looping sequence (Fig. 1, e.g., CGs are arranged in a sequence, where a CG is coupled to a CG to provide the input and another CG to receive the output), wherein the first latch comprises:
a first input coupled to a second … output of the second latch (Fig. 1, e.g., shows CGs receiving, as inputs, outputs from a previous CG);
a first … output coupled to a third input of the third latch (Fig. 1, e.g., shows CGs receiving, as inputs, outputs from a previous CG);
an enable input configured to receive a capture signal (¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs; Fig. 1, e.g., shows CGs receiving capture signal (enable input)); and
a first non-inverting output, the first latch to pass through a state of the first input to the first non-inverting output when the capture signal is inactive and to latch a final input state of the first input on the first non-inverting output when the capture signal is active, wherein the final input state is one bit of the random digital value (¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs when the capture signal is active; ¶0017, e.g., random digital value 103 is outputted).
Best does not teach:
a first input coupled to a second inverting output of the second latch
a first inverting output coupled to a third input of the third latch
However, Margittai teaches using inverting D latches in a ring oscillator, where the number of inverting elements is an odd number. Margittai explains “The ring oscillator circuit has an odd number of ordered inverting elements. The ring oscillator circuit 200 may contain any number or order of inverting elements such as: NAND gates, NOR gates, NOT gates, or inverting memory elements as long as the total number of inverting elements is odd.” (Margittai: ¶0027)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the latches in each CG as taught by Best for the inverting D latches as taught by Margittai. One would have been motivated to perform the substitution using these references because both references disclose ring oscillators using latches, and Margittai enhances the model of Best because “due to the odd number of inverting elements, a sequence of logic 101010 . . . propagates through the ring oscillator. Thus, the starter may cause the output ports of the inverting elements to oscillate.” (Margittai: ¶0025).
Regarding Claim 15, Best in view of Margittai teach:
The integrated circuit of claim 14, wherein the ring oscillator is configured to implement a free-running oscillator (FRO) function to generate the random digital value (Best: ¶0018, e.g., Internal latch in CG is transparent (free-running oscillator) when Pass signal is active).
Regarding Claim 16, Best in view of Margittai teach:
The integrated circuit of claim 14, wherein the set of latches comprises an odd number of latches (Margittai: Fig. 2, e.g., Latches invert output before being input to next latch; Combination would cause for each CG to include an inverter on the output of the latch, resulting in an odd number of signal inversions in the ring topology).
The motivation to combine provided with respect to claim 14 applies equally to claim 16.
Regarding Claim 17, Best in view of Margittai teach:
The integrated circuit of claim 14, wherein the ring oscillator is configured to permit cyclic pattern generation when the capture signal is not active and to stop the cyclic pattern generation when the capture signal is active (Best: ¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs when the capture signal is active. Internal latch in CG is transparent (cyclic pattern generation) when Pass signal is active (capture signal not active)).
Regarding Claim 18, Best in view of Margittai teach:
The integrated circuit of claim 14, further comprising a flip-flop to sample and hold the random digital value when the capture signal is active, wherein the flip-flop is clocked by a clock signal that is independent from the capture signal (Best: ¶0018, e.g., captured state is sampled by FFs 104. FFs 104 are clocked by other clock signals in the system (independent from the capture signal)).
Regarding Claim 19, it is a method claim practiced by the apparatus of claim 1. It is rejected for the same reasons as claim 1.
Claims 5-6, 10, 12-13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Best in view of Margittai, further in view of Aoyagi (U.S. Patent Application Publication No.: US 20180196641 A1), hereinafter “Aoyagi”.
Regarding Claim 5, Best in view of Margittai teach the integrated circuit of claim 2. Best in view of Margittai do not teach:
wherein the digital logic circuitry comprises an exclusive OR (XOR) reduction circuit coupled to the set of latches, wherein the XOR reduction circuit is configured to determine a parity value of the state of outputs as the unpredictable output value and output the random digital number sample based on the parity value.
However, Aoyagi teaches:
wherein the digital logic circuitry comprises an exclusive OR (XOR) reduction circuit coupled to the set of [ring oscillators] (Fig. 4, e.g., shows Ring Oscillators coupled to High-Speed Clock Selecting Unit 104 and XOR gate 105), wherein the XOR reduction circuit is configured to determine a parity value of the state of outputs as the unpredictable output value and output the random digital number sample based on the parity value (¶0060, e.g., XOR gate is used for increase the number of toggles of data, hence it increases the randomness in the random number generation; Fig. 4, e.g., shows XOR gate 105 outputting signal Q (parity value) based on outputs of ring oscillators).
Therefore, it would have been obvious to one skilled in the art to modify the all-digital random number generator (RNG) 100 as taught by Best in view of Margittai to include the High-Speed Clock Selecting Unit 104 and XOR gate 105 to input signal Q to the FF outputting a random value as taught by Aoyagi. One would have been motivated to perform this modification because both references disclose random number generation using ring oscillators, and Aoyagi enhances the model of Best in view of Margittai because “This can increase the randomness in the random number generation.” (Aoyagi: ¶0060)
Regarding Claim 6, Best in view of Margittai teach:
The integrated circuit of claim 1, wherein the digital logic circuitry comprises:
an inverter (Best: Fig. 1, e.g., shows inverters 106 receiving capture signal);
… wherein the inverter is configured to receive a capture signal indicative of the latch mode and output an inverted capture signal (Best: Fig. 1, e.g., shows inverters 106 receiving capture signal, where one inverter outputs an inverted capture signal), wherein each of the set of latches is configured to receive the capture signal and output a latch state (Best: Fig. 1, e.g., CGs receive capture state),
Best in view of Margittai do not teach:
wherein the digital logic circuitry comprises:
…
a set of AND logic gates; and
an exclusive OR (XOR) reduction circuit coupled to the set of AND logic gates,
…
wherein each of the set of AND logic gates is configured to receive the inverted capture signal and the latch state from one of the set of latches and output a captured logic state,
wherein the XOR reduction circuit is configured to determine a parity value of the state of outputs as the unpredictable output value and generate the random digital number sample in the latch mode based on the parity value.
However, Aoyagi teaches:
a set of AND logic gates (Fig. 4, e.g., high-speed clock selecting unit 104 including AND gates); and
an exclusive OR (XOR) reduction circuit coupled to the set of AND logic gates (Fig. 4, e.g., shows XOR Gate 105 coupled to the AND gates in the high-speed clock selecting unit 104),
…
wherein each of the set of AND logic gates is configured to receive the … [select] signal and the [high-speed clock signal] from one of the set of [ring oscillators] and output a [high-speed clock signal] (¶0055, e.g., AND gates receive output form ring oscillators and selection signals to select a high-speed clock),
wherein the XOR reduction circuit is configured to determine a parity value of the state of outputs as the unpredictable output value and generate the random digital number sample in the latch mode based on the parity value (¶0060, e.g., XOR gate is used for increase the number of toggles of data, hence it increases the randomness in the random number generation; Fig. 4, e.g., shows XOR gate 105 outputting signal Q (parity value) based on outputs of ring oscillators).
The motivation to combine provided with respect to claim 5 applies equally to claim 6. Combination would cause for the high-speed clock selecting unit 104 as taught by Aoyagi to receive inverted capture signal from inverters 106, and the state of the CGs to output a captured logic state as taught by Best.
Regarding Claim 10, Best in view of Margittai teach the integrated circuit of claim 7. Best in view of Margittai do not teach:
The integrated circuit of claim 7, wherein the output circuit comprises an exclusive OR (XOR) reduction circuit coupled to the set of latches, wherein the XOR reduction circuit is configured to determine a parity value of the ring state as the unpredictable output value and output the random digital value based on the parity value.
However, Aoyagi teaches:
wherein the output circuit comprises an exclusive OR (XOR) reduction circuit coupled to the set of [ring oscillators] (Fig. 4, e.g., shows Ring Oscillators coupled to High-Speed Clock Selecting Unit 104 and XOR gate 105), wherein the XOR reduction circuit is configured to determine a parity value of the ring state as the unpredictable output value and output the random digital value based on the parity value (¶0060, e.g., XOR gate is used for increase the number of toggles of data, hence it increases the randomness in the random number generation; Fig. 4, e.g., shows XOR gate 105 outputting signal Q (parity value) based on outputs of ring oscillators).
Therefore, it would have been obvious to one skilled in the art to modify the all-digital random number generator (RNG) 100 as taught by Best in view of Margittai to include the High-Speed Clock Selecting Unit 104 and XOR gate 105 to input signal Q to the FF outputting a random value as taught by Aoyagi. One would have been motivated to perform this modification because both references disclose random number generation using ring oscillators, and Aoyagi enhances the model of Best in view of Margittai because “This can increase the randomness in the random number generation.” (Aoyagi: ¶0060)
Regarding Claim 12, Best in view of Margittai teach:
wherein the output circuit comprises:
…
a flip-flop comprising an input coupled to an output of the [CGs], wherein the flip-flop is to output the random digital value when in the second mode (Best: Fig. 1, e.g., shows FF 104 receiving output from CGs; ¶0018, e.g., capture signal causes the Flip-Flop 104 to capture the current state of the CGs when the capture signal is active).
Best in view of Margittai do not teach:
wherein the output circuit comprises:
an exclusive OR (XOR) reduction circuit coupled to the set of latches, wherein the XOR reduction circuit is configured to determine a parity value of the ring state as the unpredictable output value and output the random digital value based on the parity value; and
a flip-flop comprising an input coupled to an output of the XOR reduction circuit, wherein the flip-flop is to output the random digital value when in the second mode.
However, Aoyagi teaches
an exclusive OR (XOR) reduction circuit coupled to the set of [ring oscillators] (Fig. 4, e.g., shows Ring Oscillators coupled to High-Speed Clock Selecting Unit 104 and XOR gate 105), wherein the XOR reduction circuit is configured to determine a parity value of the ring state as the unpredictable output value and output the random digital value based on the parity value (¶0060, e.g., XOR gate is used for increase the number of toggles of data, hence it increases the randomness in the random number generation; Fig. 4, e.g., shows XOR gate 105 outputting signal Q (parity value) based on outputs of ring oscillators); and
a flip-flop comprising an input coupled to an output of the XOR reduction circuit (Fig. 4, e.g., shows FF 106 connected to the output of the XOR gate 105)
The motivation to combine provided with respect to claim 10 applies equally to claim 12.
Regarding Claim 13, Best in view of Margittai in view of Aoyagi teach:
The integrated circuit of claim 12, further comprising:
an inverter coupled to receive a capture signal (Best: shows inverters 106 receiving capture signal); and
a set of logic gates coupled to the inverter and the XOR reduction circuit and each of the set of logic gates is coupled to one of the set of latches (Aoyagi: Fig. 4, e.g., shows high-speed clock selecting unit 104 including AND gates coupled to each ring oscillator and the XOR Gate; Combination would cause for the AND gates to be coupled to the CGs taught by Best, and for the inverters 106 taught by Best).
The motivation to combine provided with respect to claim 10 applies equally to claim 13.
Regarding Claim 20, it is a method claim practiced by the apparatus of claim 5. It is rejected for the same reasons as claim 5.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Best in view of Margittai, further in view of Tanamoto et al. (U.S. Patent Application Publication No.: US 20160277025 A1), hereinafter “Tanamoto”.
Regarding Claim 11, Best in view of Margittai teach the integrated circuit of claim 7. Best in view of Margittai do not teach:
wherein the output circuit comprises a hash function to generate the random digital value based on the ring state.
However, Tanamoto teaches:
wherein the output circuit comprises a hash function to generate the random digital value (¶0086, e.g., hash generating circuit generates a cryptographic key by attaching a hash function to the output) …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the all-digital random number generator (RNG) 100 as taught by Best in view of Margittai to include the hash generating circuit on its output as taught by Tanamoto. One would have been motivated perform this modification using these references because both references disclose random number generation using ring oscillators, and Tanamoto enhances the model of Best in view of Margittai by allowing for the random number generation to be used for cryptographic key generation. See Tanamoto ¶0086.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Best teaches all-digital random number generator (RNG) 100 including a chain of chaotic pattern generators (CGs) 102, organized in a looping sequence, to generate a random digital value 103 using FF 104. This RNG uses a capture/pass signal to indicate the capturing of the state of the CGs including latches. See ¶0017-0026. Best does not teach or suggest using a multiplexer to receive output from the flip-flop, and where this multiplexer outputs data to the flip-flop. Instead, Best teaches the Flip-flop receiving output directly from CGs, and separately receiving a capture signal. Therefore, Best does not teach or suggest the combination of claim 4, including the limitations “wherein the output circuit comprises: a multiplexer coupled to an output of the digital logic circuitry; and a flip-flop comprising an input coupled to an output of the multiplexer, wherein the multiplexer is configured to receive an output of the flip-flop and the output of the digital logic circuitry, wherein the multiplexer is configured to select the output of the digital logic circuitry when the capture signal is active in the latch mode.”
Margittai teaches a ring oscillator circuit 200 that uses a set of odd number of inverting latches, where these latches are controlled by a starter that produces a start/stop signal and a switch 250 that enables the ports of the inverting latches using a clock signal. Margittai does not teach or suggest using a multiplexer to receive output from the flip-flop, and where this multiplexer outputs data to the flip-flop. Instead, Margittai uses a counter to count the number of oscillations of the ring oscillator. Therefore, Margittai does not teach or suggest the combination of claim 4, including the limitations “wherein the output circuit comprises: a multiplexer coupled to an output of the digital logic circuitry; and a flip-flop comprising an input coupled to an output of the multiplexer, wherein the multiplexer is configured to receive an output of the flip-flop and the output of the digital logic circuitry, wherein the multiplexer is configured to select the output of the digital logic circuitry when the capture signal is active in the latch mode.”
Aoyagi teaches a block diagram illustrating a random number generating apparatus (100), where the random number generating apparatus uses a set of ring oscillators using different number of inverters. The output of these inverters is input into AND gates from a high-speed clock selecting unit 104. XOR Gate 105 receives outputs from the AND Gates, and outputs signal Q to the FF 106, which outputs a random number. Aoyagi does not teach or suggest using a multiplexer to receive output from the flip-flop, and where this multiplexer outputs data to the flip-flop. Instead, Aoyagi outputs the random number directly from the flipflop, and there is no feedback of this output into a multiplexer. Therefore, Aoyagi does not teach or suggest the combination of claim 4, including the limitations “wherein the output circuit comprises: a multiplexer coupled to an output of the digital logic circuitry; and a flip-flop comprising an input coupled to an output of the multiplexer, wherein the multiplexer is configured to receive an output of the flip-flop and the output of the digital logic circuitry, wherein the multiplexer is configured to select the output of the digital logic circuitry when the capture signal is active in the latch mode.”
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
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