Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The response received on 5/7/2026 has been placed in the file and was considered by the examiner. An action on the merit follows.
Response to Amendment
The amendments filed on 2026 May 7 have been fully considered. Response to these amendments is provided below.
Summary of Amendment/ Arguments and Examiner’s Response:
The applicant has amended the claims and has argued that the prior art does not teach the amended limitations.
All arguments are moot in view of new grounds of rejection, below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by U.S. Patent Application Publication No. 20060171593 (Hayakawa et al).
Regarding claim 1, Hayakawa et al discloses a method of facilitating inspection of a wafer (fig. 3), the method performed by a semiconductor wafer inspection system (fig. 1) and comprising: identifying, by the semiconductor wafer inspection system (fig. 1), a plurality of repeating patterns from reference image data associated with a layout design of the wafer by inputting the shot matrix and finding the layout of the die in the shot, the presence of the die, etc (fig. 3, s6, page 8, paragraph 99), the die being repeating patterns as seen in fig. 2, wherein the plurality of repeating patterns in the reference image data have a first characteristic, i.e. the characteristics defined by the cell areas seen in fig. 5 in each of the die of fig. 4, item 107; determining a pattern feature of one of the identified plurality of repeating patterns, i.e. a pitch of the cell area (fig. 5, fig. 3, s8) based on a change of the first characteristic between a first region and a second region within one of the plurality of repeating patterns in the reference image data (fig. 5, pitch is determined for each area which is determined to have a change/ be different, fig. 6, “set cell area A” and “set cell area B”), wherein the pattern feature includes an edge portion or a non-edge area, fig. 6, pattern features includes edge areas and non-edge areas in the cell areas shown distinguishing the first region from the second region, the regions of area a are distinguished from the regions of area b, as they look different; and causing a first area of the wafer corresponding to the determined pattern feature to be evaluated (fig. 6, “set cell comparison pitch 1”, fig. 3, s12- s14).
Claims 2 and 15 are rejected for the same reasons as claim 1. Thus, the arguments analogous to that presented above for claim 1are equally applicable to claims 2 and 15. Claims 2 and 15 distinguish from claim 1 only in that claim 2 is an apparatus for facilitating inspection of a wafer, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause a semiconductor wafer inspection system to perform operations of claim 1, and claim 15 is a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of semiconductor wafer inspection system to cause the semiconductor wafer inspection system to perform operations for extracting pattern contour information from an inspection image, the operations being operations of the method of claim 1. Hayakawa et al teaches further this feature, i.e. an apparatus for facilitating inspection of a wafer (fig. 2), comprising: a memory storing a set of instructions (fig. 1, items 58,59); and at least one processor (fig. 1, items 5,6) configured to execute the set of instructions (fig. 1, items 57, 58, 59), and a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of semiconductor wafer inspection system (fig. 1, items 58, 59, 6).
Regarding claim 3, the plurality of repeating patterns corresponds to a plurality of array cells on the wafer (fig. 2, item 55, fig. 5).
Regarding claim 4, the plurality of array cells correspond to a plurality of memory cells (pages 2-3, paragraph 17).
Regarding claim 5, the first characteristic of the plurality of repeating patterns includes a density of features associated with the repeating patterns, i.e. how dense the cells are spaced, defined by the pitch (fig. 5).
Regarding claim 6, the first characteristic of the plurality of repeating patterns includes a pitch associated with the repeating patterns (fig. 5).
Regarding claim 7, the first characteristic of the plurality of repeating patterns includes a shape associated with the repeating patterns (fig. 6, user designates the cell areas based on differences in shape as can be seen by the different cell shape).
Regarding claim 8, the pattern feature includes an edge portion of a repeating pattern of the plurality of repeating patterns, fig. 6, pattern features includes edge portions of repeating pattern, in the cell areas shown.
Regarding claim 9, causing the first area of the wafer to be evaluated comprises: causing to detect one or more defects in the first area corresponding to the determined pattern feature (fig. 8, item 46- defects discriminated based on areas in storing means item 45).
Regarding claim 10, causing the first area of the wafer to be evaluated comprises: identifying the first area on the wafer corresponding to the determined pattern feature (fig. 8, “inspection information”); and causing an inspection system to inspect the identified first area on the wafer (fig. 8, “defect discriminating unit”, “defect analyzing unit”).
Regarding claim 11, the at least one processor is configured to execute the set of instructions to cause the apparatus to further perform: causing the inspection system to inspect the identified first area using a first parameter, i.e. the parameters defined for recipe info of cell area A of fig. 8; and causing the inspection system to inspect a second area on the wafer using a second parameter, i.e. the parameters defined for recipe info of cell area B of fig. 8.
Regarding claim 12, causing the first area of the wafer to be evaluated comprises: obtaining inspection image data of the wafer from an inspection system after performing the inspection of the wafer, i.e. obtaining the image data (fig. 3, item s12-s15) after the inspection to create the recipe of fig. 3, items s1-s10; identifying, from the obtained inspection image data of the wafer, a set of inspection image data associated with the first area on the wafer corresponding to the determined pattern feature (fig. 8, ”inspection information”); and evaluating the identified set of inspection image data based on the determined pattern feature in the reference image data (fig. 8, “cell comparison” and “defect discriminating” with image data in storing means).
Regarding claim 13, the inspection of the wafer is performed using a charged-particle beam inspection system (page 4, paragraph 54).
Regarding claim 14, the apparatus is communicatively coupled to or integrated in a charged particle multi-beam system (page 4, paragraph 54).
Claim 16 is rejected for the same reasons as claim 9. Thus, the arguments analogous to that presented above for claim 9 are equally applicable to claim 16. Claim 16 distinguishes from claim 9 only in that they have different dependencies, both of which have been previously rejected. Therefore, prior art applies.
Claims 17 and 19 are rejected for the same reasons as claim 10. Thus, the arguments analogous to that presented above for claim 10 are equally applicable to claims 17 and 19. Claims 17 and 19 distinguish from claim 10 only in that they have different dependencies, both of which have been previously rejected. Therefore, prior art applies.
Regarding claim 18, causing the first area of the wafer corresponding to the determined pattern feature to be evaluated (fig. 8, fig. 3, item s12-s14) comprises inspecting the first area (fig. 8, both areas inspected) using a charged-particle beam inspection system (fig. 1, page 4, paragraph 54).
Claim 20 is rejected for the same reasons as claim 18. Thus, the arguments analogous to that presented above for claim 18 are equally applicable to claim 20. Claim 20 distinguishes from claim 18 only in that they have different dependencies, both of which have been previously rejected. Therefore, prior art applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kathleen Yuan Dulaney whose telephone number is (571)272-2902. The examiner can normally be reached M-F: 9AM-5PM.
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/KATHLEEN Y DULANEY/Primary Examiner, Art Unit 2666 6/3/2026
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