DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/29/2026 has been entered.
Response to Arguments
Applicant's arguments filed 01/29/2026 have been fully considered but they are moot in view of the new grounds of rejection or indication of allowable subject matter in light of Applicant’s claim amendments as detailed below.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12,14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites a first nucleation layer configured to form the first channel layer from a substrate. However, claim 10 depends on claim 1 and claim 1 has been amended to recite “wherein the semiconductor device is devoid of a substrate”. Consequently, claim 10 is indefinite for reciting a substrate when claim 1 has been amended to specify that the device is devoid of a substrate. Claims 11,12,14,15 are indefinite insofar as they depend on claim 10 thereby inheriting the indefinite language of claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2,7-11,14,16-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0091219 A1 to Patti, “Patti”, in view of U.S. Patent Application Publication Number 2020/0381300 A1 to Zhang et al., “Zhang”.
Regarding claim 1, Patti discloses a semiconductor device (e.g. FIG. 1A,1B) comprising:
a first channel layer (14a, ¶ [0028]-[0029]);
a first barrier layer (14b, ¶ [0028]-[0029]), wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and
a vertical 2DEG (16, ¶ [0030]-[0031]) is formed in the first heterojunction;
a first electrode (18, ¶ [0026],[0031]) positioned on an upper side of the first heterojunction and configured to have electrical contact (source) with 2DEG within the first heterojunction, wherein the first electrode (18) is connected to a first external voltage (source voltage) above the first heterojunction; and
a second electrode (12 and/or 20, ¶ [0026],[0031]) positioned at a lower side of the first heterojunction and configured to have electrical contact (drain) with 2DEG within the first heterojunction, wherein the second electrode (12 and/or 20) is connected to a second external voltage (drain voltage) below the first heterojunction.
Patti fails to clearly teach wherein the semiconductor device is devoid of a substrate (e.g. removing the substrate).
Zhang teaches (e.g. FIG. 1 to FIG. 8) forming vertical channel (106 and 108, ¶[0036]) field effect transistors and (from FIG. 9 to FIG. 10) removing the substrate (104, ¶ [0071]) in order to form (FIG. 13) backside electrical contacts (1302 and 1304, ¶ [0073]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Patti by removing the substrate as taught by Zhang in order to either 1) be able to stack multiple vertical transistors together in a single structure thereby achieving higher density scaling (Zhang ¶ [0002],[0003],[0035]) and/or 2) allow for a plurality of backside electrical contacts which also reduces the area allowing for a denser circuit layout (Zhang ¶ [0002],[0004],[0005],[0035]).
Examiner’s Note: although prior art generally teaches removing the substrate to form backside contacts such that the resulting device is devoid of a substrate, Applicant teaches (e.g. FIG. 4) removing the substate and forming insulating material (415, ¶ [0078]) contacting the nucleation layer (402A,402B) between vertical 2DEGs (e.g. 402A,403B) which is not taught by the combination of Patti in view of Zhang. Although Zhang teaches an insulator (28 or 32) between the vertical 2DEGs (16), the space opposite the 2DEG is filled with epitaxial semiconductor 24.
Regarding claim 2, Patti in view of Zhang yields the semiconductor device according to claim 1, and Patti further discloses wherein the upper side (where electrode 18 contacts 14) is a portion above the center line position of the first heterojunction (as pictured); and the lower side (wherein electrode 12/20 contacts 14) is a portion below the center line position of the first heterojunction (as pictured).
Regarding claim 7, Patti in view of Zhang yields the semiconductor device according to claim 1, and Patti further discloses a third electrode (30/32, ¶ [036]) positioned between the first electrode (18) and the second electrode (20) and configured to control a current between the first electrode and the second electrode (i.e. a gate).
Regarding claim 8, Patti in view of Zhang yields the semiconductor device according to claim 7, and Patti further discloses wherein (a portion of) the third electrode (30/32) is positioned above the center line position of the first heterojunction (see Examiner-annotated figure below):
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Examiner’s Note: claim 8 states wherein the third electrode is positioned above the center line, but claim 8 does not specify whether only a part of the third electrode or the entire third electrode is positioned above the centerline and so the former interpretation is adopted since claims are interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111).
Regarding claim 9, Patti in view of Zhang yields the semiconductor device according to claim 7, and Patti further discloses wherein the third electrode (30) is connected to a third external voltage (gate voltage, ¶ [0036]) above the first heterojunction (i.e. through gate contact 22).
Regarding claim 10 insofar as definite, Patti in view of Zhang yields the semiconductor device of claim 1, and Patti further discloses a first nucleation layer (26, ¶ [0033]) configured to form the first channel layer (14a) from a substrate 12).
Regarding claim 11 insofar as definite, Patti in view of Zhang yields the semiconductor device according to claim 10, and Patti further discloses wherein the second electrode (12 and/or 20) is in electrical contact with 2DEG in the first heterojunction through the first nucleation layer (26).
Regarding claim 14 insofar as definite, Patti in view of Zhang yields the semiconductor device according to claim 10, and Patti further discloses wherein the first channel layer (14a) is positioned beside one side (as pictured) of the first nucleation layer (26).
Regarding claim 16, Patti in view of Zhang yields the semiconductor device according to claim 1, and Patti further discloses wherein one or more of the first channel layer or the first barrier layer (14a,14b) are defined by a hole (e.g. FIG. 9 hole in 26 as pictured).
Regarding claim 17, Patti in view of Zhang yields the semiconductor device according to claim 1, and Patti further discloses:
a first interconnection layer (portion of 18 above 32) positioned above the first heterojunction (14a/14b) and electrically connected to the first electrode (portion of 18 contacting 14a/14b); and
a second interconnection layer (e.g. 20 or lateral extensions of 20 beyond HEMT 60) positioned below the first heterojunction and electrically connected to the second electrode (e.g. 12).
Regarding claim 18, Patti in view of Zhang yields the semiconductor device according to claim 17, and Patti further discloses a third interconnection layer (e.g. gate contact 22, ¶ [0026],[0027]) electrically connected to the third electrode (30).
Regarding claim 19, Patti in view of Zhang yields the semiconductor device according to claim 1, and Patti further discloses
a second channel layer (other 14a, two 14a’s in each hole as pictured); and
a second barrier layer (other 14b, two 14b’s in each hole as pictured), wherein a second heterojunction having a vertical interface is formed between the second channel layer and the second barrier layer, and
a vertical 2DEG (other 16) is formed in the second heterojunction;
wherein the first electrode (18) is positioned on an upper side of the second heterojunction and configured to electrically contact 2DEG within the second heterojunction;
the second electrode (12 and/or 20) is positioned at a lower side of the second heterojunction and is configured to make electrical contact with 2DEG within the second heterojunction.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0091219 A1 to Patti, “Patti”, in view of U.S. Patent Application Publication Number 2020/0381300 A1 to Zhang et al., “Zhang”, further in view of U.S. Patent Application Publication Number 2014/0103357 A1 to DeCoutere et al., “DeCoutere”.
Regarding claim 6, although Patti in view of Zhang yields the semiconductor device according to claim 1, Patti fails to clearly teach wherein the first electrode and the first heterojunction are in Schottky contact; the second electrode is in Ohmic contact with the first heterojunction.
DeCoutere teaches wherein a first electrode (9) and a first heterojunction (4/5/6) are in Schottky contact (Abstract, ¶ [0037],[0038]-[0040]) and a second electrode (8) is in ohmic contact with the first heterojunction (Abstract, ¶ [0005],[0007],[0036]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Patti in view of Zhang as a Schottky diode in order to be able to integrate well within the same silicon die as conventional CMOS transistors and the like (Patti ¶ [0003]-[0005]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0091219 A1 to Patti, “Patti”, in view of U.S. Patent Application Publication Number 2020/0381300 A1 to Zhang et al., “Zhang”, further in view of U.S. Patent Application Publication Number 2011/0169012 A1 to Hersee et al., “Hersee”.
Regarding claim 12 insofar as definite, although Patti in view of Zhang yields the semiconductor device according to claim 10, Patti fails to clearly teach wherein the first nucleation layer (aluminum nitride (AlN) layer 26, ¶ [0033]) is doped.
Hersee teaches a doped buffer layer which can be aluminum nitride (AlN) (¶ [0034]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Patti in view of Zhang with the first nucleation layer (AlN buffer 26) being doped as taught by Hersee in order to grow high-quality (i.e. defect free) GaN (Hersee ¶ [0028],[0033],[0034]) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0091219 A1 to Patti, “Patti”, in view of U.S. Patent Application Publication Number 2020/0381300 A1 to Zhang et al., “Zhang”, further in view of U.S. Patent Application Publication Number 2021/0028303 A1 to Suzuki et al., “Suzuki”.
Regarding claim 15 insofar as definite, although Patti in view of Zhang yields the semiconductor device according to claim 11, Patti fails to clearly teach wherein the first channel layer is positioned above the first nucleation layer.
Suzuki teaches a first nucleation layer (bottom portion of 31, i.e. FIG. 5A,5B regions of 31 grown selectively on 2, ¶ [0068]) and wherein a first channel layer (upper lateral overgrowth of 31 forms a channel region) is positioned above the first nucleation layer (lower portion of 31, see Examiner-annotated figure below).
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It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have modified the growth method (FIGs. 7-11) of Patti in view of Zhang with the vertical and lateral epitaxial lateral overgrowth (ELO) method of Suzuki (Suzuki ¶ [0017],[0068],[0129]) in order to achieve a device with as little ON-state loss as possible (Suzuki ¶ [0010],[0079],[0124],[0136]-[0139]).
Allowable Subject Matter
Claim 20 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Patti discloses a method for manufacturing a semiconductor device, comprising:
forming (FIG. 8) a first nucleation layer (26, ¶ [0052]) at a vertical interface of a substrate (24);
epitaxially (FIG. 10) growing a first channel layer (14a, ¶ [0056],[0057]) from the first nucleation layer (26);
epitaxially (FIG. 11) growing a first barrier layer (14b, ¶ [0060],[0061]) from the first channel layer, wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG (16) is formed in the first heterojunction;
forming a first electrode (18, ¶ [0026],[0031]) and a second electrode (12 and/or 20, ¶ [0026],[0031]) on an upper side and a lower side of the first heterojunction respectively, wherein the first electrode (18) is in electrical contact with 2DEG in the first heterojunction, and the second electrode (12 and/or 20) is in electrical contact with 2DEG in the first heterojunction;
connecting the first electrode (18) to a first external voltage (source voltage) above the first heterojunction; and
connecting the second electrode (12 and/or 20) to a second external voltage (drain voltage) below the first heterojunction, as discussed previously.
Prior art e.g. U.S. Patent Application Publication Number 2021/0028303 A1 to Suzuki et al. teaches forming a plurality of semiconductor portions (3) including a heterostructure (37, ¶ [0055]) on a substrate (2), transferring, removing the substrate (2 ¶ [0093]), and then forming a plurality of second electrodes (5) thereon (¶ [0093]), as discussed previously.
Prior art e.g. U.S. Patent Application Publication Number 2015/0325689 A1 to Takeya et al. teaches growing non-planar 2DEGs (up to FIG. 7), turning over (between FIG. 9 and FIG. 10) the substrate (21) and exposing the heterojunctions (exposed upper surface in FIG. 10) and removing the substrate (¶ [0043]), and forming (e.g. FIG. 13) an electrode (60s) on the exposed heterojunctions, as discussed previously.
However, prior art fails to reasonably teach or suggest removing the substrate, exposing the first heterojunction, forming a second electrode on the exposed first heterojunction, wherein the semiconductor device is devoid of a substrate, together with all of the other limitations of the method of claim 20 as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication Number 2009/0152611 A1 to Fujimoto teaches (e.g. FIG. 23) removing a base substrate to form source/drain contacts (109, ¶ [0180]) to vertical transistor channels (20).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
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