Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 1, 3-4, 6-7, 9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda (PGPub No. 2011/0201271 A1) and in further view of Motoyama (PGPub No. 2019/0349029 A1).
Regarding claim 1, Kuroda teaches a semiconductor device comprising: three or more chips stacked on each other ([0001] points to a stacked semiconductor apparatus that comprises a stack of a plurality of devices, such as semiconductor chips.), wherein each of the chips comprises: a substrate (Fig. 1 and [0072] point to substrates 10 and 20.); a transmission coil; and a reception coil provided in a region where the reception coil does not overlap with the transmission coil in an in-plane direction of the substrate (Id. points to transmission coil 11 and reception coil 12 positioned on the same substrate 10 such that they do not overlap.), wherein the transmission coil is arranged in a region where the transmission coil is adjacent to and overlaps with the reception coil of another chip in a stacking direction (Id. points to transmission coil 11 from substrate 10 overlapping with reception coil 23 from substrate 20. See also reception coil 12 and transmission coil 24.), and the reception coil is configured such that data is transmittable between the reception coil and the transmission coil arranged on the same substrate (Id. points to a determination circuit 15 connected to the transmission circuit 13 and reception circuit 14.), and the chip comprises: a transmission circuit connected to the transmission coil to transmit transmission data to the transmission coil (Fig. 1 points to transmission circuit(s) 13/22 and transmission coil(s) 11 and 24, respectively.); a reception circuit connected to the reception coil to receive reception data from the reception coil (Id. points to reception circuit(s) 14/21 and reception coil(s) 12 and 23, respectively.).
Kuroda fails to teach a transmission-side driver that switches connection between the transmission coil and the transmission circuit; and a reception-side receiver that switches connection between the reception coil and the reception circuit.
Motoyama teaches a transmission-side driver that switches connection between the transmission coil and the transmission circuit (Figs. 4(b) points to transmission and reception state(s) for a layered semiconductor device comprising a plurality of memory chips DRAMR-DRAM7 and a transmission clock signal CLK (transmission circuit) that is initially transmitted to one of the transmission coils Tx38. It is thus considered obvious that each of the transmission coils and circuits further comprise a driver/switch between them that allows for a signal to be transmitted from a specific chip.); and a reception-side receiver that switches connection between the reception coil and the reception circuit (Fig. 4(a) points to each of the memory chips DRAMR-DRAM7 further comprising a reception coil Rx37 and a reception clock signal CLK (reception circuit). In light of Fig. 4(b), it is considered obvious that each of the reception coils and circuits further comprise a receiver/switch between them that redirects the signal towards a specific chip.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Kuroda and Motoyama, such that each of the stacked chips comprises a transmission-side switch and a reception-side switch in order to allow for individual transmissions to each chip and enable the stack to perform various processes.
Regarding claim 3, Kuroda teaches wherein the transmission coil is provided at a predetermined position on the substrate at a position opposing the reception coil with respect to a reference axis extending along the in-plane direction (Fig. 1 points to transmission coils 11 and 24 in relation to reception coils 12 and 23, respectively. Although not shown, the positioning of said coils anticipates a reference axis best defined as being located between the coils and perpendicular to the direction indicated by k11.).
Regarding claim 4, Kuroda teaches wherein the substrate comprises: a front surface as one surface in a thickness direction; and a back surface as the other surface in the thickness direction, wherein the front surface is stacked adjacent to the front surface of the substrate of another chip, and the back surface is stacked adjacent to the back surface of the substrate of still another chip (Fig. 1 and [0072] point to an electronic circuit of a semiconductor chip stack comprising two substrates 10 and 20 stacked onto each other, with transmission coil 11 inductively coupled to reception coil 23 and reception coil 12 inductively coupled to transmission coil 24. As the first substrate listed, substrate 10 and its surface as shown is interpreted to mean the same as “front surface” as used in the claimed invention; likewise, the surface of substrate 20 is interpreted to be a rotated version of the same “front surface” due to the positioning of the relevant coils and circuits listed. Additionally, [0001] points to the stack comprising a plurality of such semiconductor chips, which would thus lead one of ordinary skill in the art to believe that the stack consists of chips where each chip’s “front surface” faces another chip’s “front surface”, and by extension their “back surface” would face still another chip’s “back surface”.).
Regarding claim 6, Kuroda teaches wherein the substrate comprises: a front surface as one surface in a thickness direction; and a back surface as the other surface in the thickness direction, wherein the front surface is stacked adjacent to the back surface of the substrate of another chip, and the back surface is stacked adjacent to the front surface of the substrate of still another chip (Fig. 1 and [0072] point to an electronic circuit of a semiconductor chip stack comprising two substrates 10 and 20 stacked onto each other, with transmission coil 11 inductively coupled to reception coil 23 and reception coil 12 inductively coupled to transmission coil 24. As the first substrate listed, substrate 10 and its surface as shown is interpreted to mean the same as “front surface” as used in the claimed invention; likewise, the surface of substrate 20 is interpreted to mean the same as “back surface” as used in the claimed invention due to the flipped/opposite positioning of the relevant coils and circuits listed as compared to substrate 10. Additionally, [0001] points to the stack comprising a plurality of such semiconductor chips, which would thus lead one of ordinary skill in the art to believe that the stack consists of chips where each chip’s “front surface” faces another chip’s “back surface”, and by extension their “back surface” would face still another chip’s “front surface”.).
Regarding claim 7, Motoyama teaches wherein the transmission coil is, in the stacking direction, adjacent to the reception coil of another chip with at least one still another chip interposed therebetween (Fig. 4(b) and [0071] point to a transmission coil Tx38 located in DRAM7 that is adjacent in the stacking direction to the reception coil Rx39 located in A-I/P (another chip), with DRAMR-6 located in between (at least one still another chip interposed therebetween).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kuroda and Motoyama, such that another chip is interposed between the transmission coil and reception coil in order to electrically insulate both coils and reduce signal interference.
Regarding claim 9, Motoyama teaches wherein the transmission-side driver switches the connection between the transmission coil and the transmission circuit based on a transmission direction of the transmission data along the stacking direction (Figs. 4(b) points to transmission and reception state(s) for a layered semiconductor device comprising a plurality of memory chips DRAMR-DRAM7 and a transmission clock signal CLK (transmission circuit) that is initially transmitted to one of the transmission coils Tx38. It is thus considered obvious that each of the transmission coils and circuits further comprise a driver/switch between them that allows for a signal to be transmitted from a specific chip.), and the reception-side receiver switches the connection between the reception coil and the reception circuit according to switching by the transmission-side driver (Fig. 4(a) points to each of the memory chips DRAMR-DRAM7 further comprising a reception coil Rx37 and a reception clock signal CLK (reception circuit). In light of Fig. 4(b), it is considered obvious that each of the reception coils and circuits further comprise a receiver/switch between them that redirects the signal towards a specific chip.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kuroda and Motoyama, such that each of the stacked chips comprises a transmission-side switch and a reception-side switch in order to allow for individual transmissions to each chip and enable the stack to perform various processes.
Regarding claim 11, Kuroda teaches the semiconductor device being manufactured in such a manner that wafers are stacked on each other and are subsequently divided into pieces (Fig. 1, [0001], and [0072] point to a stacked semiconductor apparatus (semiconductor device) comprising a stack of a plurality of devices such as semiconductor chips (wafers), which are comprised of various regions of coils and circuits (divided into pieces).).
Regarding claim 12, Motoyama teaches wherein the transmission coil is, in the stacking direction, adjacent to the reception coil of another chip with at least one still another chip interposed therebetween (Fig. 4(b) and [0071] point to a transmission coil Tx38 located in DRAM7 that is adjacent in the stacking direction to the reception coil Rx39 located in A-I/P (another chip), with DRAMR-6 located in between (at least one still another chip interposed therebetween).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kuroda and Motoyama, such that another chip is interposed between the transmission coil and reception coil in order to electrically insulate both coils and reduce signal interference.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kuroda et al. in further view of Nakagawa (PGPub. 2010/0069000 A1).
Regarding claim 2, Nakagawa teaches wherein two or more pairs of the reception coil and the transmission coil are provided (Fig. 17 and [0143] point to a semiconductor device having a transmission and reception coil pair comprising a plurality of transmission coils and a plurality of reception coils (two or more pairs).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kuroda et al. and Nakagawa, such that multiple reception and transmission coils are provided in order to perform high-quality signal transmission without needing highly accurate positioning control.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda et al. in further view of Ogawa (PGPub No. 2019/0035768 A1).
Regarding claim 5, Ogawa teaches wherein the transmission coil is, on the substrate, provided at a predetermined position opposing the reception coil with respect to an intersection between two reference axes extending in the in- plane direction and extending perpendicular to each other (Fig. 2 and [0035] point to an interposer 3 (substrate) comprising transmission/reception coils C1-C4. The distances between C1-C3 and C2-C4 are interpreted as forming “two reference axes”, respectively, which meet in the middle of the four coils, as best defined as where the dotted line CL meets the interposer 3.). Thus, it would have been obvious for a POSITA prior to the filing date of the claimed invention to combine the teachings of Kuroda et al. and Ogawa, such that the transmission and reception coils are placed in symmetrical positions along a substrate to allow for easier stacking and by extension reduce fabrication costs.
Regarding claim 10, Ogawa teaches wherein the transmission coil is different from the reception coil in at least any one of number of turns, a wire width, an inter-wire space, or a wire to be used ([0036] points to a transmission/reception coil (T/R), a term used to generically refer to both transmission coils and reception coils, having various possible structures, such a number of turns of the T/R being set to any value, and the distance between the T/Rs being about half the size of the T/R itself.). Thus, it would have been obvious for a POSITA prior to the filing date of the claimed invention to combine the teachings of Kuroda et al. and Ogawa, such that the transmission and reception coils comprise different dimensions/geometries in order to achieve maximum power transfer and minimal reflection.
Response to Arguments
Applicant’s arguments, see Remarks, filed 07/29/2025, with respect to the rejection(s) of claim 1, and by extension claims 3, 9, and 11-12, under 35 U.S.C. §102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. §103 in view of Kuroda (PGPub No. 2011/0201271 A1) and in further view of Motoyama (PGPub No. 2019/0349029 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899