Attorney’s Docket Number: 3105-22SG1P6926-US
Filing Date: 10/20/2022
Claimed Priority Date: 11/26/2021 (PCT/CN2021/133706)
Applicant: Wang
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the RCE filed on 04/30/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1,2,5,6-15,18-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites “substrate is overlapped with an orthographic projection of opening region on the substrate”. It is unclear if “opening region” is referring to the same or different features, rendering the claim indefinite. For the purpose of examination, examiner understands this claim as – substrate is overlapped with an orthographic projection of the opening region on the substrate -- as introduced in the parent claim and best understood by the examiner in view of the original disclosure (Fig 6A), until further clarifications are provided by the applicant.
Claims 2, 5-9 depend on claim 1, thus inheriting the deficiency identified supra.
Claims 10-15,18-20 also recite “substrate is overlapped with an orthographic projection of opening region on the substrate”. It is unclear if “opening region” is referring to the same or different features, rendering the claim indefinite. For the purpose of examination, examiner understands this claim as – substrate is overlapped with an orthographic projection of the opening region on the substrate -- as introduced in the parent claim and best understood by the examiner in view of the original disclosure (Fig 6A), until further clarifications are provided by the applicant.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (CN 112913033 A, Hereinafter Yamazaki).
Regarding Claim 1, Yamazaki (Figures 1A-1D [0042] - [0139]) shows most aspects of the invention, including a field effect transistor, comprising:
a substrate ( oxide 230a and layers below);
an active layer disposed on a side of the substrate (oxide 230b);
a source and a drain disposed on a side of the active layer away from the substrate (240a and 240b);
a first insulating layer disposed on a side, away from the substrate, of the source and the drain, wherein the first insulating layer is provided with an opening region (insulator 280 with an opening in the middle) , the active layer comprises a target region in the opening region, and the target region is between the source and the drain (target region is between 240a and 240b in oxide 230b layer, “channel-forming region”); and
an oxygenating layer disposed on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate (230c is the oxygen supply layer, providing oxygen to the target region), wherein the field effect transistor further comprises:
wherein an orthographic projection of the first ate insulating layer on the substrate is overlapped with an orthographic projection of the opening region on the substrate; (Fig 1B shows the positioning)
a first ate disposed on a side of the first ate insulating layer away from the substrate (Gate 260),
While Yamazaki shows most aspects of the invention, it does not explicitly show in this embodiment of transistor 200 to have a first ate insulating layer disposed between the oxygenating layer and the first insulating layer. In another embodiment, (Fig 15B and [0332]) without oxide 230c, wherein the insulator 250 also has the effect of supplying oxygen to oxide 230a and oxide 230b ([0061]). And As can be seen in all of the figures, both layer are integral to each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the gate insulating layer in between the oxygenating layer and the first insulating layer as this change would serve the same purpose as an oxygen supply layer.
Regarding Claim 2, See comments from claim 1 as they would be considered repeated here.
Regarding Claim 5, Yamazaki shows the material of the oxygenating layer to be In-Ga-Zn oxide([0224])
Regarding Claim 6, Yamazaki shows the material of the first gate insulating layer to be silicon oxide([paragraph [0189]])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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