You DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Initiated Interview Summary dated on Feb. 10th 2026, with respect to Claim 1-8 have been fully considered and are persuasive. The Non-Final OA on Dec. 10th 2025 of claim 1-8 has been withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device with oxide electrode material and Method of Manufacturing the Same.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 22 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 22 failed to further limit the subject matter of the previous claim 19 since the dependent claim cited the semiconductor device that is already recited in parent claim 19. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kub et al. (US 20140264380) in view of Beach et al. (US 20050194612) and Iwakami et al. (US 20110233538).
Regarding claim 1, Kub teaches a method (Abstract) for manufacturing a semiconductor device (fig. 1, Field Effect Transistors FET; para. 0026), the method comprising:
forming a p-GaN layer (fig. 1, bottom panel, Nitrogen-Polar GaN and P-type doping; para.0034) on a substrate (substrate; para. 0026), the p-GaN layer (GaN) comprising p-type GaN (P-type doping; para. 0034) and having an N polar surface (Nitrogen-Polar; para. 0004);
forming an AlGaN layer (AlGaN) on the p-GaN layer (GaN), the AlGaN layer (AlGaN) having an N polar surface (non-inverted and Nitrogen-Polar; para. 0004);
Kub fails to explicitly teach the AlGaN layer comprising undoped AlGaN;
oxidizing a surface of the AlGaN layer to form a surface oxidized layer comprising AlGaON;
forming an electrode on the surface oxidized layer, the electrode comprising an electrode material containing Ni and being in contact with the surface oxidized layer; and
forming an oxide layer in a portion of the electrode in contact with the surface oxidized layer between the electrode and the AlGaN layer, the oxide layer comprising an oxide of the electrode material and being in contact with both the AlGaN layer and the electrode.
However, Beach teaches oxidizing (Beach: fig. 3B, localized oxidation; para. 0063) a surface of the AlGaN layer (Beach: AlGaN; para. 0063, similar to AlGaN of Kub) to form a surface oxidized layer comprising AlGaON (Beach: localized oxidized AlGaN; para. 0063) including AlGaON (Beach: AlGaON; para. 0063).
Beach and Kub are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add oxidizing a surface of the AlGaN layer as taught by Beach.
Doing so would realize a localized oxidation to reduce the local density of 2DEG (Beach: para. 0063).
In addition, Kub in view of Beach fails to explicitly teach the AlGaN layer comprising undoped AlGaN;
forming an electrode on the surface oxidized layer, the electrode comprising an electrode material containing Ni and being in contact with the surface oxidized layer; and
forming an oxide layer in a portion of the electrode in contact with the surface oxidized layer between the electrode and the AlGaN layer, the oxide layer comprising an oxide of the electrode material and being in contact with both the AlGaN layer and the electrode.
However, Iwakami teaches the AlGaN layer (Iwakami: fig. 14, carrier supply layer 22; para. 0022, similar to AlGaN of Kub) comprising undoped AlGaN (Iwakami: undoped AlGaN; para. 0029);
forming an electrode (Iwakami: fig. 9, NiO film 80, TiN film 51 and Al film 52 for control electrode 5; para. 0064) on the surface oxidized layer (Beach: localized oxidized AlGaN as top of 22 of Iwakami), the electrode (Iwakami: 51, 52) comprising an electrode material (Iwakami: material of Ni, Ti, Al; para. 0064) containing Ni (Iwakami: Ni; para. 0064) and being in contact with the surface oxidized layer (Beach: localized oxidized AlGaN as top of 22 of Iwakami); and
forming an oxide layer (fig. 14, metal oxide semiconductor film 8; para. 0022) in a portion of the electrode (Iwakami: portion of 80) in contact with the surface oxidized layer(Beach: localized oxidized AlGaN as top of 22 of Iwakami) between the electrode (Iwakami: 5 after heat) and the AlGaN layer (Iwakami: 22), the oxide layer (Iwakami: fig. 14, 8) comprising an oxide of the electrode material (Iwakami: fig. 3A, NiO; para. 0038) and being in contact with both the AlGaN layer (Iwakami: 22) and the electrode (Iwakami: 5).
Iwakami, Beach and Kub are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an oxide layer as taught by Iwakami.
Doing so would realize a metal oxide semiconductor film to reduce the gate leak current and increase reliability (Iwakami: para. 0081).
Regarding claim 10, Kub in view of Beach and Iwakami teaches the method according to claim 9, wherein the oxide layer (Iwakami: fig. 14, 8) is in ohmic contact (Iwakami: ohmically connect; para. 0022) with a two-dimensional hole gas (Iwakami: 2DEG layer 211; para. 0083) formed near an interface of the p-GaN layer (Iwakami: carrier travel layer 21; para. 0022, similar to GaN of Kub) with the AlGaN layer (Iwakami: 22).
Regarding claim 11, Kub in view of Beach and Iwakami teaches the method according to claim 9, wherein forming the oxide layer (Iwakami: fig. 14, 8) comprises performing a heating process (Iwakami: heat treatment; para. 0071) to form the oxide layer (Iwakami: 8).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kub in view of Beach and Iwakami as applied to claims 9 above, and further in view of Terano et al. (US 20150179780).
Regarding claim 12, Kub in view of Beach and Iwakami teaches the method according to claim 9 including the p-GaN layer (Kub: fig. 1, GaN).
Kub in view of Beach and Iwakami fails to explicitly teach forming a nucleation layer on the substrate; and
forming a buffer layer on the nucleation layer, wherein the p-GaN layer is formed on the buffer layer.
However, Terano teaches forming a nucleation layer (Terano: fig. 5A, buffer layer 2; para. 0053) on the substrate (Terano: sapphire substrate 1; para. 0053, similar to substrate of Kub); and
forming a buffer layer (Terano: n-type collector layer 3; para. 0053) on the nucleation layer (Terano: 2), wherein the p-GaN layer (Terano: first p-type base layer 4; para. 0053, similar to GaN of Kub) is formed on the buffer layer (Terano: 3).
Terano, Iwakami, Beach and Kub are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add nucleation layer and a buffer layer as taught by Terano.
Doing so would realize buffer layer structure for easier epitaxially growing nitride semiconductor layers on the substrate (Terano: para. 0126).
Regarding claim 13, Kub in view of Beach, Iwakami and Terano teaches the method according to claim 12, wherein the nucleation layer (Terano: fig. 5A, 2) comprises GaN (Terano: undoped GaN; para. 0053) and has a Group V polar plane (Kub: Nitrogen-Polar for above Nitrogen-Polar GaN layer; para. 0004).
Regarding claim 14, Kub in view of Beach, Iwakami and Terano teaches the method according to claim 13, wherein the buffer layer (Terano: fig. 5A, 3) comprises GaN (Terano: n-type GaN; para. 0053).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kub in view of Iwakami.
Regarding claim 15, Kub teaches a semiconductor device (fig. 1, Field Effect Transistors FET; para. 0026) comprising:
a p-GaN layer (fig. 1, bottom panel, Nitrogen-Polar GaN and P-type doping; para.0034) on a substrate (substrate; para. 0026), the p-GaN layer (GaN) comprising p-type GaN (GaN and P-type doping; para.0034) and having an N polar surface (Nitrogen-Polar; para. 0004);
an AlGaN layer (AlGaN) on the p-GaN layer (GaN), the AlGaN layer (AlGaN) having an N polar surface (non-inverted and Nitrogen-Polar; para. 0004).
Kub fails to explicitly teach the AlGaN layer comprising undoped AlGaN;
an electrode on the AlGaN layer, the electrode comprising an electrode material containing Ni; and
an oxide layer between the AlGaN layer and the electrode, the oxide layer comprising an oxide of the electrode material and being in contact with both the AlGaN layer and the electrode.
However, Iwakami teaches the AlGaN layer (Iwakami: fig. 14, carrier supply layer 22; para. 0022, similar to AlGaN of Kub) comprising undoped AlGaN (Iwakami: undoped AlGaN; para. 0029);
an electrode (Iwakami: control electrode 5; para. 0022) on the AlGaN layer (Iwakami: 22), the electrode (Iwakami: 5) comprising an electrode material (Iwakami: fig. 3A, as Ni and Ni/Au/Ti stacked; para. 0046, 0078) containing Ni (Iwakami: Ni; para. 0046); and
an oxide layer (Iwakami: metal oxide semiconductor film 8; para. 0022) between the AlGaN layer (Iwakami: 22) and the electrode (Iwakami: 5), the oxide layer (Iwakami: 8) comprising an oxide of the electrode material (Iwakami: fig. 3A, NiO; para. 0038) and being in contact with both the AlGaN layer (Iwakami: 22) and the electrode (Iwakami: 5).
Iwakami and Kub are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an oxide layer as taught by Iwakami.
Doing so would realize a metal oxide semiconductor film to reduce the gate leak current and increase reliability (Iwakami: para. 0081).
Regarding claim 16, Kub in view of Iwakami teaches the semiconductor device according to claim 15, wherein the oxide layer (Iwakami: fig. 14, 8) is in ohmic contact (Iwakami: ohmically connect; para. 0022) with a two-dimensional hole gas (Iwakami: 2DEG layer 211; para. 0083) formed near an interface of the p-GaN layer (Iwakami: carrier travel layer 21; para. 0022, similar to GaN of Kub) with the AlGaN layer (Iwakami: 22).
Regarding claim 17, Kub in view of Iwakami teaches the semiconductor device according to claim 15, further comprising a buffer layer (Iwakami: fig. 14, buffer layer 11; para. 0025) on the substrate (Iwakami: substrate 10; para. 0025, similar to substrate of Kub), wherein the p-GaN layer (Iwakami: 21, similar to GaN of Kub) is on the buffer layer (Iwakami: 11).
Regarding claim 18, Kub in view of Iwakami teaches the semiconductor device according to claim 17, wherein the buffer layer (Iwakami: fig. 14, 11) comprises GaN (Iwakami: 11 made of gallium nitride; para. 0025).
Claims 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Terano et al. (US 20150179780) in view of Morita et al. (US 20080121938), Beach and Iwakami.
Regarding claim 19, Terano teaches a method (Abstract) for manufacturing a semiconductor device (transistor; Abstract), the method comprising:
forming a collector layer (fig. 5A, n-type collector layer 3; para. 0053) on a substrate (sapphire substrate 1; para. 0053), the collector layer (3) comprising GaN (n-type GaN; para. 0053);
forming a base layer (first p-type base layer 4; para. 0053) on the collector layer (3), the base layer comprising p-type GaN (p-type GaN; para. 0053);
forming an emitter layer (second p-type base layer 5 and will add emitter region 8; para. 0056) on the base layer (4),
forming an emitter electrode (fig. 5E, emitter electrode pattern 9; para. 0057) on the emitter layer (5);
forming a collector electrode (collector electrode 10; para. 0057) electrically connected to the collector layer (3).
Terano fails to explicitly teach the collector layer having an N polar surface;
the base layer having an N polar surface;
the emitter layer comprising undoped AlGaN and having an N polar surface;
oxidizing a surface of the emitter layer positioned around the emitter electrode to form a surface oxidized layer comprising AlGaON;
forming a base electrode on the surface oxidized layer, the base electrode comprising an electrode material containing Ni and being in contact with the surface oxidized layer;
forming an oxide layer in a portion of the base electrode in contact with the surface oxidized layer between the base electrode and the emitter layer, the oxide layer comprising an oxide of the electrode material and being in contact with both the emitter layer and the base electrode.
However, Morita teaches the collector layer (Morita: collector layer; para. 0026, similar to 3 of Terano) having an N polar surface (Morita: nitrogen face; para. 0026);
the base layer (Morita: base layer; para. 0026, similar to 4 of Terano) having an N polar surface (Morita: nitrogen face; para. 0026);
the emitter layer (Morita: emitter layer; para. 0026, similar to 5, 8 of Terano) having an N polar surface (Morita: nitrogen face; para. 0026);
Morita and Terano are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add collector layer, base layer and emitter layer having an N polar surface as taught by Morita.
Doing so would realize a N polar surface transistor structure that excels in crystallinity can be formed, transistor of higher gain can be realized (Morita: para. 0027).
In addition, Terano in view of Morita fails to explicitly teach the emitter layer comprising undoped AlGaN;
oxidizing a surface of the emitter layer positioned around the emitter electrode to form a surface oxidized layer comprising AlGaON;
forming a base electrode on the surface oxidized layer, the base electrode comprising an electrode material containing Ni and being in contact with the surface oxidized layer;
forming an oxide layer in a portion of the base electrode in contact with the surface oxidized layer between the base electrode and the emitter layer, the oxide layer comprising an oxide of the electrode material and being in contact with both the emitter layer and the base electrode.
However, Beach teaches oxidizing (Beach: fig. 3B, localized oxidation; para. 0063) a surface of the emitter layer (Beach: AlGaN; para. 0063, similar to 5 of Terano) positioned around the emitter electrode (Terano: 5 around 9) to form a surface oxidized layer (Beach: localized oxidized AlGaN; para. 0063) comprising AlGaON (Beach: AlGaON; para. 0063).
Beach, Morita and Terano are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a third step of oxidizing as taught by Beach.
Doing so would realize a localized oxidation to reduce the local density of 2DEG (Beach: para. 0063).
In addition, Terano in view of Morita fails to explicitly teach the emitter layer comprising undoped AlGaN;
forming a base electrode on the surface oxidized layer, the base electrode comprising an electrode material containing Ni and being in contact with the surface oxidized layer;
forming an oxide layer in a portion of the base electrode in contact with the surface oxidized layer between the base electrode and the emitter layer, the oxide layer comprising an oxide of the electrode material and being in contact with both the emitter layer and the base electrode.
However, Iwakami teaches the emitter layer (Iwakami: fig. 14, carrier supply layer 22; para. 0022, similar to 5 of Terano) comprising undoped AlGaN (Iwakami: undoped AlGaN; para. 0029);
forming a base electrode (Iwakami: fig. 9, NiO film 80, TiN film 51 and Al film 52 for control electrode 5; para. 0064) on the surface oxidized layer (Beach: localized oxidized AlGaN as top of 22 of Iwakami), the base electrode (Iwakami: 80, 51, 52) comprising an electrode material (Iwakami: material of Ni, Ti, Al; para. 0064) containing Ni (Iwakami: Ni; para. 0046) and being in contact with the surface oxidized layer (Beach: localized oxidized AlGaN as top of 22 of Iwakami);
forming an oxide layer (fig. 14, metal oxide semiconductor film 8; para. 0022) in a portion of the base electrode (Iwakami: portion of 80) in contact with the surface oxidized layer (Beach: localized oxidized AlGaN as top of 22 of Iwakami) between the base electrode (Iwakami: 5) and the emitter layer (Iwakami: 22), the oxide layer (Iwakami: 8) comprising an oxide of the electrode material (Iwakami: fig. 3A, NiO; para. 0038) and being in contact with both the emitter layer (Iwakami: 22) and the base electrode (Iwakami: 5).
Iwakami, Beach, Morita and Terano are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an oxide layer as taught by Iwakami.
Doing so would realize a metal oxide semiconductor film to reduce the gate leak current and increase reliability (Iwakami: para. 0081).
Regarding claim 20, Terano in view of Morita, Beach and Iwakami teaches the method according to claim 19, wherein the oxide layer (Iwakami: fig. 14, 8) is in ohmic contact (Iwakami: ohmically connect; para. 0022) with a two-dimensional hole gas (Iwakami: 2DEG layer 211; para. 0083) formed near an interface of the base layer (Iwakami: 5) with the emitter layer (Iwakami: 22).
Regarding claim 21, Terano in view of Morita, Beach and Iwakami teaches the method according to claim 19, wherein forming the oxide layer (Iwakami: fig. 14, 8) comprises performing a heating process (Iwakami: heat treatment; para. 0071) to form the oxide layer (Iwakami: 8).
Regarding claim 22, Terano in view of Morita, Beach and Iwakami teaches the semiconductor device (Terano: transistor; Abstract) manufactured according to the method of claim 19.
Regarding claim 23, Terano in view of Morita, Beach and Iwakami teaches the semiconductor device according to claim 22, wherein the oxide layer (Iwakami: fig. 14, 8) is in ohmic contact (Iwakami: ohmically connect; para. 0022) with a two-dimensional hole gas (Iwakami: 2DEG layer 211; para. 0083) formed near an interface of the base layer (Iwakami: 5) with the emitter layer (Iwakami: 22).
Conclusion
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818