DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/17/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the first sub-dielectric layer” in line 4, “the second sub-dielectric layer” in line 5 and “the through hole” in line 7. There is insufficient antecedent basis for this limitation in the claim. For the sake of prosecution, it is assumed claim 13 is dependent on claim 23 as language is consistent with limitations found within claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4-5, 11-12, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. Publication No. 2021/0367113 A1; hereinafter Lin) in view of Taninaka et al. (U.S. Publication No. 5,997,152; hereinafter Taninaka)
With respect to claim 1, Lin discloses display substrate, comprising: a base substrate [310]; a dielectric layer [322] located on one side of the base substrate (see ¶[0040]), and comprising a plurality of recessed portions [H1,H2,H3]; a plurality of first-type light-emitting diodes [332,352], each of the first-type light-emitting diodes being located in one of the recessed portions respectively; and a photoluminescence structure [334,544,354], the photoluminescence structure being located in at least some of the recessed portions, and located on a side, facing away from the base substrate, of the first-type light-emitting diode, and the photoluminescence structure configured to convert light of a first wave length emitted by the first-type light-emitting diode into light of a second wave length (see Figures 5; ¶[0041-0043]); wherein the display substrate further comprises a plurality of second-type light-emitting diodes [542] located on a side, facing away from the base substrate, of the dielectric layer, wherein the first-type light emitting didoes are blue light emitting diodes, the second-type light emitting diodes are green light light-emitting diodes, and a material of the photoluminescence structure is a quantum dot material excited by blue light to emit red light (see Figure 5, 11 and 12E ¶[0043]). Lin fails to disclose wherein the display substrate further comprises: a plurality of second-type light-emitting diodes located at a height from the second-type light-emitting diode to the base substrate being different from a height from the first-type light-emitting diode to the base substrate. In the same field of endeavor, Taninaka teaches a plurality of second-type light-emitting diodes [13b] located on a side, facing away from the base substrate, of the dielectric layer, and a height from the second-type light-emitting diode to the base substrate being different from a height from the first-type light-emitting diode to the base substrate (See Figure 2B) and second-type light-emitting diodes are located on a side, facing away from the dielectric layer, and are parallel to the first-type light-emitting diodes in a direction parallel to the base substrate (see Taninaka Figure 2B).
Arrangement of LEDs as taught by Taninaka results in a display array with zero gaps between LEDs, thereby creating a more consistent image (see Taninaka Column 5, line 59-Column 6, line 9). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 4, the combination of Lin and Taninaka discloses wherein the first-type light-emitting diodes and the second-type light-emitting diodes are distributed in a plurality of rows and columns; and in a same row, the first-type light-emitting diodes and the second-type light-emitting diodes are alternately distributed; and in a same column, the first-type light-emitting diodes and the second-type light-emitting diodes are alternately distributed (see Lin, Figures 12A-12H, Taninka Figure 2B).
With respect to claim 5, the combination of Lin and Taninaka discloses wherein for the first-type light-emitting diodes in the same row, first-type light-emitting diodes spaced other one first-type light-emitting diode are provided with the photoluminescence structure (see Lin Figure 3A-3B).
With respect to claim 11, Lin discloses a display apparatus, comprising a display substrate comprising: a base substrate [310]; a dielectric layer [322] located on one side of the base substrate (see ¶[0040]), and comprising a plurality of recessed portions [H1,H2,H3]; a plurality of first-type light-emitting diodes [332, 352], each of the first-type light-emitting diodes being located in one of the recessed portions respectively; and a photoluminescence structure [354], the photoluminescence structure being located in at least some of the recessed portions, and located on a side, facing away from the base substrate, of the first-type light-emitting diode, and the photoluminescence structure configured to convert light of a first wave length emitted by the first-type light-emitting diode into light of a second wave length (see Figures 3A-3B; ¶[0041-0043]); wherein the display substrate further comprises a plurality of second-type light-emitting diodes [542] located on a side, facing away from the base substrate, of the dielectric layer, wherein the first-type light emitting didoes are blue light emitting diodes, the second-type light emitting diodes are green light light-emitting diodes, and a material of the photoluminescence structure is a quantum dot material excited by blue light to emit red light (see Figure 5, 11 and 12E ¶[0043]).
Lin fails to disclose wherein the display substrate further comprises: a plurality of second-type light-emitting diodes located at a height from the second-type light-emitting diode to the base substrate being different from a height from the first-type light-emitting diode to the base substrate. In the same field of endeavor, Taninaka teaches a plurality of second-type light-emitting diodes [13b] located on a side, facing away from the base substrate, of the dielectric layer, and a height from the second-type light-emitting diode to the base substrate being different from a height from the first-type light-emitting diode to the base substrate (See Figure 2b) and second-type light-emitting diodes are located on a side, facing away from the dielectric layer, and are parallel to the first-type light-emitting diodes in a direction parallel to the base substrate (see Taninaka Figure 2B).
Arrangement of LEDs as taught by Taninaka results in a display array with zero gaps between LEDs, thereby creating a more consistent image (see Taninaka Column 5, line 59-Column 6, line 9). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, the combination of Lin and Taninaka discloses providing the base substrate [310]; forming the dielectric layer [322] with a plurality of recessed portions on one side of the base substrate; arranging the first-type light-emitting diode [332,342,352] in each recessed portion; and forming the photoluminescence structure [334,344,354] on a side, facing away from the base substrate, of the first-type light-emitting diodes in at least some of the recessed portions (see Lin Figures 3A-3B; ¶[0041-0043]).
With respect to claim 16, the combination of Lin and Taninaka discloses wherein after the forming the photoluminescence structure on the side, facing away from the base substrate, of the first-type light-emitting diodes in at least some of the recessed portions, the manufacturing method further comprises: arranging a plurality of second-type light-emitting diodes [13b] on a side, facing away from the base substrate, of the dielectric layer (See Taninaka Figure 2b).
Arrangement of LEDs as taught by Taninaka results in a display array with zero gaps between LEDs, thereby creating a more consistent image (see Taninaka Column 5, line 59-Column 6, line 9). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 6 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Taninaka as applied to claims 5 and 12 above, and further in view of Lim et al. (U.S. Publication No. 2020/0287107 A1; hereinafter Lim).
With respect to claim 6, the combination of Lin and Taninaka fails to disclose wherein first-type light-emitting diodes not provided with the photoluminescence structure are further provided with a scattering structure located in the recessed portion on a side facing away from the base substrate. In the same field of endeavor, Lim teaches implementing scattering structure within any light transparent materials, photoluminescence structure or non-wavelength converting (See ¶[0223]). Implementation of a scattering structure as taught by Lim results in improved light efficiency and higher color reproducibility (See Lim ¶[0023]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, the combination of Lin and Taninaka fails to disclose forming a scattering structure coating the first-type light-emitting diodes in the recessed portion not provided with the photoluminescence structure.
In the same field of endeavor, Lim teaches implementing scattering structure within any light transparent materials, photoluminescence structure or non-wavelength converting (See ¶[0223]). Implementation of a scattering structure as taught by Lim results in improved light efficiency and higher color reproducibility (See Lim ¶[0023]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 9, 13, 19-20 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Taninaka as applied to claims 5 and 12 above, and further in view of Chang et al. (U.S. Publication No. 2018/0158847 A1; hereinafter Chang). Due to dependencies, claim 23 will be addressed first.
With respect to claim 23, the combination of Lin and Taninaka fails to disclose wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, and the second sub-dielectric layer is located on a side, facing away from the base substrate, of the first sub-dielectric layer; and the recessed portions are through holes penetrating through the second sub-dielectric layer, and the second-type light-emitting diodes are located on a side, facing away from the first sub-dielectric layer, of the second sub-dielectric layer, and are parallel to the first-type light-emitting diodes in a direction parallel to the base substrate.
In the same field of endeavor, Chang teaches wherein the dielectric layer comprises a first sub-dielectric layer [110] and a second sub-dielectric layer [160], and the second sub-dielectric layer is located on a side, facing away from the base substrate, of the first sub-dielectric layer; and the recessed portions are through holes penetrating through the second sub-dielectric layer (see Figure 4), and the second-type light-emitting diodes are located on a side, facing away from the first sub-dielectric layer, of the second sub-dielectric layer, and are parallel to the first-type light-emitting diodes in a direction parallel to the base substrate (see Chang Figure 4). Implementation of two sub-layers within the dielectric layer of Lin and Taninaka as taught by Chang allows for the integration of driver transistors within the device and providing structural protection and isolation of the transistors below (see Chang ¶[0033]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 9, the combination of Lin, Taninaka and Chang discloses a drive structure [T1-T3] located between the base substrate and the first sub-dielectric layer, wherein the drive structure comprises a first-type transistor correspondingly and electrically connected with the first-type light-emitting diodes, and a second-type transistor correspondingly and electrically connected with the second-type light-emitting diodes (see Chang Figure 4).
With respect to claim 13, the combination of Lin and Taninaka fails to disclose wherein the forming the dielectric layer with the plurality of recessed portions on one side of the base substrate, comprises: forming the first sub-dielectric layer on one side of the base substrate; forming the second sub-dielectric layer on a side, facing away from the base substrate, of the first sub-dielectric layer; and forming the through hole penetrating through the second sub-dielectric layer on the second sub-dielectric layer to serve as the recessed portion through a patterning process. In the same field of endeavor, Chang discloses wherein the forming the dielectric layer with the plurality of recessed portions on one side of the base substrate, comprises: forming the first sub-dielectric layer [110] on one side of the base substrate; forming the second sub-dielectric layer [160] on a side, facing away from the base substrate, of the first sub-dielectric layer; and forming the through hole [O1,O2, O3] penetrating through the second sub-dielectric layer on the second sub-dielectric layer to serve as the recessed portion through a patterning process (see Chang Figure 4).
Implementation of two sub-layers within the dielectric layer of Lin and Taninaka as taught by Chang allows for the integration of driver transistors within the device and providing structural protection and isolation of the transistors below (see Chang ¶[0033]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 19, the combination of Lin and Taninaka fails to disclose wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer, and the second sub-dielectric layer is located on a side, facing away from the base substrate, of the first sub-dielectric layer; and the recessed portions are through holes penetrating through the second sub-dielectric layer, and the second-type light-emitting diodes are located on a side, facing away from the first sub-dielectric layer, of the second sub-dielectric layer, and are parallel to the first-type light-emitting diodes in a direction parallel to the base substrate. In the same field of endeavor, Chang discloses wherein the dielectric layer comprises a first sub-dielectric layer [110] and a second sub-dielectric layer [160], and the second sub-dielectric layer is located on a side, facing away from the base substrate, of the first sub-dielectric layer; and the recessed portions are through holes penetrating through the second sub-dielectric layer, and the second-type light-emitting diodes are located on a side, facing away from the first sub-dielectric layer, of the second sub-dielectric layer, and are parallel to the first-type light-emitting diodes in a direction parallel to the base substrate (see Chang Figure 4).
Implementation of two sub-layers within the dielectric layer of Lin and Taninaka as taught by Chang allows for the integration of driver transistors within the device and providing structural protection and isolation of the transistors below (see Chang ¶[0033]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 20, the combination of Lin, Taninaka and Chang disclose wherein the first-type light-emitting diodes and the second-type light-emitting diodes are distributed in a plurality of rows and columns; and in a same row, the first-type light-emitting diodes and the second-type light-emitting diodes are alternately distributed; and in a same column, the first-type light-emitting diodes and the second-type light-emitting diodes are alternately distributed (see Lin, Figures 12A-12H, Taninka Figure 2B and Chang Figure 3).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Taninaka and Chang as applied to claim 9 above, and further in view of Bai et al. (U.S. Publication No. 2017/0365646 A1; hereinafter Bai)
With respect to claim 10, the combination of Lin, Taninaka and Chang discloses wherein in the recessed portions, a first-type connecting pad [171-173] is further arranged between the first-type light-emitting diodes and the first sub-dielectric layer; the first-type connecting pad electrically connects the first-type light-emitting diodes and the first-type transistor by a via hole penetrating through the first sub-dielectric layer (See Chang Figure 4); but fails to disclose a second-type connecting pad is further arranged between the second sub-dielectric layer and the second-type light-emitting diodes; and the second-type connecting pad electrically connects the second-type light-emitting diodes and the second-type transistor by a via hole penetrating through the first sub-dielectric layer and the second sub-dielectric layer. In the same field of endeavor, Bai teaches a second-type connecting pad [300] is further arranged between the second sub-dielectric layer and the second-type light-emitting diodes; and the second-type connecting pad electrically connects the second-type light-emitting diodes and the second-type transistor by a via hole penetrating through the first sub-dielectric layer and the second sub-dielectric layer (See Figure 3 and ¶[0046]). Differences in height between transistors and light emitting diodes can be accommodated for as taught by Bai in order to properly account for variations in height and still allows transistors to remain in the same layer for driving the circuit (See ¶[0046]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Taninaka and Chang as applied to claim 13 above, and further in view of Hsieh et al. (U.S. Patent No. 9,748,449 B2; hereinafter Hsieh)
With respect to claim 14, the combination of Lin and Taninaka fails to disclose wherein the arranging the first-type light-emitting diode in each recessed portion, comprises: arranging the first-type light-emitting diode in each recessed portion through a fluid self-assembly process. In the same field of endeavor, Hsieh teaches arranging the first-type light-emitting diode in each recessed portion through a fluid self-assembly process (See Column 3, lines 32-42). Implementation of a fluidic self-assembly process is well appreciated in the art as an effective method for deposition of light emitting diodes onto a substrate and well appreciated in the art (see Hsieh Column 3, lines 32-42). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 15, the combination of Lin, Taninaka, and Hsieh discloses wherein the forming the photoluminescence structure on the side, facing away from the base substrate, of the first-type light-emitting diodes in at least some of the recessed portions, comprises: forming the photoluminescence structure covering the first-type light-emitting diode in at least some of the recessed portions through an ink-jet printing process or a spin-coating process (see Hsieh Column 11, lines 48-65).
Response to Arguments
Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive. With respect to claim 1, Applicant argues that Examiner asserts that Lin teaches light extraction colors of the first-type light-emitting diodes in the recessed portions are the same, and light extraction colors of the second-type light emitting diodes are the same. Applicant further asserts that Lin fails to disclose light-emitting elements arranged on a side, facing away from the first sub-dielectric layer, of the second sub-dielectric layer, and cannot teach the second-type light-emitting diodes located on a side, facing away from the base substrate, of the dielectric layer are green light light-emitting diodes, that is, the second-type light-emitting diodes located on a side, facing away from the base substrate, of the dielectric layer are of the same extraction color. First and second sub-dielectric layers are not claimed within claim 1.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., first sub-dielectric layer and second sub-dielectric layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, Applicant asserts that Lin does not disclose green light light emitting diodes however Examiner has cited Lin ¶[0055] in the previous Final Rejection dated 11/21/2025 where Lin explicitly states: “Specifically, the second sub-pixel 540 is still a green sub-pixel. In this embodiment, the second light-emitting element 542 emits a green light, and the second wavelength conversion layer 544 allows the green light to penetrate.” Examiner has revised the rejection to better specify that [542] specifically emits the green light and is not converted from blue through a wavelength conversion layer as in additional embodiments of Lin, however [540] green sub-pixel was previously presented within the rejection of claim 21 (now cancelled) which contained consistent language with the newly introduced amendment to claim 1 within which [542] exists.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818