DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/15/2026 has been entered.
Response to Arguments
Applicant's arguments filed 01/15/2026 have been fully considered but they are moot in view of the new grounds of rejection or indication of allowable subject matter as detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17-20,25-26 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2020/0091338 A1 to Nishiwaki, “Nishiwaki”, in view of U.S. Patent Application Publication Number 2019/0259845 A1 to Oritsuki et al., “Oritsuki”, further in view of U.S. Patent Application Publication Number 2017/0365665 A1 to Hoshi et al., “Hoshi”, and U.S. Patent Application Publication Number 2004/0195620 A1 to Chuang et al., “Chuang”.
Regarding claim 17, Nishiwaki discloses a semiconductor device (Fig. 2B,2C) comprising:
a chip (3,4,5 ¶ [0028]) having a main surface (upper);
a trench gate structure (trench “C”) that is formed at the main surface and that extends in one direction in plan view;
an intermediate trench source structure (parts of trench “D”) that is formed at the main surface at a distance from the trench gate structure (trench “C”) in the one direction and that extends in the one direction in plan view (FIG. 1);
an insulating film (12/14, ¶ [0028]) covering the trench gate structure (trench “C”) and the intermediate trench source structure (trench “D”);
a gate wiring (Fig. 2C line layer 16, ¶ [0028]) that is formed on the insulating film (12/14) and that is electrically connected to the trench gate structure (part 13) through the insulating film; and
a source wiring (Fig. 2B source line 7, ¶ [0028]) that is formed on the insulating film (12/14) at a distance from the gate wiring (16) and that is electrically connected to the intermediate trench source structure (trench “D”) through the insulating film (12/14).
Nishiwaki fails to clearly teach wherein the source wiring is formed so as to extend as a belt shape.
Oritsuki teaches (FIGs. 1,2) wherein a source wiring (13) is formed so as to extend as a belt shape (i.e. includes belt shape in region “A” around gate pad 11, ¶ [0043]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Nishiwaki by adding a belt shaped portion as taught by Oritsuki in order to suppress the dielectric breakdown of the insulating film under the gate pad (Oritsuki ¶ [0005]-[0006],[0008],[0065],[0070]).
Nishiwaki fails to clearly teach wherein the chip and device are based on silicon carbide (SiC).
Hoshi teaches the benefits of silicon carbide (SiC) for power devices including wide band gap, very stable at high temperatures, higher critical field strength (¶ [0003],[0006]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Nishiwaki from silicon carbide (SiC) as exemplified by Hoshi in order to achieve the benefits of silicon carbide (SiC) such as wide band gap, very stable at high temperatures, higher critical field strength (Hoshi ¶ [0003],[0006]) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Nishiwaki fails to clearly teach a side wiring formed on the main surface at a distance from the trench gate structure toward the side of the chip, wherein the insulating film covers the side wiring.
Chuang teaches (FIG. 4F) forming a side wiring (142 in termination trench 131, ¶ [0030],[0034]) at a distance from a trench gate structure (141) toward a side of the chip (termination, Title, Abstract), wherein the insulating film (181, ¶ [0032]) that covers the gate electrode (141) also covers the side wiring (142).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Nishiwaki in view of Oritsuki and Hoshi with a trench termination structure having a side wiring within a termination trench as taught by Chuang in order to achieve the benefits of a trench termination structure of reducing electric field crowding and leakage currents (Chuang FIG. 5,6 shows less crowded electric fields, ¶ [0009],[0010],[0012],[0038]-[0040], connecting to source prevents electric field crowding ¶ [0042]) and benefits of forming the trench termination structure simultaneously with the gate thereby reducing the number of processing steps (Chaung ¶ [0009],[0017],[0041]).
Regarding claim 18, Nishiwaki in view of Oritsuki and Hoshi and Chuang yields the SiC semiconductor device according to claim 17, and Nishiwaki further teaches wherein a plurality of the trench gate structures (trenches “C”) are arranged at the main surface with an interval between the trench gate structures in an intersection direction that intersects the one direction (Y direction), and
a plurality of the intermediate trench source structures (trenches “D”) are arranged with an interval
between the intermediate trench source structures in the intersection direction such as to face
the trench gate structures in the one direction in a one-to-one correspondence (as pictured).
Regarding claim 19, Nishiwaki in view of Oritsuki and Hoshi and Chuang yields the SiC semiconductor device according to Claim 17, and Nishiwaki further teaches a pn-junction portion (between base 5 and drift 4) formed in a region along the intermediate trench source structure (trench “D”) inside the chip (SiC when applying teachings of Hoshi); wherein the gate wiring faces the pn-junction portion in plan view (as evidenced by cross-section, since bottom of gate wiring 16 faces the junction between base 5 and drift 4).
Regarding claim 20, Nishiwaki in view of Oritsuki and Hoshi and Chuang yields the SiC semiconductor device according to claim 17, and Nishiwaki further teaches a gate-side pn-junction portion (between base 5 and drift 4) formed in a region along the trench gate structure inside the chip (SiC when applying teachings of Hoshi); wherein the gate wiring faces the gate-side pn-junction portion in plan view (as evidenced by cross-section, since bottom of gate wiring 16 faces the junction between base 5 and drift 4).
Regarding claim 25, Nishiwaki in view of Oritsuki and Hoshi and Chuang yields the SiC semiconductor device according to Claim 17, and Chuang further teaches wherein the side wiring (142) is electrically separated from the trench gate structure (141, rather instead connected via 180 to source electrode 191).
Regarding claim 26, Nishiwaki in view of Oritsuki and Hoshi and Chuang yields semiconductor device according to Claim 17, and Chuang further teaches wherein the main surface includes a first surface (FIG. 4B upper surface on left), a second surface (FIG. 4B lateral surface within trench 131) hollowed in a thickness direction of the SiC chip outside the first surface, and a connecting surface (FIG. 4B sidewall connecting upper surface to lower surface in trench 131) connecting the first surface and the second surface, the trench gate structure (e.g. 130, when applied to Nishiwaki) is formed at the first surface, the intermediate trench source structure (e.g. FIG. 4E trenches 170, when applied to Nishiwaki) is formed at the first surface, and the side wiring (142) is formed as a side wall wiring that is formed on the second surface so as to cover the connecting surface (as pictured).
Allowable Subject Matter
Claims 1-13,16,21-24 are allowed.
The following is an examiner’s statement of reasons for allowance:
Prior art e.g. U.S. Patent Application Publication Number 2017/0365665 A1 to Hoshi et al. teaches the benefits of silicon carbide (SiC) for power devices including wide band gap, very stable at high temperatures, higher critical field strength (¶ [0003],[0006]), as discussed previously.
Prior art e.g. U.S. Patent Application Publication Number 2020/0091338 A1 to Nishiwaki teaches a semiconductor device (Fig. 2B,2C) comprising:
a semiconductor chip (3,4,5 ¶ [0028]) having a main surface (upper);
a trench gate structure (trench “C”, ¶ [0031]) formed at the main surface;
a trench source structure (trench “D”) formed at the main surface away from the trench gate structure in one direction (e.g. Y direction);
a gate contact electrode (Fig. 2C portion of 16, see Examiner-annotated figure below) covering the trench gate structure on the main surface and electrically connected to the trench gate structure;
an insulating film (12/14, ¶ [0028]) covering the trench gate structure (trench “C”), the trench source structure (trench “D”), and the gate contact electrode (covering sides of portion of 16, see Examiner-annotated figure below) above the main surface;
a gate main surface electrode (13, ¶ [0028],[0044]) formed on the insulating film; and
a gate wiring (Fig. 2C line layer 16, ¶ [0028]) that is led out from the gate main surface electrode (13) onto the insulating film such as to cross the trench gate structure (trench “C”) and the trench source structure (trench “D”) in the one direction (lateral or Y direction), and that is electrically connected to the trench gate structure (trench “C”) through the insulating film, and that faces the trench source structure (trench “D”) with the insulating film between the trench source structure (trench “D”) and the gate wiring (16), as discussed previously, and further teaches wherein the trench gate structure includes a gate trench (trench “C”) formed at the main surface, a gate insulating film (12) covering an inner wall of the gate trench, and a gate electrode (13) embedded with the gate insulating film (12) between the gate trench (C) and the gate electrode (13);
the trench source structure includes a source trench (trench “D”) formed at the main surface, a source insulating film (12) covering an inner wall of the source trench, and source electrode (15) embedded in the source trench with the source insulating film (14) between the source trench and the source electrode.
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However, prior art fails to reasonably teach or suggest additionally wherein the gate contact electrode covers the gate electrode and is electrically connected to the gate electrode and the gate wiring is electrically connected to the gate electrode via the gate contact electrode through the insulating film together with all of the other limitations of claim 1 as claimed. Claims 2-5,12-13,16,21-24 are allowable insofar as they depend upon and include all of the limitations of allowable claim 1.
Additionally, prior art fails to reasonably teach or suggest additionally an intermediate trench source structure formed at the main surface at a distance from the trench gate structure in an intersection that intersects the one direction and a source main surface electrode that is formed on the insulating film away from the gate main surface electrode and from the gate wiring in plan view, and that is electrically connected to the trench source structure through the insulating film, and that faces the trench gate structure with the insulating film between the trench gate structure and the source main surface electrode, together with all of the other limitations of claim 6 as claimed. Claims 7-11 are allowable insofar as they depend upon and include all of the limitations of allowable claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Number 8,614,482 to Hsieh teaches (e.g. Fig. 2B,2C) a side wiring (233) connected to the source electrode (Top electrode);
U.S. Patent Number 8,017,494 B2 to Ma teaches (e.g. FIG. 3) a side wiring (portion of 42 in trench of termination region 12) connected to the source electrode (30).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891