CTNF 17/922,064 CTNF 100398 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 07-29 AIA The disclosure is objected to because of the following informalities: The abstract should not exceed 150 words. See MPEP 608.01(b) . Appropriate correction is required. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to a function of which the claims are directed. The following title is suggested: Product-sum semiconductor device processing weight and bias data. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 20210263992 A1, hereinafter “Qin”) in view of Matsui (US 5904731 A, hereinafter “Matsui”, provided in IDS filed 2/13/2026) . As per claim 1, Qin teaches A semiconductor device comprising: a storage circuit (Qin: Fig. 6 elements 610-3,610-4) ; an arithmetic circuit (Qin: Fig. 6 elements 630-650) ; and a product-sum operation circuit (Qin: Fig. 6 elements 630-650) , wherein the storage circuit comprises a first storage region and a second storage region (Qin: Fig. 6 elements 610-3,610-4) , wherein the first storage region is configured to retain first storage data (Qin: Fig. 6 elements 610-3; [0034]) , wherein the second storage region is configured to retain second storage data (Qin: Fig. 6 elements 610-4; [0034]) , wherein the switching circuit is configured to output the first storage data or the second storage data to the product-sum operation circuit (Qin: [0035]) , wherein the product-sum operation circuit is configured to retain first output data obtained by arithmetic processing performed on the first input data and the first storage data selected by the switching circuit (Qin: [0035]) , and wherein the product-sum operation circuit is configured to add, to the first output data, second output data obtained by arithmetic processing performed on the second input data and the second storage data selected by the switching circuit (Qin: [0035]; wherein multiply-accumulate operations with MSB set of weight vectors are added with the results of multiply-accumulate with LSB set of weight vectors) . However, while Qin discloses a multiplexor to route activation and weight banks, Qin does not explicitly disclose the structure of the multiplexer. Thus, Qin does not teach and a driver circuit, wherein the arithmetic circuit comprises a switching circuit wherein the driver circuit is configured to output first input data or second input data to the product-sum operation circuit; Matsui teaches and a driver circuit (Matsui: Fig. 5 element 81, in particular the output of element 81; col 5 lines 61-63) , wherein the arithmetic circuit comprises a switching circuit (Matsui: Fig. 5 element 82; col 5 lines 63-65) wherein the driver circuit is configured to output first input data or second input data to the product-sum operation circuit (Matsui: col 5 lines 61-63) ; Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the multiplexor of Qin with the selectors of Matsui. One would have been motivated to combine these references because both references disclose selecting each operand for multiply-accumulate computation, and combining prior art elements according to known methods to yield predictable results (structure of the multiplexing function). As per claim 4, Qin/Matsui further teaches The semiconductor device according to claim 1, wherein the first storage data is weight data (Qin: [0034]) . As per claim 5, Qin/Matsui further teaches The semiconductor device according to claim 1, wherein the product-sum operation circuit comprises a multiplier circuit, an adder circuit, and a register (Qin: Fig. 6 elements 630-650) . 07-21-aia AIA Claim s 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Qin/Matsui in view of Harada et al. (US 20180101359 A1, hereinafter “Harada”) . As per claim 6, Qin/Matsui further teaches The semiconductor device according to claim 1, However, while Qin discloses logic-level circuity, Qin does not explicitly disclose the circuitry at a transistor level. Thus, Qin does not teach wherein the storage circuit comprises a memory cell comprising a first transistor, and wherein the first transistor comprises a semiconductor layer containing a metal oxide in a channel formation region. Harada teaches wherein the storage circuit comprises a memory cell comprising a first transistor, and wherein the first transistor comprises a semiconductor layer containing a metal oxide in a channel formation region (Harada: [0205]) . Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the logic-level of circuity of Qin with the transistors of Harada. One would have been motivated to combine these references because both references disclose circuitry computing multiply-accumulate, and the OS transistors enables performing the product-sum operation with high calculation accuracy (Harada: [0212]). As per claim 7, Qin/Matsui/Harada further teaches The semiconductor device according to claim 6, wherein the metal oxide comprises In, Ga, and Zn (Harada: [0211]) . As per claim 8, Qin/Matsui further teaches The semiconductor device according to claim 1, However, while Qin discloses logic-level circuity, Qin does not explicitly disclose the circuitry at a transistor level. Thus, Qin does not teach wherein the arithmetic circuit comprises a second transistor, and wherein the second transistor comprises a semiconductor layer containing silicon in a channel formation region. Harada teaches wherein the arithmetic circuit comprises a second transistor, and wherein the second transistor comprises a semiconductor layer containing silicon in a channel formation region (Harada: [0617]) . Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the logic-level of circuity of Qin with the transistors of Harada for at least the same reasons as discussed above for claim 6 . 07-21-aia AIA Claim s 2, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Qin in view of Matsui in further view of Kim et al. (US 20190189221 A1, hereinafter “Kim”) . As per claim 2, the claim is directed to a semiconductor device that implements the same or similar features as the semiconductor device of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, while Qin discloses memory and arithmetic circuitry, Qin does not explicitly disclose the physical layout of the circuitry. Thus, Qin does not teach wherein a layer including the storage circuit is provided over a layer including the arithmetic circuit. Kim teaches wherein a layer including the storage circuit is provided over a layer including the arithmetic circuit (Kim: [0132]) . Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the logic-level of circuity of Qin with arrangement teachings of Kim. One would have been motivated to combine these references because both references disclose circuitry computing multiply-accumulate, and the structure of Kim effectively decreases an area occupying on a surface perpendicular to the stacking direction (Kim: [0133]). As per claims 10-11, the claims are directed to a semiconductor device that implements the same or similar features as the semiconductor device of claims 4-5, and are therefore rejected for at least the same reasons therein . 07-21-aia AIA Claim s 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Qin/Matsui/Kim in view of Harada . As per claims 12-13, the claims are directed to a semiconductor device that implements the same or similar features as the semiconductor device of claims 6-8, and are therefore rejected for at least the same reasons therein . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claims 3 and 9, the prior art of record does not teach or suggest a combination as claimed wherein the second storage data and the second input data are divisors of the second input data. Qin discloses a vector-vector multiplication product unit wherein the weights and activations are stored in at least two SRAM banks each, and are selected for computation ([0034]-[0035]). Qin does not suggest a correlation between the weight MSB and activation MSB. Therefore, Qin does not teach or suggest a combination as claimed including the limitations identified above. Matsui discloses a product-sum device wherein coefficients and input data are stored in at least two register each, and are selected for computation (Fig. 5; col 5 lines 50-65), wherein the coefficients may be fractions (col 4 line3 5). Matsui does not suggest the coefficients and data are related as integer divisors. Therefore, Matsui does not teach or suggest a combination as claimed including the limitations identified above. Tomita et al. (US 7139436 A, hereinafter “Tomita”, provided in IDS filed 2/13/2026) discloses multiply-accumulate circuit wherein transform coefficients are selected (Fig. 6). Tomita does not suggest a correlation of the values of the selected coefficients with the input data. Therefore, Tomita does not teach or suggest a combination as claimed including the limitations identified above. Martin (US 20190147327 A1, hereinafter “Martin”) discloses a neuron engine selecting weight and input data based on sparsity (Fig. 3; [0140]). Martin does not suggest a correlation of the weight value and the input data value. Therefore, Martin does not teach or suggest a combination as claimed including the limitations identified above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.N.L./ Phat LeExaminer, Art Unit 2182 (571) 272-0546 /ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182 Application/Control Number: 17/922,064 Page 2 Art Unit: 2182 Application/Control Number: 17/922,064 Page 3 Art Unit: 2182 Application/Control Number: 17/922,064 Page 4 Art Unit: 2182 Application/Control Number: 17/922,064 Page 5 Art Unit: 2182 Application/Control Number: 17/922,064 Page 6 Art Unit: 2182 Application/Control Number: 17/922,064 Page 7 Art Unit: 2182
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