DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Previous objection to specification is withdrawn in view of corrected title.
Drawings
Prior drawing objection related to claim 12 is withdrawn in view of applicant’s explanation provided in the reply to the office action dated 8/12/2025, which stated that the metal pad 1524 in Fig. 15 is considered part of the string 1520.
Prior drawing objection related to Figs. 1-3 are withdrawn in view of corrected drawings.
Claim Objections
Prior objection to claim 1 is withdrawn in view of amendment to claim 1.
Claim Rejections - 35 USC § 112
Prior rejection of Claim 3 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s explanation provided in the reply to the office action dated 8/12/2025.
Prior rejection of Claims 13 and 14 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claim 13.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xiao et al. (US 2020/0194452 A1, of record).
Re Claim 1, Xiao teaches a three-dimensional (3D) flash memory (Fig. 1A) comprising:
a substrate (120, Fig. 1A, para [0038]) extending in a first direction (x-axis Fig. 1A);
at least one string (channel structures, 122+152, Fig. 1A, paras [0044], [0048] and [0056]) on the substrate (120), the at least one string extending in a second direction (y-axis, Fig. 1A) crossing the first direction (x-axis); and
at least two intermediate lines (128+148, Fig. 1A, paras [0049] – [0050] and [0056] - [0057]) disposed at an intermediate region (marked “intermediate region” in annotated Fig. 1A below) in the second direction (y-axis) in which the at least one string extends (122+152 extends along y-axis), the at least two intermediate lines extending in the second direction (128+148 extends along y-axis),
wherein a string of the at least one string (122+152) is connected between one bit line (158, Fig. 1A, para [0056]) and one source line (148), and is divided by the at least two intermediate lines (128+148) into an upper string (152) and a lower string (122), and
wherein each of the at least two intermediate lines (128+148) is fixedly used as a source electrode for one of the upper string and the lower string (148 acts as the source for channel structures 152, para [0057]) or a drain electrode another one of the upper string and the lower string (128 acts as the drain for channel structures 122, para [0050]).
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Re Claim 2, Xiao teaches the 3D flash memory of claim 1, wherein the at least two intermediate lines (128+148) includes:
at least one intermediate source line used as a source electrode for the at least one string (148 acts as the source for channel structures 152, para [0057]); and
at least one intermediate drain line used as a drain electrode for the at least one string (128 acts as the drain for channel structures 122, para [0050]).
Re Claim 3, Xiao teaches the 3D flash memory of claim 2, wherein each of the at least one intermediate source line (148) and the at least one intermediate drain line (128) are provided to be separated from each other in a single layer (148 and 128 are separated within the layer “intermediate region”, see annotated Fig. 1A above).
Re Claim 4, Xiao teaches the 3D flash memory of claim 2, wherein each of the at least one intermediate source line (148) and the at least one intermediate drain line (128) are provided in mutually different layers (148 is within “layer-1” and 128 is within “layer-2”, see annotated Fig. 1A, above).
Re Claim 5, Xiao teaches the 3D flash memory of claim 2, wherein the at least one intermediate source line (148) and the at least one intermediate drain line (128) are connected to mutually different strings (122 and 152), respectively, of at least one upper string (152) and at least one lower string (122) which are obtained by dividing the at least one string (122+152) into two parts by the at least one intermediate source line (148) and the at least one intermediate drain line (128).
Claim 6 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Goda et al. (US 2021/0202751 A1, of record).
Re Claim 6, Goda teaches a three-dimensional (3D) flash memory (Fig. 1G) comprising:
a string (marked “string” in annotated Fig. 1G below) on a substrate (“base material”, para [0028], also see para [0026]) extending in a first direction (x-axis, Fig. 1G), wherein the string (“string”) includes a channel layer (118+119, Fig. 1G, para [0032] and paras [0037] – [0038]) extending in a second direction (z-axis, Fig. 1G) crossing the first direction (x-axis) and a charge storage layer (112+114+116, oxide-nitride-oxide structure, Fig. 1G, para [0028], also see para [0004]) extending in the second direction (z-axis, Fig. 1G) while surrounding the channel layer (118+119, see Fig. 1G);
at least one selection line (106B, Fig. 1G, para [0047]) connected to an upper end or a lower end of the string in a vertical direction (see Fig. 1G); and
a plurality of word lines (106, Fig. 1G, para [0047]) positioned at an upper portion or a lower portion of the at least one selection line (106B) and connected to the string in the vertical direction (see Fig. 1G),
wherein the channel layer (118+119) includes:
a first region (marked “region-1” in annotated Fig. 1G below) corresponding to the plurality of word lines (106) and a second region (marked “region-2” in annotated Fig. 1G below) corresponding to the at least one selection line (106B),
wherein the first region (“region-1”) and the second region (“region-2”) include mutually different materials (“region-1” includes 118 and “region-2” includes 119, where 118 is polysilicon, para [0032], and 119 which can be oxide semiconductor, para [0038]),
wherein each of the first region (“region-1”) and the second region (“region-2”) extends from a first sidewall of the channel layer to a second sidewall of the channel layer (see annotated Fig. 1G below), and
wherein the first region (“region-1”) including single crystalline silicon or polysilicon (“region-1” includes 118, where 118 is polysilicon, para [0032]) entirely overlaps (see annotated Fig. 1G below), in the second direction (y-axis), with the second region (“region-2”) including an oxide semiconductor material (“region-2” includes 119, where 119 which can be oxide semiconductor, para [0038]).
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Claims 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo et al. (US 2016/0049423 A1, of record).
Re Claim 12, Yoo teaches a three-dimensional (3D) flash memory comprising:
a substrate (100, Fig. 4A, para [0055]) extending in a first direction (horizontal-axis, Fig. 4A);
at least one string (200a+207, Fig. 4A, paras [0054] and [0117]) extending in a second direction (vertical direction in Fig. 4A) on the substrate (100) the second direction (vertical direction in Fig. 4A) crossing the first direction (horizontal-axis, Fig. 4A);
at least one plug line (240, Fig. 4A, para [0070]) formed on the at least one string (200a+207); and
at least one bit line (BL, Fig. 4A, para [0054]) connected to the at least one string (200a+207) through the at least one plug line (240),
wherein the at least one bit line (BL) is directly connected to the at least one string (200a+207) through only the at least one plug line (240) without passing through a component other than the at least one plug line (see Fig. 4A), and
wherein a relative position of a first plug line (240), with respect to a corresponding one of the at least one string (200a+207), for forming the first plug line on the corresponding one of the at least one string is different from that of a second plug line (2nd 240, Fig. 4A), wherein corresponding ones of the at least one string of the first plug line and the second plug line are positioned in the same column or the same row (Compare Figs. 3A and 4A, where Fig. 3A shows a top view, and Fig. 4A is the cut along I-I’ of Fig. 3A. The plug lines 240 are directly above the channels 200a in Fig. 4A and hence the position of channels also represent the positions of the corresponding plug lines. In Fig. 3A along I-I’, channels 200a, are positioned along the same column, which also represents the positions of the corresponding plug lines).
Re Claim 13, Yoo teaches the 3D flash memory of claim 12, wherein at least one string (200a+207) includes a contact metal pad (207, Fig. 4A, para [0121]) formed thereon.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. (US 2013/0234231 A1, of record), and further in view of Hu et al. (US 2020/0365612 A1, newly cited).
Re Claim 6 (Rejection-2), Fujiki teaches a three-dimensional (3D) flash memory comprising:
a string (“memory string” in Figs. 2 and 3A, paras [0007] – [0008]) on a substrate (10, Fig. 1, para [0018]) extending in a first direction (x-axis in Fig. 2), wherein the string (“memory string”) includes a channel layer (62+61+60+20a+20a1+20a1a, Fig. 3A, paras [0035], [0038], [0044] and [0056]) extending in a second direction (z-axis, Fig. 3A) crossing the first direction (x-axis) and a charge storage layer (32, Fig. 3A, para [0032]) extending in the second direction (z-axis, Fig. 3A) while surrounding the channel layer (62+61+60+20a+20a1+20a1a, see Fig. 3A);
at least one selection line (DSG, Fig. 3A, para [0037]) connected to an upper end or a lower end of the string (“memory string”) in a vertical direction (see Fig. 3A); and
a plurality of word lines (WL1-WL4, Fig. 3A, paras [0032] – [0034]) positioned at an upper portion or a lower portion of the at least one selection line (DSG) and connected to the string in the vertical direction (see Fig. 3A),
wherein the channel layer (62+61+60+20a+20a1+20a1a) includes:
a first region (20a+20a1+20a1a, Fig. 3A, para [0038]) corresponding to the plurality of word lines (WL1-WL4) and a second region (62+61+60) corresponding to the at least one selection line (DSG),
wherein the first region (20a+20a1+20a1a) and the second region (62+61+60) include mutually different materials (20a is doped silicon, para [0038], and 61/60 are doped silicon-germanium, paras [0040] – [0042]),
wherein each of the first region (20a+20a1+20a1a) and the second region (62+61+60) extends from a first sidewall of the channel layer to a second sidewall of the channel layer (see Fig. 3A), and
wherein the first region (20a+20a1+20a1a) including single crystalline silicon or polysilicon (20a is doped silicon, para [0038]) entirely overlaps (see Fig. 3A), in the second direction (z-axis), with the second region (62+61+60).
Fujiki does not disclose that the second region (60+61+62) includes an oxide semiconductor material. However, Fujiki discloses that the regions 60/61 can be doped silicon-germanium (paras [0040] – [0042]) and the channel plug 62 can be made of silicon (para [0044]).
In a related semiconductor art, Hu discloses that the channel plug can be made of a variety of semiconductor materials including polysilicon, metal silicide (such as silicon-titanium (SiTi), cobalt-silicon (CoSi) or silicon-germanium (SiGe)), oxide semiconductors (such as indium zinc oxide (ITO) or indium gallium zinc oxide (IGZO)) or combinations of two or more of the above materials (para [0054]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the channel plug of Fujiki such that the layer is made of oxide semiconductors (such as indium zinc oxide (ITO) or indium gallium zinc oxide (IGZO)) as disclosed by Hu. Hu teaches that polysilicon, metal silicide (such as silicon-titanium (SiTi), cobalt-silicon (CoSi) or silicon-germanium (SiGe)), oxide semiconductors (such as indium zinc oxide (ITO) or indium gallium zinc oxide (IGZO)) or combinations of two or more of the above materials, are art recognized alternative materials for a channel plug, and one of ordinary skill in the art would have found it obvious to substitute silicon for oxide semiconductors or a combination thereof, as disclosed by Hu (para [0054]). The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 8, Fujiki modified by Hu teaches the 3D flash memory of claim 6 (Rejection-2), but does not explicitly state that the second region (62+61+60) is used to:
block a leakage current for the at least one selection line; and
improve a characteristic of a transistor of the at least one selection line.
However, it would be obvious to one of ordinary skill in the art that the device of Fujiki will perform all the functions recited in the above claimed limitation because Fujiki discloses all the structural features of the claimed device as recited in claim 6. “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, see MPEP 2114.II.
Re Claim 9, Fujiki modified by Hu teaches the 3D flash memory of claim 6 (Rejection-2), wherein the second region (62+61+60) further includes:
an N-type junction (60 can be silicon-germanium doped with phosphorus, which is N-type impurity, para [0040]) formed on a contact interface (see Fig. 3A) with the first region (20a).
Re Claim 10, Fujiki modified by Hu teaches the 3D flash memory of claim 9, but does not explicitly disclose that the N-type junction (60) is used to:
reduce a contact resistance between the first region and the second region.
However, it would be obvious to one of ordinary skill in the art that the device of Fujiki will perform all the functions recited in the above claimed limitation because Fujiki discloses all the structural features of the claimed device as recited in claims 6 and 9. “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, see MPEP 2114.II.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiki et al. (US 2013/0234231 A1, of record) and Hu et al. (US 2020/0365612 A1, newly cited), and further in view of Kim et al. (US 2016/0005759 A1, of record) and Nam et al. (US 2015/0115348 A1, of record).
Re Claim 11, Fujiki modified by Hu teaches the 3D flash memory of claim 9, wherein the at least one selection line (DSG) is adjacent to one of the upper end or the lower end of the string (“memory string”) in the vertical direction (see Fig. 3A).
Fujiki does not disclose a plurality of selection lines.
However, in a related semiconductor art, Kim teaches a string selection transistor (SST) which can be made of multiple selection lines, for example three selection line (110S, Fig. 6, para [0047]). Use of multiple selection transistors in series on a bit-line can increase the voltage handling capacity of the circuit and improve power efficiency. Additionally, as disclosed by Nam, string selection transistor may include two or more transistors to reduce the gate length of the select gate electrodes, so that a space between the interlayer insulating layers may be completely filled (para [0051]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the memory device of Fujiki to include multiple selection lines as disclosed by Kim, because multiple selection transistors in series on a bit-line can increase the voltage handling capacity of the circuit and improve power efficiency. Additionally, as disclosed by Nam, string selection transistor may include two or more transistors to reduce the gate length of the select gate electrodes, so that a space between the interlayer insulating layers may be completely filled (para [0051], Nam).
Additionally, Fujiki also does not disclose that the second region (62+61+60) is used to:
block a leakage current for an upper selection line of two selection lines, improve a characteristic of a transistor of the at least one selection line, and inject a hole into the first region through the N- type junction in relation to a lower selection line of the two selection lines.
However, it would be obvious to one of ordinary skill in the art that the device of Fujiki modified by Kim and Nam will perform all the functions recited in the above claimed limitation because Fujiki modified by Kim and Nam discloses all the structural features of the claimed device as recited in claims 6, 9 and 11. “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, see MPEP 2114.II.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2016/0049423 A1, of record).
Re Claim 14, Yoo teaches the 3D flash memory of claim 13, wherein the contact metal pad (207) includes a metal material applied on an entire region of an upper portion of the at least one string (207 covers the entire top portion of the channel, Fig. 4A).
Yoo does not explicitly disclose that the metal pad ( 207) reduces a contact resistance between the at least one string and the at least one plug line.
However, it would be obvious to one of ordinary skill in the art that the device of Yoo will perform all the functions recited in the above claimed limitation because Yoo discloses all the structural features of the claimed device as recited in claims 13 and 14. “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, see MPEP 2114.II.
Response to Arguments
Applicant’s arguments with respect to claims 1, 6 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 1, applicant argues that the intermediate line 148 extends only along x-axis and not along y-axis. Examiner respectfully disagrees because the intermediate lines 128 and 148 are 3-dimensional objects and extends along all three directions. Additionally, the applicant also argues that the channel structures 122+152 are connected to two bit lines. Examiner agrees that the channel structures 122+152 are connected to two bit lines, 158 and 142. However, the claim language does not preclude this treatment. The claim recites that “a string of the at least one string is connected between one bit line and one source line”, which is taught by the reference as applied to the rejection of claim 1. The claim language does not exclude that the string cannot be connected to more than one bit lines.
Regarding claim 12, applicant argues that “Fig. 3A of Yoo merely discloses that the vertical channel structures 200a may be two-dimensionally arranged, when viewed in plan-view and the vertical channel structures 200a may be disposed to form a zigzag arrangement” and that “there is no disclosure whatsoever as to a relative position of a plug line with respect to its corresponding string”. Examiner respectfully disagrees with the applicant. As shown in Fig. 4A, the plug line 240 sits directly above the channel 200a and hence a position of the channel also represents the position of the corresponding plug line. When comparing Figs. 3A and 4A, Fig. 3A shows a top view, and Fig. 4A is the cut along I-I’ of Fig. 3A. In Fig. 3A along I-I’, channels 200a, are positioned along the same column of a bit line, which also represent the positions of the corresponding plug lines.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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