DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/4/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive. Applicant argues that Lee’s device 104 is not a crystal device, but a passive device such as resistors and capacitors. However, applicant’s specification describes a crystal device to be an RLC device, which is a passive device that includes resistors and capacitors (paragraph 117). Applicant argues that Lee’s element 122 is not an adapter board, but is conductive structures. Besides the fact that an adapter can be interpreted to be conductive, applicant defines the adapter board as comprising a first ground pad and an interconnect via, both of which are conductive. Applicant also argues that the interconnect via extends through a surface of the adapter board. However, since the adapter board is defined as comprising the interconnect via, this would mean that the adapter board is extending through itself. Applicant argues that Lee’s metallization layer (120) cannot be interpreted to be the claimed ground pad since it is within Lee’s substrate (106) and not on a surface. However, the metallization layer is on an inner surface of the substrate, and there is an unlabeled between element 120 and 122 which is on the upper surface of substrate 106. Applicant argues that secondary reference Shanmugam’s molding compound (160) does not have a second part that is between the adapter board and substrate. Element 250 can be interpreted to be a substrate since it is providing support for the component 220 (Figure 8A). A portion (second part) of it is located between component 140 and wiring layer 250. There is no requirement in the claim that the component cannot be in direct contact with the substrate. Shanmugam’s molding (160) is integrally formed with the rest of the molding surrounding the components (first part). While reference Baek is used to teach the third ground pad in claim 1, an embodiment of Lee teaches a third ground pad as shown in the alternative rejections for claim 3 below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Publication No. 2017/0179039) in view of Shanmugam et al. (US Publication No. 2022/0093522).
Regarding claim 1, Lee discloses an electronic device comprising (Figures 9 and 22):
a substrate (106)
a first crystal device (104) and an adapter board (122) arranged in parallel on a side surface of the substrate, wherein the adapter board comprises a first ground pad (between 120 and 122) and an interconnect via (122), wherein one end of the interconnect via (122) is connected to the first ground pad (between 120 and 122), the first ground pad (between 120 and 122) is arranged on a surface of the adapter board (122) facing the substrate (106), and the adapter board is electrically connected to the substrate (106) by the first ground pad, so that the adapter board is grounded (paragraph 47)
a first plastic packaging layer (124) comprising a first part that is arranged on a surface of the first crystal device (104)
a first shielding metal (156) that covers a surface of the first part, wherein a first end of the first shielding metal (130) extends from the surface of the first part to the surface of the adapter board (122) facing away from the substrate (106) and wherein the first shielding metal (130) is electrically connected to the first ground pad (between 120 and 122), so that the first shielding metal is grounded (paragraph 47)
a third ground pad (between 120 and 122 right side) arranged at a position where a second end (bottom) of the first shielding metal (130) comes into contact with the substrate (106), wherein the second end of the first shielding metal is connected to the third ground pad (between 120 and 122)
Lee does not disclose a housing and a second part of the first plastic packaging layer that is arranged between the adapter board and the substrate, wherein the first part and the second part are integrally formed. However, Shanmugam discloses a housing (902) and a second part of a plastic packaging layer (160) that is arranged between the adapter board (140) and the substrate (250), wherein the first part and second part are integrally formed (160) (Figure 8). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Lee to include a housing and integral plastic packaging layer surrounding the adapter layer, as taught by Shanmugam, since provide multiple components of different thicknesses for reduction in z-height for small housing applications such as earbuds (paragraphs 39-40).
Regarding claim 2, Lee discloses the adapter board (122) further comprises and wherein the first shielding metal (130) is connected to the interconnect via (122), so that the first shielding metal is connected to the first ground pad (between 120 and 122 right side) through the interconnect via (122).
Regarding claim 3, in the embodiment in Figure 9, Lee discloses the adapter board (122) comprises and interconnect via (122) and a second ground pad (128), wherein the second ground pad (128) is arranged on a surface of the adapter board facing away from the substrate, and two ends of the interconnect via (122) are respectively connected to the first ground pad (between 120 and 122 on the right) and the second ground pad (128), and wherein the first shielding metal (130) extends from the surface of the first part to the surface of the adapter board facing away from the substrate (106), and is connected to the second ground pad (128), the interconnect via (122) and the first ground pad (between 120 and 122 on the right) (Figure 9).
Regarding claim 10, Lee discloses the first crystal device (104) comprises a NOR flash memory, a metal-oxide-semiconductor (MOS) transistor, a system-on-chip (SoC) chip, a decoding circuit, a charging chip, a resistor, inductor, capacitor (RLC) device, a crystal, a Bluetooth chip, a radio frequency chip, a Wi-Fi chip, a near-field communications (NFC) chip, a sensor, or combinations thereof (paragraphs 43-44).
Claims 3-5, 7-9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Publication No. 2017/0179039) in view of Shanmugam et al. (US Publication No. 2022/0093522), and further in view of Baek et al. (US Publication No. 2018/0053732).
Regarding claim 3, Lee/Shanmugam discloses the limitations as discussed in the rejection of claim 1 above. In the embodiment of Figure 22, Lee/Shanmugam does not specifically disclose the adapter board further comprises an interconnect via and a second ground pad, wherein the second ground pad is arranged on a surface of the adapter board facing away from the substrate, and two ends of the interconnect via are respectively connected to the first ground pad and the second ground pad, and wherein the first shielding metal extends from the surface of the first part to the surface of the adapter board facing away from the substrate, and is connected to the second ground pad, so that the first shielding metal is connected to the first ground pad by the second ground pad and the interconnect via. However, Baek discloses an interconnect via (151a) and a second ground pad (115c), wherein the second ground pad (115c) is arranged on a surface of the adaptor board (111a) facing away from the substrate (150), and is connected to the second ground pad (115c), so that the first shielding metal (132) is connected to the first ground pad (115b) by the second ground pad (115c) and the interconnect via (115a). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the adapter board of Lee/Shanmugam, to include the ground pads connecting to the shielding member, as taught by Baek, since it can improve electrical characteristics while reducing noise by shielding EMI (paragraphs 62 and 83; Figure 22).
Regarding claim 4, Baek discloses a second shielding metal, comprising a first shielding segment (132) and a second shielding segment (112c), wherein the first shielding segment is arranged on a side surface of the adapter board (111a) facing the first crystal device (121), and an end of the first shielding segment away from the substrate is connected to the first shielding metal (132), and wherein the second shielding segment is arranged on the surface of the adapter board (111a) facing the substrate, one end of the second shielding segment (112c) is connected (113a) to the first shielding segment, and an another end of the second shielding segment (112c) is connected to the first ground pad (115b). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Lee et al. in view of Shanmugam et al.
Regarding claim 5, Baek discloses the second shielding metal (112c) further comprises a third shielding segment (113a), and wherein the third shielding segment is arranged on the surface of the adapter board (111a) facing away from the substrate (150), one end of the third shielding segment (113a) is connected to the first shielding segment (132), another end of the third shielding segment extends toward the second ground pad (115c) by a certain distance, and the third shielding segment (113a) is connected to the first shielding metal (132). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Lee et al. in view of Shanmugam et al.
Regarding claim 7, Lee discloses the adapter board (122) is distributed on an edge of the substrate (106) (Figures 20-21; paragraph 51).
Regarding claim 8, Baek discloses a second crystal device (240) arranged on another surface of the substrate (230); a second plastic packaging layer (250) arranged on a surface of the second crystal device; a third shielding metal (261) covering a surface of the second plastic packaging layer (250) and the side surface of the substrate (230); and a ground metal layer (220) located inside the substrate, extending from inside of the substrate to the side surface of the substrate, and connected to the third shielding metal (261) (Figure 13). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Lee et al. in view of Shanmugam et al.
Regarding claim 9, Baek discloses the third shielding metal (261) further covers a side surface of the second part facing away from the first crystal device, and further covers a side surface of the adapter board facing away from the first crystal device (Figure 13).
Regarding claim 11, Lee discloses the first crystal device (104) comprises a NOR flash memory, a metal-oxide-semiconductor (MOS) transistor, a system-on-chip (SoC) chip, a decoding circuit, a charging chip, a resistor, inductor, capacitor (RLC) device, a crystal, a Bluetooth chip, a radio frequency chip, a Wi-Fi chip, a near-field communications (NFC) chip, a sensor, or combinations thereof (paragraphs 43-44).
Regarding claim 12, Lee discloses the first shielding metal, the second shielding metal, and the third shielding metal are formed by spraying or sputtering (paragraph 57).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571)270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 1/27/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897