Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/12/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements mentioned above are being considered by the examiner, except for the references that have been lined through in the IDS submitted on 12/12/2022 because the applicant has not provided a translated copy nor concise explanation of relevance as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language of the cited references, (DE 10161224 A1), (DE 102019120689 A1), (DE 112018005590 A1), see 37 C.F.R. 1.98(3)(i), 37 C.F.R. 1.98(3)(ii), MPEP 609.04(a)(II), and MPEP 609.04(a)(III), furthermore because the applicant has not provided legible copies of Foreign patent documents (WO 2006100209 A2), and (WO 2019097350 A1), see 37 C.F.R. 1.98(2)(i), MPEP 609.04(a)(II)(A).
Specification
The abstract of the disclosure is objected to because the abstract is not concise, exceeding 150 words in length, furthermore the abstract of the disclosure is objected to because the abstract refers to purported merits and speculative application of the invention. Furthermore, the Examiner notes that the abstract appears to be a translation into English from a foreign document, and are replete with grammatical and idiomatic errors, as an example, the abstract recites: “The capacitance is initially precharged”, and “By this means the capacitance is discharged”. Capacitance1 is the measure of a component’s ability to store an electrical charge, it’s an electrical property, not a component which can be charged/discharged. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
Claim Objections
Claims 2, 8, and 11 are objected to because of the following informalities:
Regarding claim 2, claim 2 appears to contain a grammatical error, having a space before a comma and no space after the comma, and should be changed to: “represents an artificial neuron, and”.
Regarding claim 8, claim 8 appears to contain a grammatical error and should be changed to: “[[an]] a FET array”.
Regarding claim 11, claim 11 appears to contain a grammatical error and should be changed to:
“[[an]] a FET array”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims, claim 1-18, are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors. Some examples are the various uses of the term “capacitance” in a manner that suggest that it is a component, “serving as a current source, a charging device, and at least one capacitance”, “the capacitance is precharged”, “the capacitance is discharged”, “determined from a residual charge or voltage of the capacitance”, “charge difference between the latter and a further capacitance” of claim 1, and which can be found similarly in claim 2, 9-12, 14-16, and 18.
The dependent claims, 3, and 9 recite the limitation of: “Method according to Claim 2”. It is unclear if each of these, claim 3 and claim 9, are the “Method according to Claim 2” or if it is another method entirely, as in, a “Method according to Claim 2”.
Claims 4-8 inherit the same deficiency as claim 3 based on dependence.
The dependent claims 4, 5, and 8 recite the limitation of: “Method according to Claim 3”. It is unclear if each of these, claim 4, 5, and 8, are the “Method according to Claim 3” or if it is another method entirely, as in, a “Method according to Claim 3”.
Claim 6 inherits the same deficiency as claim 4 based on dependence.
Claim 7 inherits the same deficiency as claim 5 based on dependence.
The dependent claim 6 recites the limitation of: “Method according to Claim 4”. It is unclear if claim 6 is the “Method according to Claim 4” or if it is another method entirely, as in, a “Method according to Claim 4”.
The dependent claim 7 recites the limitation of: “Method according to Claim 5”. It is unclear if claim 7 is the “Method according to Claim 5” or if it is another method entirely, as in, a “Method according to Claim 5”.
The dependent claims 12-13 recite the limitation of: “Neural network according to Claim 10”. It is unclear if each of these, claim 12-13, are the “Neural network according to Claim 10” or if it is another apparatus entirely, as in, a “Neural network according to Claim 10”.
The dependent claim 15 recites the limitation of: “Method according to Claim 1”. It is unclear if claim 15 is the “Method according to Claim 1” or if it is another method entirely, as in, a “Method according to Claim 1”.
The dependent claims 16-18 recite the limitation of: “Neural network according to Claim 11”. It is unclear if each of these, claim 16-18, are the “Neural network according to Claim 11” or if it is another apparatus entirely, as in, a “Neural network according to Claim 11”.
The Examiner suggests, where applicable, inserting a “The” at the beginning of the dependent claims, “The method according to Claim 1”as an example. Furthermore, the Examiner suggests, inserting an “A” at the beginning of the independent claims, “A method for the analogue multiplication” as an example.
Claims 1-3, 9-11, 14-15, and 18 use the term “which” throughout their limitations, “Method for the analogue multiplication with a circuit assembly, which has a series circuit”, “series circuit comprising the first FET and the second FET, or FET array, in which - the capacitance is precharged” as of claim 1, “Method for the analogue calculation of a scalar product, which is formed by the multiplication”, “plurality of value pairs, with a circuit assembly, which has a plurality of parallel-connected series circuits”, as of claim 2, “Neural network with one or more layers of artificial neurons, in which the neurons of at least one of the layers”, as of claim 10, “Neural network with one or more layers of artificial neurons, wherein the neurons of at least one of the layers in each case have a circuit array, which comprises” as of claim 11, as a few examples from the claims. It is unclear what term “which” modifies throughout the claims. The Examiner suggests, where applicable, instead using a wherein clause.
Claim 15 inherits the same deficiency as claim 1 based on dependence.
Claims 3-9 inherit the same deficiency as claim 2 based on dependence.
Claims 12-14 inherit the same deficiency as claim 10 based on dependence.
Claims 16-18 inherit the same deficiency as claim 11 based on dependence.
Regarding claim 1, claim 1 recites the limitation of: “Method for the analogue multiplication”. There is insufficient antecedent basis for this limitation in the claim, “the analogue multiplication”.
Furthermore, claim 1 recites the limitation of: “which has a series circuit comprising a first FET and a second FET, or FET array comprising”. It is unclear if it is meant to be understood as a series circuity comprising a first FET and a second FET or a series circuitry comprising a FET array (by itself) or if it meant to be understood as a FET array instead of a series circuit, or if it is meant to be understood as a series circuit comprising a first FET and a second FET or a first FET and a FET array.
Furthermore, claim 1 recites the limitations of: “and can be discharged by way of the series circuit comprising the first FET and the second FET, or FET array”. It is unclear if it is meant to be understood as the first FET and the second FET or the FET array (in place of the first and second FET), or if it is meant to be understood as the first FET and the FET array (where the FET array is in place of the second FET only).
Furthermore, claim 1 recites the limitations of: “a circuit assembly, which has a series circuit comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs, serving as a current source, a charging device, and at least one capacitance”. It is unclear if the limitation is meant to be understood as the series circuit serves “as a current source, a charging device, and at least one capacitance”, or if it is meant to be understood as the first FET, or the second FET or the FET array, or if it is meant to be understood as the first FET and the second FET, or the first FET and the FET array, or the FET array itself, or if there is some other component of the circuit assembly which serves “as a current source, a charging device, and at least one capacitance”. Furthermore, it is unclear if the component or combination of components, first FET, second FET, FET array, serves as all three, “as a current source, a charging device, and at least one capacitance”, or if different components serve as the different purposes.
Furthermore, claim 1 recites the limitations of: “and a result of the multiplication can be determined from a residual charge or voltage of the capacitance, or from a voltage difference, or charge difference between the latter and a further capacitance”. It is unclear what is meant by “charge difference between the latter and a further capacitance”. The term “latter” typically means the last of a list of things, in this instance, the last of the list in the limitations that comes before the term “latter” is “voltage difference”. However, if replacing the term “latter” with “voltage difference” as the meaning of the term “latter” implies the limitation would become “charge difference between the voltage difference and a further capacitance”. The term “further capacitance” implies that the charge difference is between a capacitance and then by a “further capacitance”, and a voltage difference is not a capacitance.
Furthermore, claim 1 recites the limitation of: “the second value, encoded as a voltage amplitude, is applied to the gate of the second FET, or, encoded as binary voltage amplitudes, is applied to the gates of the parallel-connected second FETs, so that the capacitance is discharged for a period of time which is specified by the pulse width of the voltage pulse applied to the gate of the first FET, with a discharge current, which is specified by the voltage amplitude(s) applied to the gate of the second FET, or to the gates of the parallel-connected second FETs”. These claim limitations are unclear. The limitation of “so that the capacitance is discharged for a period of time” implies that it is dependent on the second value is encoded (or binary encoded) as a voltage amplitude and applied to the gate of the second FET (or applied to the gates of the parallel-connected second FETs). Furthermore, the limitation of “which is specified by the pulse width of the voltage pulse applied to the gate of the first FET, with a discharge current, which is specified by the voltage amplitude(s) applied to the gate of the second FET, or to the gates of the parallel-connected second FETs” implies that the capacitance being discharged over a period of time is dependent upon the pulse width of the voltage pulse applied to the gate of the first FET, and a discharge current that is dependent upon the voltage amplitude. From this it is unclear if these limitations are meant to be understood as the voltage amplitude applied to the gate of the second FET (or to the gates of the parallel-connected second FETs) is dependent upon the pulse width applied to the gate of the first FET and dependent upon itself (the voltage amplitude) or if it is meant to be understood as a capacitor (or one or more of the FETs) holding a charge, is discharged, with the discharge current being dependent upon the specified voltage amplitude applied to the gate of the second FET (or to the gates of the parallel-connected second FETs), and with the discharge time being dependent upon the pulse width of the voltage pulse applied to the gate of the first FET.
Claim 15 inherits the same deficiencies as claim 1 based on dependence.
Regarding claim 15, claim 15 recites the limitations of: “the circuit assembly for processing signed first values in each of the series circuits”. There is insufficient antecedent basis for this limitation in the claim, “signed first values”, and “each of the series circuits”.
Furthermore, claim 15 recites the limitation of: “the circuit assembly for processing signed first values in each of the series circuits comprises two parallel circuit branches, which are serially connected to the second FET, or FET array, and in each case comprise a first FET”. It is unclear if the “a first FET” is different or the same as the FET in the claim it depends upon, claim 1.
Furthermore, claim 15 recites the limitation of: “in each case”. It is unclear what “in each case” is referring to. It is unclear if “in each case” is referring to each of the series circuits, or each of the branches.
Furthermore, claim 15 recites the limitations of: “wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance, which can be precharged by way of the charging device, and can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as both “the capacitance” and “second capacitance” is precharged by way of the charging device, and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array) or if it is meant to be understood as only the “second capacitance” is precharged by way of the charging device and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array).
Furthermore, claim 15 recites the limitation of: “and can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as the discharge is by way of the first FET and the second FET or by the FET array (by itself) or if it is meant to be understood as the discharge is by way of the first FET and the second FET or by way of the first FET and the FET array.
Furthermore, claim 15 recites the limitation of: “in each of the series circuits comprises two parallel circuit branches, which are serially connected to the second FET, or FET array, and in each case comprise a first FET”. This limitation of claim 15, as interpreted by the Examiner, states that there are a plurality of series circuits, and “in each case”, as interpreted by the Examiner, means that each series circuit has two branches and each branch contains a first FET. From this, it makes it unclear which series circuit, of the “series circuits”, is meant by “can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array” since the claim, as interpreted by the Examiner, states, that each of the series circuits would have this.
Furthermore, in regards to claim 15, claim 1, (which claim 15 is dependent upon) recites the limitations of: “a circuit assembly, which has a series circuit comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs, serving as a current source, a charging device, and at least one capacitance”. Claim 15 recites the limitation of: “the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if the series circuit of claim 15 is the same as the series circuit of this limitation in claim 1, or if the series circuit of claim 15 is another series circuit, with claim 15’s limitation of “each of the series circuits”.
Furthermore, claim 15 recites the limitation of: “wherein the respective first value”. It is unclear if it is meant to be understood as the same or different “first value” recited in claim 1, claim 1 reciting a singular “first value”, “a first value”, “the first value”.
Furthermore, claim 15 recites the limitations of: “wherein the respective first value, encoded as the pulse width of a voltage pulse, is applied, depending on its sign, either to the gate of the first FET of the first circuit branch, or to the gate of the first FET of the second circuit branch”. Claim 1 recites: “a first FET”, “comprising the first FET”, “gate of the first FET”, “voltage pulse applied to the gate of the first FET”. Claim 1’s recitation of “a first FET” indicates a singular first FET, yet claim 15 recites multiple first FETs. It is unclear how the limitations of multiple first FETs of claim 15 coincide with the limitation of a singular first FET of claim 1.
Furthermore, claim 15 recites the limitations of: “and a result of the multiplication or calculation of the scalar product can be determined from a voltage difference or charge difference between the two capacitors.” Claim 1 recites the limitations of: “execution of a multiplication of a first value by a second value”, “the first value, encoded as a pulse width of a voltage pulse”, “the second value, encoded as a voltage amplitude”, and “result of the multiplication can be determined from a residual charge or voltage of the capacitance, or from a voltage difference or charge difference between the latter and a further capacitance.” It is unclear what determines the multiplication result. Claim 1 recites that it is a result of a voltage pulse (from a first value) and a voltage amplitude (from a second value) and that it is determined by “a residual charge or voltage of the capacitance, or from a voltage difference or charge difference between the latter and a further capacitance.” It is unclear how the limitation of claim 15 can coincide with the limitations of claim 1, for example the multiplication may be determined by a residual charge in claim 1, whereas claim 15 states that the multiplication can be determined by voltage difference or charge difference between two capacitors.
Furthermore, claim 15 recites the limitation of: “between the two capacitors”. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 2 recites the limitation of: “which has a plurality of parallel-connected series circuits comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”. It is unclear if the limitation means that each series circuit comprises a first FET and a second FET or FET array, or if it is meant to be understood as between all of the series circuits, they only comprise a (singular) first FET, and a (singular) second FET, or FET array.
Furthermore claim 2 recites the limitation of: “which has a plurality of parallel-connected series circuits comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”. It is unclear if it is meant to be understood as the series circuits comprise a first FET and a second FET or a FET array, or if it is meant to be understood as the series circuits comprise a first FET and a second FET or a first FET and a FET array.
Furthermore, claim 2 recites the limitations of: “serving as a current source, a charging device, and at least one capacitance”. It is unclear if the limitation is meant to be understood as the series circuits serve “as a current source, a charging device, and at least one capacitance”, or if it is meant to be understood as the first FET, or the second FET or the FET array, or if it is meant to be understood as the first FET and the second FET, or the first FET and the FET array, or the FET array itself, or if there is some other component of the circuit assembly which serves “as a current source, a charging device, and at least one capacitance”. Furthermore, it is unclear if the component or combination of components, first FET, second FET, FET array, serves as all three, “as a current source, a charging device, and at least one capacitance”, or if different components serve as the different purposes.
Furthermore, claim 2 recites the limitations of: “a circuit assembly, which has a plurality of parallel-connected series circuits comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs, serving as a current source, a charging device, and at least one capacitance”. The Examiner interprets, “a plurality of parallel-connected series circuits comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs” as each of the series circuits comprise “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”, given that context, it is unclear if all of the plurality of series circuits, or all of “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs” serve as a singular current source, or if each series circuit (or each of the series circuits comprising “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”) serve as a current source each (multiple current sources). Similarly, it is unclear if all of the plurality of series circuits, or all of “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs” serve as a charging device, or if each series circuit (or each of the series circuits comprising “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”) serve as a charging device each (multiple charging devices). Similarly, it is unclear if all of the plurality of series circuits, or all of “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs” serve as “at least one capacitance”, or if each series circuit (or each of the series circuits comprising “a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”) serve as “at least one capacitance” each (multiple charging devices).
Furthermore, claim 2 recites the limitation of: “each of the value pairs is associated with one of the series circuits”. It is unclear if it is meant to be understood as each of the value pairs (as in all of them) is associated with only one of the series circuits, or if each of the value pairs is associated with one of the series circuits respectively (as in each value pair is associated with its own series circuit).
Furthermore, claim 2 recites the limitation of: “in each case”. It is unclear what “in each case” is referring to. It is unclear what “in each case” is referring to.
Furthermore, claim 2 recites the limitations of: “a result of the calculation of the scalar product can be determined from a residual charge or voltage of the capacitance, or from a voltage or charge difference between the latter and a further capacitance.” It is unclear what is meant by “charge difference between the latter and a further capacitance”. The term “latter” typically means the last of a list of things, in this instance, the last of the list in the limitations that comes before the term “latter” is “voltage difference”. However, if replacing the term “latter” with “voltage difference” as the meaning of the term “latter” implies the limitation would become “charge difference between the voltage difference and a further capacitance”. The term “further capacitance” implies that the charge difference is between a capacitance and then by a “further capacitance”, and a voltage difference is not a capacitance.
Furthermore, claim 2 recites the limitations of: “a plurality of parallel-connected series circuits comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs, serving as a current source, a charging device, and at least one capacitance”. The Examiner interprets this limitation to mean that there are a plurality of series circuits “comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”, and that each of these series circuits (either by individual components or by some combination of components) serve as “a current source, a charging device, and at least one capacitance” each. Given that context, it is unclear which capacitance is referred to in the later claim 2 limitations, “the capacitance is at least partially discharged”, and “voltage of the capacitance”.
Claims 3-9 inherit the same deficiency as claim 2 based on dependence.
Regarding claim 6, claim 6 recites the limitations of: “wherein each digit of the digit sequence controls the pulse width at the gate of the first FET” It is unclear if the “first FET” in claim 2, which claim 6 is dependent upon, is a singular first FET, or if there are a plurality of first FETs. As interpreted by the Examiner, the limitations in claim 2 describe a plurality of series circuits, each with a “first FET”. Claim 6 recites “wherein each digit of the digit sequence controls the pulse width at the gate of the first FET”. It is unclear which first FET claim 6 is referring to, given that claim 2, as interpreted by the Examiner, describes a plurality of first FETs.
Regarding claim 8, claim 8 recites the limitation of: “matrix-like”. The phrase "like" renders the claim(s) indefinite because the claim(s) include(s) elements not actually disclosed (those encompassed by "like"), thereby rendering the scope of the claim(s) unascertainable. See MPEP § 2173.05(d).
Furthermore, claim 8 recites the limitation of: “comprising a first FET and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”. It is unclear if it is meant to be understood as a first FET and a second FET or a FET array (the FET array in place of the first FET and the second FET), or if it is meant to be understood as the first FET and a second FET or a first FET and the FET array.
Furthermore, claim 8 recites the limitations of: “characterised in that the parallel-connected series circuits, comprising a first FET and a second FET, or an FET array comprising a plurality of parallel-connected second FETs, serving as a current source, are used in a matrix-like manner at crossing points between horizontal connections for an input vector, and vertical connections for an output vector”. It is unclear if meant to be understood as the series circuits themselves are organized in a matrix, or if the first FET and second FET (or FET array) is meant to be organized in a matrix, or if just the FET array comprising a plurality of parallel-connected second FETs is meant to be organized as a matrix.
Furthermore, claim 8 recites the limitations of: “are used in a matrix-like manner at crossing points between horizontal connections for an input vector, and vertical connections for an output vector”. Claim 3, which claim 8 is dependent upon, recites: “each value pair is respectively formed by a weight factor and an input value of the artificial neuron”. It is unclear if the input value from claim 3 (which claim 8 is dependent upon) belongs to the input vector of claim 8, or if the input vector is of an entirely different input than the input claimed in claim 3.
Furthermore, claim 8 recites the limitation of: “the parallel-connected series circuits, comprising a first FET and a second FET, or an FET array”. It is unclear if the limitation means that each series circuit comprises a first FET and a second FET or FET array, or if it is meant to be understood as between all of the series circuits, they only comprise a (singular) first FET, and a (singular) second FET or a singular FET array.
Regarding claim 9, claim 9 recites the limitations of: “the circuit assembly for processing signed first values in each of the series circuits comprises two parallel circuit branches, which are serially connected to the second FET, or FET array, and in each case comprise a first FET”. It is unclear as to what “in each case” is referring to. Unclear if it is meant to be understood as each of the series circuits, or each branch.
Furthermore, claim 9 recites the limitations of: “series circuits comprises two parallel circuit branches, which are serially connected to the second FET, or FET array, and in each case comprise a first FET”. Claim 2 recites: “a first FET”, “comprising the first FET”, “gate of the first FET”, “voltage pulse applied to the gate of the first FET”. Claim 2’s recitation of “a first FET” indicates a singular first FET, yet claim 9 recites multiple first FETs. It is unclear how the limitations of multiple first FETs of claim 9 coincide with the limitation of a singular first FET of claim 2.
Furthermore, claim 9 recites the limitation of: “between the two capacitors”. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, claim 9 recites the limitations of: “wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance, which can be precharged by way of the charging device, and can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as both “the capacitance” and “second capacitance” is precharged by way of the charging device, and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array) or if it is meant to be understood as only the “second capacitance” is precharged by way of the charging device and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array).
Furthermore, claim 2, which claim 9 is dependent upon, recites the limitations of: “a plurality of parallel-connected series circuits comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs, serving as a current source, a charging device, and at least one capacitance”. The Examiner interprets this limitation to mean that there are a plurality of series circuits “comprising a first FET and a second FET, or FET array comprising a plurality of parallel-connected second FETs”, and that each of these series circuits (either by individual components or by some combination of components) serve as “a current source, a charging device, and at least one capacitance” each. Given that context, it is unclear which capacitance is referred to in claim 9 limitations, “a first of the two circuit branches is connected to the capacitance”.
Furthermore, claim 9 recites the limitations of: “and can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as the discharge is by way of the first FET and the second FET or by the FET array (by itself) or if it is meant to be understood as the discharge is by way of the first FET and the second FET or by way of the first FET and the FET array. Furthermore, “can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array”. Claim 9 also recites the limitation of: “in each of the series circuits comprises two parallel circuit branches, which are serially connected to the second FET, or FET array, and in each case comprise a first FET, wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance”. Claim 9 states that each of the series circuits comprises two branches, and, as interpreted by the Examiner, “and in each case comprise a first FET” refers to each branch. From this, it makes it unclear which series circuit is meant by “can be discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET, or FET array” since the claim seemingly states, as interpreted by the Examiner, that each of the series circuits would have this.
Furthermore, claim 9 recites the limitations of: “and a result of the multiplication or calculation of the scalar product can be determined from a voltage difference or charge difference between the two capacitors.” Claim 2, which claim 9 is dependent upon, recites the limitations of: “multiplication of a first value by a second value of a respective value pair”, “the first value, encoded as a pulse width of a voltage pulse”, “the second value, encoded as a voltage amplitude”, and “result of the calculation of the scalar product can be determined from a residual charge or voltage of the capacitance. or from a voltage or charge difference between the latter and a further capacitance.” It is unclear what determines the scalar product result. Claim 2 recites that it is a result of a voltage pulse (from a first value) and a voltage amplitude (from a second value) and that it is determined by “a residual charge or voltage of the capacitance. or from a voltage or charge difference between the latter and a further capacitance.” It is unclear how the limitation of claim 9 can coincide with the limitations of claim 2, for example the scalar product may be determined by a residual charge in claim 2, whereas claim 9 states that the multiplication can be determined by voltage difference or charge difference between two capacitors.
Regarding claim 10, claim 10 recites the limitations of: “a plurality of parallel-connected series circuits comprising a first FET and a second FET, serving as a current source , - a charging device, and - a capacitance”. It is unclear as to what is serving as the current source, charging device and capacitance. It is unclear if it is meant to be understood as the plurality of parallel-connected series circuits, the first FET, or the second FET, or the first FET in combination with the second FET. Furthermore, it is unclear if the component or combination of components, first FET, second FET, or the series circuits itself serves as all three, “as a current source , - a charging device, and - a capacitance”, or if different components serve as the different purposes.
Furthermore, claim 10 recites the limitations of: “can be discharged by way of the series circuits comprising the first FET and the second FET”, and “a plurality of parallel-connected series circuits comprising a first FET and a second FET”. With the added context of there are a plurality of parallel-connected series circuits comprising a first FET and a second FET, it is unclear if “can be discharged by way of the series circuits comprising the first FET and the second FET” is meant to be understood as the “capacitance” can be discharged by any one of the series circuits, or if it is meant to be understood as it can be discharged by all of the series circuits “comprising the first FET and the second FET”.
Furthermore, claim 10 recites the limitations of: “a plurality of parallel-connected series circuits comprising a first FET and a second FET, serving as a current source, - a charging device, and - a capacitance”. The Examiner interprets, “a plurality of parallel-connected series circuits comprising a first FET and a second FET” as each of the series circuits comprise “a first FET and a second FET”, given that context, it is unclear if all of the plurality of series circuits, or all of “a first FET and a second FET” serve as a singular current source, or if each series circuit (or each of the series circuits comprising “a first FET and a second FET”) serve as a current source each (multiple current sources). Similarly, it is unclear if all of the plurality of series circuits, or all of “a first FET and a second FET” serve as a charging device, or if each series circuit (or each of the series circuits comprising “a first FET and a second FET”) serve as a charging device each (multiple charging devices). Similarly, it is unclear if all of the plurality of series circuits, or all of “a first FET and a second FET” serve as “a capacitance”, or if each series circuit (or each of the series circuits comprising “a first FET and a second FET”) serve as “a capacitance” each (multiple charging devices).
Furthermore, claim 10 recites the limitation of: “a circuit assembly comprising: - a plurality of parallel-connected series circuits comprising a first FET and a second FET”. It is unclear if the limitation means that each series circuit comprises a first FET and a second FET, or if it is meant to be understood as between all of the series circuits, they only comprise a (singular) first FET, and a (singular) second FET.
Claims 12-14 inherit the same deficiency as claim 10 based on dependence.
Regarding claim 14, claim 14 recites the limitations of: “the circuit assembly for the processing of signed components”. There is insufficient antecedent basis for this limitation in the claim, “signed components”.
Furthermore, claim 14 recites the limitation of: “in each case”. It is unclear if “in each case” is referring to each of the series circuits, or each of the branches.
Furthermore, claim 14 recites the limitations of: “wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance, which can be precharged by way of the charging means, and can be discharged by way of the series connection of the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as both “the capacitance” and “second capacitance” is precharged by way of the charging device, and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array) or if it is meant to be understood as only the “second capacitance” is precharged by way of the charging device and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array).
Furthermore, claim 14 recites the limitation of: “and can be discharged by way of the series connection of the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as the discharge is by way of the first FET and the second FET or by the FET array (by itself) or if it is meant to be understood as the discharge is by way of the first FET and the second FET or by way of the first FET and the FET array.
Furthermore, claim 14 recites the limitations of: “each of the series circuits has two parallel circuit branches, which are connected to the second FET, or FET array, and in each case have a first FET, wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance”. Claim 10, which claim 14 is dependent upon, recites: “series circuits comprising a first FET”, “comprising the first FET”, “gate of the first FET”. Claim 10’s recitation of “a first FET” indicates a singular first FET, yet claim 14 recites multiple first FETs, as interpreted by the Examiner, through each branch, “two parallel circuit branches, which are connected to the second FET, or FET array, and in each case have a first FET”. It is unclear how the limitations of multiple first FETs of claim 14 coincide with the limitation of a singular first FET of claim 10.
Furthermore, claim 10, which claim 14 is dependent upon, recites the limitations of: “a plurality of parallel-connected series circuits comprising a first FET and a second FET, serving as a current source, - a charging device, and - a capacitance”. The Examiner interprets this limitation to mean that there are a plurality of series circuits “comprising a first FET and a second FET”, and that each of these series circuits (either by individual components or by some combination of components) serve as “as a current source, - a charging device, and - a capacitance” each. Given that context, it is unclear which capacitance is referred to in claim 14 limitations, “a first of the two circuit branches is connected to the capacitance”.
Furthermore, claim 14 recites the limitation of: “by the control device”. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 11, claim 11 recites the limitations of: “wherein the neurons of at least one of the layers in each case have a circuit array”. It is unclear what is meant by “in each case”. It is unclear if it is meant to be understood as each layer, or each neuron.
Furthermore, claim 11 recites the limitations of: “have a circuit array, which comprises: - a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”. It is unclear if the limitation means that each series circuit comprises a first FET and a second FET or FET array, or if it is meant to be understood as the series circuits comprises a (singular) first FET, and a (singular) second FET, or FET array.
Furthermore, claim 11 recites the limitation of: “have a circuit array, which comprises: - a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”. It is unclear if it is meant to be understood as the series circuits comprise a first FET and a second FET, or a first FET and a FET array (in place of the second FET), Or if it is meant to be understood as the series circuits comprise a FET array (in place of a first FET and a second FET).
Furthermore, claim 11 recites the limitation of: “a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs, serving as a current source, - a charging device, and - a capacitance”. It is unclear if the limitation is meant to be understood as the series circuit serves “as a current source, - a charging device, and - a capacitance”, or if it is meant to be understood as the first FET, or the second FET or the FET array, or if it is meant to be understood as the first FET and the second FET, or the first FET and the FET array, or the FET array itself, or if there is some other component of the circuit assembly which serves “as a current source, - a charging device, and - a capacitance”. Furthermore, it is unclear if the component or combination of components, first FET, second FET, FET array, serves as all three, “as a current source, - a charging device, and - a capacitance”, or if different components serve as the different purposes.
Furthermore, claim 11 recites the limitations of: “a circuit array, which comprises: - a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs, serving as a current source, - a charging device, and - a capacitance”. The Examiner interprets, “a circuit array, which comprises: - a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs” as each of the series circuits comprise “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”, given that context, it is unclear if all of the plurality of series circuits, or all of “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs” serve as a singular current source, or if each series circuit (or each of the series circuits comprising “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”) serve as a current source each (multiple current sources). Similarly, it is unclear if all of the plurality of series circuits, or all of “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs” serve as a charging device, or if each series circuit (or each of the series circuits comprising “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”) serve as a charging device each (multiple charging devices). Similarly, it is unclear if all of the plurality of series circuits, or all of “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs” serve as “a capacitance”, or if each series circuit (or each of the series circuits comprising “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”) serve as “a capacitance” each (multiple charging devices).
Furthermore, claim 11 recites the limitations of: “can be discharged by way of the series circuits of the first FET and the second FET, or FET array”, and “a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array”. With the added context of there are a plurality of parallel-connected series circuits comprising a first FET and a second FET, it is unclear if “can be discharged by way of the series circuits of the first FET and the second FET, or FET array” is meant to be understood as the “capacitance” can be discharged by any one of the series circuits, or if it is meant to be understood as it can be discharged by all of the series circuits “can be discharged by way of the series circuits of the first FET and the second FET, or FET array”.
Claims 16-18 inherit the same deficiency as claim 11 based on dependence.
Regarding claim 16, claim 16 recites the limitations of: “circuit assemblies”, and “the respective circuit assembly”. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 17, claim 17 recites the limitation of: “upstream of each circuit assembly”. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 18, claim 18 recites the limitations of: “the circuit assembly for the processing of signed components of the weight vectors in each of the series circuits has two parallel circuit branches, which are connected to the second FET, or FET array, and in each case have a first FET”. It is unclear as to what “in each case” is referring to. Unclear if it is meant to be understood as each of the series circuits, or each branch.
Furthermore, claim 18 recites the limitation of: “the circuit assembly”. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, claim 18 recites the limitation of: “processing of signed components”. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, claim 18 recites the limitations of: “each of the series circuits has two parallel circuit branches, which are connected to the second FET, or FET array, and in each case have a first FET, wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance”. Claim 11 recites: “series circuits comprising a first FET”, “series circuits of the first FET”. Claim 11’s recitation of “a first FET” indicates a singular first FET, yet claim 18 recites multiple first FETs, as interpreted by the Examiner, through each branch, “two parallel circuit branches, which are connected to the second FET, or FET array, and in each case have a first FET”. It is unclear how the limitations of multiple first FETs of claim 18 coincide with the limitation of a singular first FET of claim 11.
Furthermore, claim 18 recites the limitations of: “wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance, which can be precharged by way of the charging means, and can be discharged by way of the series connection of the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as both “the capacitance” and “second capacitance” is precharged by way of the charging device, and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array) or if it is meant to be understood as only the “second capacitance” is precharged by way of the charging device and discharged by way of the series circuit comprising the first FET of the second circuit branch and the second FET (or FET array).
Furthermore, claim 11, which claim 18 is dependent upon, recites the limitations of: “a circuit array, which comprises: - a plurality of parallel-connected series circuits comprising a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs, serving as a current source, - a charging device, and - a capacitance”. The Examiner interprets this limitation to mean that there are a plurality of series circuits “a first FET, and a second FET, or an FET array comprising a plurality of parallel-connected second FETs”, and that each of these series circuits (either by individual components or by some combination of components) serve as “a current source, - a charging device, and - a capacitance” each. Given that context, it is unclear which capacitance is referred to in claim 18 limitations, “a first of the two circuit branches is connected to the capacitance”.
Furthermore, claim 18 recites the limitation of: “and can be discharged by way of the series connection of the first FET of the second circuit branch and the second FET, or FET array”. It is unclear if it is meant to be understood as the discharge is by way of the first FET and the second FET or by the FET array (by itself) or if it is meant to be understood as the discharge is by way of the first FET and the second FET or by way of the first FET and the FET array.
Furthermore, claim 18 recites the limitation of: “and can be discharged by way of the series connection of the first FET of the second circuit branch and the second FET, or FET array”. Claim 18 also recites the limitation of: “in each of the series circuits has two parallel circuit branches, which are connected to the second FET, or FET array, and in each case have a first FET, wherein a first of the two circuit branches is connected to the capacitance, and a second of the two circuit branches is connected to a second capacitance”. Claim 18 states that each of the series circuits comprises two branches, and, as interpreted by the Examiner, “and in each case comprise a first FET” refers to each branch. From this, it makes it unclear which series circuit is meant by “can be discharged by way of the series connection of the first FET of the second circuit branch and the second FET, or FET array,” since the claim seemingly states, as interpreted by the Examiner, that each of the series circuits would have this.
Deferring of Indication of Allowable Subject Matter
Due to the numerous amount of 35 U.S.C. 112(b) rejections made rendering the Examiner unable to reasonably discern many of the limitations claimed, the Examiner is deferring decision as to prior art and/or indication of allowable subject matter over prior art pending resolution of the 35 U.S.C. 112(b) rejections made.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Holler et al. (U.S. Patent 4956564), hereinafter, “Holler”
Describes a circuit, using transistors, for multiplication of an input voltage and a stored weight (Fig. 4; Fig. 5; Column 6 lines 25-38)
Describes use of a pulse width to represent inputs into the circuit (Column 5 lines 17-22)
Veale (U.S. Patent 3731206), hereinafter, “Veale”
Describes a multiplying circuit with a switch and a pulse generator circuit (Fig. 5a; column 8 lines 7-22)
Describes the pulse generator as a transistor switch (column 8 lines 33-42)
Describes the switch and pulse generator as transistor switches (column 13 lines 47-48)
Conclusion
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
1 Introduction to capacitors, capacitance and electric charge. (2017). electronics-tutorials.ws/capacitor/cap_1.html Regarding description of capacitance
Prosecution Insights