Prosecution Insights
Last updated: October 04, 2026
Application No. 17/926,505

LIGHT EMITTING DEVICE ARRAY

Non-Final OA §103§112
Filed
Nov 18, 2022
Priority
May 22, 2020 — GB 2007719.4 +1 more
Examiner
YEMELYANOV, DMITRIY
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Plessey Semiconductors Limited
OA Round
2 (Non-Final)
74%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
425 granted / 572 resolved
+6.3% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
41 currently pending
Career history
611
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
56.4%
+16.4% vs TC avg
§102
21.9%
-18.1% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “forming a light emitting stack on a substrate surface of a substrate, the light emitting stack having a light emitting surface orientated towards the substrate surface” “a first semiconducting layer provided towards the substrate surface” and “removing the substrate from the light emitting stack” of Claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 16-21, 24 and 25 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 16 recites “a second semiconducting layer provided towards a contact surface of the light emitting stack” is introduced despite having already been established in the claim. It is unclear whether a second, distinct contact surface is intended or whether this is mis citation of the previously defined contact surface. Claim 16 recites the limitation “the first contact layer configured to be in electrical contact with the first semiconducting layer” the Claim previously introduces “a first electrical contact layer,” not “first contact layer”. The inconsistent terminology creates ambiguity as to whether the same element or different, unclaimed element is being referenced. For the purposes of examination, the Examiner will treat ““the first contact layer configured to be in electrical contact with the first semiconducting layer” as --the first electrical contact layer configured to be in electrical contact with the first semiconducting layer--. Claim 16 recites the limitation "“a light extraction efficiency of light generated by the light emitting device layer" in line 22. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the Examiner will treat “a light extraction efficiency of light generated by the light emitting device layer” as --a light extraction efficiency of light generated by a light emitting device layer” Claim 19 as written it is unclear whether this limitation means that the pitch is not greater than 5um or, in the alternative, no greater than 2um or the pitch is no greater than 5 and must be exactly 2? Since one of ordinary skill in the art cannot determine with reasonable certainty which of these readings defines the claim’s actual boundary the claims fails definiteness standard under MPEP 2173. For the purposes of examination, the Examiner will consider claim limitation met as long as the pitch is not greater than 5um. Claims 17-21, 24 and 25 are rejected as being dependent on Claim 16. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 16-20, 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2011/0156616 A1) in view of Han (US 2016/0197151). Regarding Claim 16, Anderson (Fig. 3, 4) discloses a method of forming a light emitting device array comprising: forming a light emitting stack (430, 420, 410) on a substrate surface of a substrate (480), the light emitting stack (430, 420, 410) having a light emitting surface (surface closer to 430) orientated towards the substrate surface (480) and a contact surface on an opposing side of the light emitting stack (430, 420, 410), forming the light emitting stack (430, 420, 410) comprising forming a plurality of Group III-nitride layers (430, 420, 410) including: a first semiconducting layer (n-doped layer 430) provided towards the substrate surface (480); a second semiconducting layer (p-doped layer 410) provided towards a contact surface (surface closer to 410) of the light emitting stack (430, 420, 410); and an active layer (quantum well layer 420) provided between the first semiconducting layer (430) and the second semiconducting layer (410), the active layer configured to generate light having a first wavelength (“Alternating the two materials in, e.g. a multiple quantum well, creates a bandgap corresponding to a particular emission wavelength” [0042-0044]; wherein the light emitting surface and the contact surface of the light emitting stack (430, 420, 410) are formed parallel to each other and aligned with the plurality of Group III-nitride layers (430, 420, 410) (Fig. 4); forming an array of second electrical contacts (individually addressable electrodes 440) on the contact surface of the light emitting stack (surface closer to 410), each second electrical contact (440) defining a light emitting device (“electrically pixelated luminescent devices “, “spatial control of the light output by electrical pixelation”) [0027-0028, 0064, 0090-0092] between the first semiconducting layer (430) and the second electrical contact (440), wherein each of the second electrical contacts (440) are spaced apart from the other second electrical contacts to form a two-dimensional array of the light emitting devices (“electrically pixelated luminescent devices”); removing the substrate (480) from the light emitting stack [0080]; forming a first electrical contact layer (450) on the light emitting stack (430, 420, 410), the first contact layer (430) configured to be in electrical contact with the first semiconducting layer (450); and Anderson does not explicitly disclose forming an anti-reflection layer on the light emitting surface, the anti-reflection layer configured to increase a light extraction efficiency of light generated by the light emitting device layer. Han (Fig. 11) discloses forming an anti-reflection layer (“nanoporous GaN”) on a light emitting surface, the anti-reflection layer (“nanoporous GaN”) configured to increase a light extraction efficiency of light generated by the light emitting device layer. (“This index difference and the scattering nature of the porous structure can improve the extraction efficiency of light from a light-emitting device.”) [0061] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of forming a light emitting device in Anderson in view of Han such that an anti-reflection layer on the light emitting surface, the anti-reflection layer configured to increase a light extraction efficiency of light generated by the light emitting device layer in order to improve the extraction efficiency of light from a light-emitting device. [0061]. Examiner notes that “configured to increase a light extraction efficiency of light generated by the light emitting device layer.” is a functional language. While features of an apparatus may be recited either structurally or functionally, claim directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). Regarding Claim 17, Anderson in view of Han discloses the method according to claim 16, further comprising forming an absorbing layer (“light blocking elements placed between each specific light emission region of continuous light emitter layer.” And “mask may be positioned over all or part of the top surface of the EPLD in order to selectively absorb”) on at least a portion of the light emitting stack, the absorbing layer configured to absorb light of the first wavelength generated by the active layer. [0101 and Claim 24 Anderson] Regarding Claim 18, Anderson in view of Han discloses the method according to claim 16, wherein forming the anti-reflection layer (“nanoporous GaN” Han) comprises: forming a third semiconducting layer comprising a Group III-nitride (GaN) and a donor density of at least 1 × 10.sup.18 cm.sup.-3 on the light emitting surface (“doping density between approximately 5×10.sup.18 cm.sup.−3 and approximately 2×10.sup.20 cm.sup.−3 [0032-0034 Han]; and subjecting the third semiconducting layer (GaN) to a porosity treatment process to increase an areal porosity of the third semiconducting layer (GaN) to at least 30%. (“porosity of 40%”) [0042, 0047, 0048, 0050 Han] Regarding Claim 19, Anderson in view of Han discloses the method according to claim 16, wherein a pitch of each second electrical contact formed in the light emitting device array. (“the individually addressable electrodes are separated by a pixel pitch of 10 .mu.m or less.”) [0100, Claim 18] Anderson further discloses that optimizing pitch of each second electrical contact formed in the light emitting device array the individually addressable electrodes be separated by a desired pixel pitch. (“The pixel pitch may also be varied according to placement of the electrodes in a manner that is desired for the end use”).[0100] Anderson in view of Han does not explicitly disclose a pitch of each second electrical contact formed in the light emitting device array is no greater than 5 µm, or 2 µm. Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of forming a light emitting device in Anderson in view of Han such that an anti-reflection layer on the light emitting surface, the anti-reflection layer configured to increase a light extraction efficiency of light generated by the light emitting device layer in order to optimize a pitch of each second electrical contact formed in the light emitting device array to be no greater than 5 µm, or 2 µm for direct-viewing or illumination systems [0100, Claim 18] and since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 276 (CCPA 1980). Regarding Claim 20, Anderson in view of Han discloses the method according to claim 16, wherein forming the first electrical contact layer comprises forming a transparent conductive oxide on the light emitting surface (“a transparent conductor, e.g., Indium Tin Oxide (ITO)” [0085 Anderson]. Regarding Claim 24, Anderson in view of Han discloses the method according to claim 16, wherein forming the first semiconducting layer comprises forming a n-type doped Group III-nitride (“n-doped layer 430” 0075); and/or forming the second semiconducting layer comprises forming a p-type doped Group III-nitride (“ p-doped layer 410”) [0079] ; and/or forming the active layer comprises forming multiple quantum well layers comprising Group III-nitrides. (quantum well layer 420 (“single or double quantum well)” [0076] Regarding Claim 25, Anderson in view of Han discloses the method according to claim 16, wherein the active layer (quantum well layer 420) is formed as a continuous layer extending between at least two adjacent light emitting devices of the light emitting device array. (See Fig. 4) Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 2011/0156616 A1) in view of Han (US 2016/0197151) and further in view of Yuri (US 2005/0161696 A1). Regarding Claim 21, Anderson in view of Han discloses the method according to claim 20, wherein the anti-reflection layer (“nanoporous GaN” Han) is formed on the light emitting surface (Han) Anderson in view of Han does not explicitly disclose followed by forming the first electrical contact layer on the anti-reflection layer Yuri (Fig. 11, 12, 13) discloses forming an anti-reflection layer (porous structure 9) is formed on an light emitting surface (2) followed by forming a first electrical contact layer (transparent conductive film (transparent electrode) 13) on the anti-reflection layer. (9) [0115-0117] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method of forming a light emitting device in Anderson in view of Han and Yuri such that the anti-reflection layer (is formed on the light emitting surface followed by forming the first electrical contact layer on the anti-reflection layer so that the reliability of the device is improved more greatly and the efficiency of light emission of the device can be still further improved. [0116]. Response to Arguments Applicant's arguments filed 06/23/2026 have been fully considered but they are not persuasive. Regarding Applicant’s Arguments concerning Objection to the drawings The Examiner notes that substrate is an affirmatively claimed structural element of in Claim 16. It is the surface of which the light emitting stack is formed, it defines the orientation of the light emitting surface, and it is the subject of an express process step (“removing the substrate”). Under 37 C.F.R 1.83 (a) “the drawings must show every feature of the invention specified in the claims.” since the substrate is recited as a structural and process element, at least one figure must depict it. Regarding Applicants Arguments on page 10-11 concerning Claim 16. That prior art of does not disclose “forming an anti-reflection layer on the light emitting surface, the anti-reflection layer configured to increase a light extraction efficiency of light generated by the light emitting device layer.” The Examiner notes that Claim 16 requires “the anti-reflection layer configured to increase a light extraction efficiency of light generated by the light emitting device layer.” This limitation does not specify how the layer must work optically (quarter-wave interference, graded index etc) and defined entirely by outcome. Prior art of Han in [0061] states almost verbatim that purification “can improve the extraction efficiency of light from a light-emitting device”. That’s the same functional result as claim requires. The Examiner notes that anti-reflection layers work by inserting a refractive index step or gradient at an interface to reduce Fresnel reflection, so more light transmits through rather than reflecting back. Prior art of Han discloses exaclty this physics since porification “reduces the layer's refractive index….. by as much as 0.5, which can produce an appreciable index difference at an interface between a porous and non-porous layer.” [0061] and it’s precisely that “index difference” that “can improve the extraction efficiency of light from a light-emitting device”. Index contrast layer (Porous gallium-nitride layers 1110, 1150) at interface that increases the fraction of light escaping the device is functionally what ant-reflection layer is. Further, nothing in [0061] of Han limits the index contrast interface to the substrate interface. Its states property of any porous/non-porous boundary. The reason light gets “lost in the substrate 105” in the first place is the same underlying problem anti-reflection layer solves and the top surface (index mismatch causing internal reflection that prevents extraction). Prior art of Had is describing one instance of a general principal, a porous layer’s index contrast redirects light that would otherwise be lost, thereby raising overall extraction efficiency and that principle applies with equal if the porous layer sits at the light emitting surface or adjacent to the substrate. Han does not teach away from that placement. Fig. 11 nanoporous layer 1150 sits above p-GaN layer 1140 at the light emitting surface. The Applicant emphasizes that attributes this layer functions to facilitate “out-diffusion of acceptor bopund species” but Han never states that these functions are exclusive. A layer can simultaneously provide an out-diffusion pathway and exhibit the index contrast property Han generally attributes ito porous GaN in [0061]. The refractive index reduction is presented as an intrinsic consequence of purification itself. Under inherency principles, a property that necessarily flows from a disclosed structure doesn’t need to be restated. Layer 1150 is porous GaN, so it necessarily exhibits the index contrast effect Han describes. Therefore, Han discloses a porous III-nitride layer, formed and an interface that produces an index contrast which Han states increases light extraction efficiency and in Fig. 11 that layer is positioned an the top/light -emitting surface. That is a disclosure if an anti-reflection layer under the claim’s functional definition. Conclusion A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRIY YEMELYANOV/Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Nov 18, 2022
Application Filed
Dec 23, 2025
Non-Final Rejection mailed — §103, §112
Jun 23, 2026
Response Filed
Sep 01, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
74%
Grant Probability
94%
With Interview (+19.2%)
2y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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