DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The amendment filed on January 21st, 2026 has been acknowledged. By this amendment, claim 1 has been amended. Accordingly, claims 1-13 are pending in the present application in which claim 1 is in independent form.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019106284 A1 (of record; US 20200283924 A1 relied upon for a translation), hereafter "Nsalambi" in view of WO 2006013115 A1 (of record; translation provided with previous action), hereafter "Bestetti" and DE 19630049 A1 (translation provided with previous action), hereafter "Heitzer".
Regarding claim 1, Nsalambi teaches an electrical circuit 5 [0033] (Fig. 2) having electrical contacts 7 [0033] for chip card modules (see Fig. 1), comprising:
a dielectric substrate 4 [0032] with a sheet of electrically conductive material 10 [0039] (Fig. 3) resting on the dielectric substrate 4, at least one layer of an electrically conductive [0010] material 13 [0048] resting directly or indirectly on the sheet of electrically conductive material 10, this layer of the electrically conductive material 13 forming a surface layer (see 13) covering at least one region of the surface of at least one conductive track 6 [0047] (see Fig. 2), this conductive track 6 being formed in the sheet of electrically conductive material 10 ([0047]) and being configured to form the electrical contacts 7 [0033] (see Fig. 2).
Nsalambi does not teach that the surface layer 13 consists of a compound of XₚOqNrCs type, with X included in the list constituted by Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, and in which p and q are strictly positive and r and S are numbers at least one of which is greater than or equal to zero. Instead, Nsalambi teaches that the compound may be a rhodium alloy [0017] chosen in order to form a white/metallic white colored chip-card module (see [0006]) that blends well with the card material hosting the chip card module, while "retaining electrical and mechanical properties suitable for use thereof in chip card contact modules" [0006].
Bestetti teaches a method of depositing a protection/color coating (pg. 2, lines 15-25) on a device (end product) comprising conductive layers of nickel and copper (pg. 2, lines 21-22), wherein a surface layer COL (Fig. 2; pg. 7, line 4) is titanium oxide (see Example 27; pg. 61, line 22) and produces a colored surface (pg. 61, line 23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the rhodium alloy material of the surface layer 13 of Nsalambi with the titanium oxide surface layer COL of Bestetti, such that the surface layer 13 comprises a compound of XₚOqNrCs type, with X included in the list constituted by Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc (Ti, as taught by Bestetti), and in which p and q are strictly positive (where p = 1 and q = 2 for titanium oxide; where oxygen content can be varied depending on desired color; see Fig. 9) and r and S are numbers at least one of which is greater than or equal to zero (where both r and S are 0). One would be motivated to make such a substitution in order to form a layer that can produce a variety of different colors (see Table 1 of Fig. 9; pg. 21, lines 14- 15), so as to better suit a card design with different colors.
Bestetti does not explicitly motivate that the Ti oxide surface layer, as described, may be implemented with "electrical and mechanical properties suitable for use thereof in chip card contact modules" [0006], as required by Nsalambi.
Heitzer teaches an electrical circuit having electrical contacts for chip card modules (Fig. 1) comprising a surface layer 11 [0033] (Fig. 4) characterized in that the surface layer consists of a compound of XₚOqNrCs type, with X included in the list constituted by Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc (Ti), and in which p and q are strictly positive (where p = 1 and q = 2 for titanium oxide [0033]) and r and S are numbers at least one of which is greater than or equal to zero (where both r and S are 0). Further, Heitzer teaches the surface layer 11 is and can be provided to be implemented in chip card modules (see Fig. 1; [0010]) while still retaining suitable mechanical and electrical properties (see [0010]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize that the Ti oxide surface layer of Bestetti could suitably utilized to form a colored, patterned surface layer, as taught by Heitzer [0010] (see MPEP 2144.07).
Regarding claim 2, Nsalambi, in view of Bestetti and Heitzer, teaches the electrical circuit according to claim 1, wherein the surface layer 13 (TiO₂, as taught by Bestetti and Heitzer; where Ti has a mass of about 48 u and O₂ a mass of about 32 u) comprises 30% to 65% by weight of at least one of the metals included in the list constituted by Hf, Ta, Zr, Nb, Mo, Cr, V, Ti or Sc (where Ti is 60% by weight; see above), 0% to 40% by weight of nitrogen (0%), 15% to 55% by weight of oxygen (40% by weight) and 0% to 6% by weight of carbon (0%).
Regarding claim 3, Nsalambi, in view of Bestetti and Heitzer, teaches the electrical circuit according to claim 1.
Nsalambi does not teach a bond layer underlying the surface layer 13 comprising at least one of the metals in the following list: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium. Rather, Nsalambi teaches the surface layer 13 is formed on a nickel layer 11 [0034] (where no primer layer 12 is present [0011]).
Bestetti further teaches their device comprising a bond layer ME (Fig. 2; pg. 7, line 4) underlying the surface layer COL, the bond layer ME comprising at least one of the metals in the following list: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium (titanium; see pg. 61, lines 19-22 formed on a nickel layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the bond layer ME of Bestetti underlying the surface layer in order to manufacture a card chip with an interference coloring design (pg. 20, lines 15- 18) and for the same reasons discussed above in claim 1.
Regarding claim 4, Nsalambi, in view of Bestetti and Heitzer, teaches the electrical circuit according to claim 3, comprising the bond layer (ME of Besetti) having a thickness between 10 and 1000 nanometers (may be 1 micron; pg. 42, lines 10-11) and a surface layer 13 (titanium oxide layer taught by Bestetti) having a thickness between 100 and 2000 nanometers (see Fig. 9 'Pink', having a thickness of the oxidation layer of 170 nm; see further pg. 21, lines 14-15 regarding Table 1). One would be further motivated to include the teachings of Bestetti, specifically, to choose such thicknesses, for the same reasons discussed above regarding claim 1.
Regarding claim 5, Nsalambi in view of Bestetti and Heitzer teaches the electrical circuit according to claim 1, wherein X = Ti (as taught by Bestetti and Heitzer).
Regarding claim 6, Nsalambi teaches a chip card [0032] (Fig. 1) comprising a card body 1 [0032] and a module 2 [0032] inserted in a cavity [0032] formed in the card body 1, this module 2 comprising a connector 3 comprising the electrical circuit according to claim 1 (as taught by Nsalambi in view of Bestetti and Heitzer).
Regarding claim 7, Nsalambi teaches a manufacturing method specially designed for the manufacture of an electrical circuit (see title; Figs. 4a-4k) according to claim 1, this method comprising the following steps: providing a dielectric substrate 4 [0032] with a sheet of electrically conductive material 10 [0039] resting on the dielectric substrate 4, depositing at least one layer of an electrically conductive material 13 [0048] on the sheet of electrically conductive material 10, this layer of the electrically conductive material 13 forming a surface layer 13 covering at least one region of the surface of at least one conductive track 6 [0033](see [0017] and Fig. 2), this conductive
track 6 being formed in (so as to include) the sheet of electrically conductive material 10 and being configured to form the electrical contacts 7 [0033].
Nsalambi nor Heitzer teach that the method is characterized in that the formation of the surface layer 13 includes a step of physical vapour deposition from at least one metal target, in the composition of which at least one of the metals in the following list is involved: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium, and in the atmosphere of a gas comprising at least one of the following elements: argon, nitrogen and oxygen.
However, Bestetti further teaches that the formation of the surface layer (COL) includes a step of physical vapour deposition (reactive sputtering; pg. 61, lines 22-23) from at least one metal target (titanium oxide; pg. 7, line 13), in the composition of which at least one of the metals in the following list is involved: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium (titanium), and in the atmosphere of a gas comprising at least one of the following elements: argon, nitrogen and oxygen (Argon and Oxygen; see pg. 21, lines 4-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further include the teachings of Bestetti for the same reasons discussed above regarding claim 1.
Regarding claim 8, Nsalambi in view of Bestetti and Heitzer teaches the method according to claim 7, and Bestetti further teaches wherein the surface layer 13 (COL) comprises a compound of XₚOqNrCs type, with X included in the list constituted by Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, (where X is Ti of the titanium oxide) and in which p and q are strictly positive (where p= 1 and q=2) and r and S are numbers at least one of which is greater than or equal to zero (where they both =0).
Regarding claim 9, Nsalambi in view of Bestetti and Heitzer teaches the method according to claim 7.
Nsalambi does not teach wherein the surface layer 13 is deposited on a bond layer, which itself is formed from physical vapour deposition in the atmosphere of a working gas comprising argon, in which at least one metal target is used, in the composition of which at least one of the metals in the following list is involved: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium.
However, Bestetti further teaches wherein the surface layer 13 (COL) is deposited on a bond layer ME (Fig. 2; pg. 7, line 4; Ti of Example 27 on pg. 61), which itself is formed from physical vapour deposition (magnetron sputtering; pg. 61, lines 21-22) in the atmosphere of a working gas comprising argon (see pgs. 42-43; lines 24-25 and 1-6, respectively), in which at least one metal target (titanium; pg. 61, line 20) is used, in the composition of which at least one of the metals in the following list is involved: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium (titanium).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the bond layer ME of Bestetti underlying the surface layer in order to manufacture a card chip with an interference coloring design (pg. 20, lines 15- 18) and for the same reasons discussed above in claim 1.
Regarding claim 11, Nsalambi in view of Bestetti and Heitzer teaches the method according to claim 7, and Nsalambi further teaches wherein the bond layer ME ( Ti conductive layer of Bestetti) and the surface layer 13 are deposited on a leadframe (see [0008]) formed in the sheet of electrically conductive material [0008], in the course of steps prior to a step of transferring this leadframe to the dielectric substrate 4.
Regarding claim 13, Nsalambi in view of Bestetti and Heitzer teaches the method according to claim 7, and Nsalambi further teaches the manufacturing method comprising a step of producing a mask [0047] (to be deposited on the backside face 18 [0047]; Fig. 4k), prior to the formation of the surface layer 13 (see [0046,0047]), in order to selectively deposit the surface layer 13 only in certain regions (the top side region, i.e., the side that accommodates the conductive tracks 6 [0047]) of the sheet of electrically conductive material 10.
12. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nsalambi in view of Bestetti and Heitzer as applied to claim 9 above, and further in view of US 20150269474 A1 (of record), hereafter "Finn".
Regarding claim 10, Nsalambi in view of Bestetti and Heitzer teaches the method according to claim 9, as discussed above, and Nsalambi teaches the method further comprising a step of etching (chemically, see [0043]) the sheet of electrically conductive material 10 [0043] (see Fig. 4h) located between at least two conductive tracks (see portion of 10 between photoresist portions 16 [0042] in Fig. 4g), in order to disconnect these conductive tracks 6 (see Fig. 2).
However, Nsalambi does not specifically teach the step of etching is a step of laser etching the surface layer 13 (titanium oxide layer, as taught by Bestetti) and the bond layer (titanium layer of Bestetti).
Finn teaches a method for manufacturing an electrical circuit for chip card modules comprising a step of laser etching ('laser ablation'; [0444]) conductive material [0444] located between at least two conductive tracks (see Fig. 15A; so as to form "slits" 1530 [0444]), in order to disconnect these conductive tracks [0444].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a laser etching method, as taught by Finn, to separate the conductive tracks 6 of Nsalambi, given laser etching can provide finer feature spacing by about a factor of 4, as taught by Finn (see [027]) allowing more area to be used for conductive tracks.
13. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nsalambi in view of Bestetti and Heitzer as applied to claim 7 above, and further in view of US 20180323139 A1 (of record), hereafter "Degeilh".
Regarding claim 12, Nsalambi in view of Bestetti and Heitzer teaches the method according to claim 7, as discussed above. While Heitzer further teaches the surface layer is selectively disposed (so as to form a logo or pattern [0009,0034]), Nsalambi in view of Bestetti and Heitzer do not explicitly teach wherein the surface layer 13 (titanium oxide of Bestetti) is deposited selectively in at least one region of the surface of at least one conductive track 6 in the course of a step during which the surface layer 13, deposited on a support beforehand is transferred to the sheet of electrically conductive material 10 with the aid of a laser.
Degeilh teaches a method of manufacturing integrated circuit chip card modules (see [0018]), including a step wherein a surface layer 53 [0108](Figs. 8A & 8B; see also [0071, 0072], where the targeted material of LIFT process [0071] may be "Various conductive or insulating materials" [0072]) is deposited selectively ([0146,0147]) in at least one region of the surface of at least one conductive track (see patterns of 53 [0108] in Figs. 8A and 8B on contacts 28 [0108]) in the course of a step during which the surface layer 53 deposited on a support (donor substrate [0070,0072]) beforehand is transferred to the sheet of electrically conductive material (receiving substrate [0070,0072]; see electrical contact modules 4E [0108] of Fig. 8A) with the aid of a laser (LIFT method; see Fig. 2 [0070]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Degeilh to selectively deposit the surface layer 13 of Nsalambi in order to customize logos/patterns on the chip module ([0111,0112,0155]), as taught by Degeilh as opposed to providing a blanket coating of color, as taught by Nsalambi and Bestetti.
Response to Applicant’s Amendment and Arguments
Applicant's arguments filed January 21st, 2025 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant contends that there is no motivation to combine Nsalambi and Bestetti with Heitzer to arrive at an electrical circuit in which the surface layer consists of a compound of XₚOqNrCs type, with X included in the list constituted by Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, and in which p and q are strictly positive and r and s are numbers at least one of which is greater than or equal to zero, as recited in claim 1. Particularly, Applicants contends that amended claim 1 does not read on the technology taught by Heitzer, and that Heitzer discloses a conductive “Carbonlack” (carbon lacquer) that is doped with TiO2 pigment to provide color. In Hetizer’s system, the essential electrical conductively is provided by the carbon lacquer matrix itself, and the TiO2 is merely a passive pigment dispersed within this conductive and as disclosed in the specification, this layer is formed, for example, by a PVD process and must itself provide the required electrically conductive properties.
However, it is respectfully submitted that Applicant’s above argument is not persuasive because, Nsalambi discloses an electrical circuit having electrical contacts for chip card modules, including, inter-alia, at least one layer of an electrically conductive material 13 resting directly or indirectly on the sheet of electrically conductive material 10 thus constitutes a surface layer 13 covering at least one region of the surface of at least one conductive track 6 (see paragraphs [0010], [0047], [0048] and figs. 1-2).
Particularly, Nsalambi discloses that the surface layer 13 comprises a compound of rhodium alloy chosen in order to form a white/metallic white colored chip-card module (see paragraphs [0006], [0017] and figs. 1-2), Bestetti discloses an electrical circuit, including, inter-alia, a surface layer COL of titanium oxide (see page 7, line 4, page 61, line 22 and fig. 2) and produces a colored surface (see page 61, line 23), and Heitzer discloses an electrical circuit, including, inter-alia, a surface layer 11 consists of a compound of XₚOqNrCs type, with X included in the list constituted of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc. Note that, Heitzer discloses that the surface layer 11 includes Ti in which p = 1 and q = 2 for titanium oxide and r and s are 0 (see paragraphs [0032], [0033]). Heitzer further discloses that the surface layer 11 can be provided to be implemented in chip car modules while still retaining suitable mechanical and electrical properties (see paragraph [0010] and fig. 1).
In view of the above, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the features as taught by Bestetti and Heitzer into the electrical circuit of Nsalambi to obtain a surface layer that consists of a compound of XₚOqNrCs type, which X includes Ti, p = 1 and q = 2, and r and s are 0 so that when inserting the chip card into a chip card reader, a perfect contact at the contact surfaces is still guaranteed and to ensure that the electrically conductive layer and nay electrically conductive protective layer applied over it have the lowest possible electrical surface resistance (see paragraph [0010] of Heitzer) and furthermore it is respectfully submitted that it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Furthermore, in response to Applicant’s argument that the examiner’s conclusion of obviousness is based upper improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made and does not include knowledge gleaned only from the Applicant’s disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In the instant case, Heitzer discloses in a same field of endeavor, a chip card containing an electrical circuit (see paragraph [0001]), including, inter-alia, an electrically conductive layer 11 which constitutes a surface layer can be chosen to be blue, green or similar such that a good contact between the surface layer 11 and the underlying contact zone S is ensured (see paragraph [0032] and fig. 1). Heitzer further discloses that colors such as white or red are also possible, whereby carbon lacquer is advantageously doped with color pigments and that TiO2 can be chosen for white and purple for red thus achieving a particularly cost-effective color scheme. Thus, the teaching is obtained from Heitzer and does not include knowledge gleaned from Applicant’s disclosure, and therefore, the combination of Nsalambi, Bestetti, and Heitzer would not constitute impermissible hindsight.
Additionally, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., claim 1 clearly recites a surface layer that is made of or consists of the XₚOqNrCs compound. As disclosed in the specification, this layer is formed, for example, by a PVD process and must itself provide the required electrically conductive properties) are not recited in the rejected claim(s). It is respectfully submitted that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, notes that the claims are given the broadest reasonable interpretation (In re Hyatt, 211 F. 3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). Therefore, since Heitzer discloses that the electrically conductive layer which constitutes as the surface layer contains TiO2 and thus read on a surface layer that consists of a compound of XₚOqNrCs type, with X included Ti and in which p and q are strictly positive (p = 1 and q = 2 in the instant case), and r and s are numbers at least one of which is greater than or equal to zero (r and s = 0 in the instant case) regardless of how the surface layer is made.
For this reason, it is respectfully submitted that the rejection is proper.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
