Prosecution Insights
Last updated: October 26, 2026
Application No. 17/927,328

DISTRIBUTED PLASMA SOURCE ARRAY

Final Rejection §103§112
Filed
Nov 22, 2022
Priority
May 27, 2020 — provisional 63/030,644 +1 more
Examiner
ALEJANDRO MULERO, LUZ L
Art Unit
1716
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Lam Research Corporation
OA Round
2 (Final)
48%
Grant Probability
Moderate
3-4
OA Rounds
3m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 48% of resolved cases
48%
Career Allowance Rate
208 granted / 434 resolved
-17.1% vs TC avg
Strong +40% interview lift
Without
With
+39.7%
Interview Lift
resolved cases with interview
Typical timeline
4y 2m
Avg Prosecution
13 currently pending
Career history
455
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.7%
+9.7% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
24.0%
-16.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 434 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Once a limitation is introduced in a claim sequence subsequent use of that limitation must use either -- the -- or -- said --, or be appropriately differentiated to represent a different limitation, note that claim 8 recites the term “F inductive coils” in line 2, however, “F inductive coils” were introduced in independent claim 1-line 10. Clarification and/or correction are/is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-7 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063. With respect to independent claim 1, Lai et al. shows the invention as claimed including a substrate processing system, comprising: a processing chamber 100 including a window 152; a substrate support 112 arranged inside the processing chamber to support a substrate 114 during plasma processing; a first array including E inductive coils 154 arranged adjacent to and outside of the processing chamber, where E is an integer greater than three; and a second array including D RF direct drive circuits 170/174a/174b configured to output RF power to the first array, where D is an integer greater than three, and to generate plasma inside of the processing chamber (see, for example, Figs. 1 and 7-8, and their descriptions, especially paragraph 0025, Figs. 1 and 7 are shown below). PNG media_image1.png 485 335 media_image1.png Greyscale PNG media_image2.png 488 334 media_image2.png Greyscale Lai et al. does not expressly disclose the claimed third array including F inductive coils that are embedded within the window. Yamazawa et al. discloses a substrate processing system having a first array including a plurality of E inductive coils 62 arranged adjacent to and outside of the processing chamber, a second array including RF direct drive circuits 58 configured to output RF power to the first array, and a third array including a plurality of F inductive coils 64 that are embedded within the window 52, that are unconnected to the E inductive coils, and that are powered remotely without a direct connection to a power supply, wherein the E inductive coils generate magnetic fields that couple with and deliver RF energy to the F inductive coils (see, for example, Figs. 4A-B and 6, and their descriptions, Figs. 4A and 6 are shown below). PNG media_image3.png 235 245 media_image3.png Greyscale PNG media_image4.png 255 275 media_image4.png Greyscale Also, Yamawaku et al. discloses a substrate processing system having a first array including an E inductive coil 541 arranged adjacent to and outside of the processing chamber, a second array including a RF direct drive circuit 61 configured to output RF power to the first array, and a third array including a F inductive coil 542b that is embedded within a window 56, that is unconnected to the E inductive coil, and that is powered remotely without a direct connection to a power supply, wherein the E inductive coil generate magnetic fields that couple with and deliver RF energy to the F inductive coil (see, for example, Fig. 7, and its description, Fig. 7 is shown below). PNG media_image5.png 425 347 media_image5.png Greyscale Therefore, in view of these disclosures, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Lai et al. as to comprise the claimed third array of F inductive coils embedded within the window and powered remotely without a direct connection to a power supply by magnetic fields generated by the E inductive coils, because such configuration is known and used in the art as a suitable configuration to effectively and efficiently improve uniformity and controllability of plasma density distribution. Regarding claims 2-3, Lai et al. discloses that the distance between the bottom surface of the window and a top surface of the substrate support is in a range of 1/20 and 1/5 of the distance between the top surface of the substrate and the bottom surface of the ceiling of the chamber in order to ensure that the coil is effectively immersed in the plasma (see, for example, paragraph 0018). Therefore, a prima facie case of obviousness still exists because it would have been obvious to one of ordinary skill in the art before the filing date of the instant claimed invention to optimize the distance between a top surface of the substrate support and a bottom surface of the window during routine experimentation depending upon, for example, the desired coil immersion in the chamber and the desired plasma characteristics, and such limitation would not lend patentability to the instant application absent the showing of unexpected results. With respect to claims 4-5, it should be noted that Lai et al. discloses that the E inductive coils have one of a circular outer shape and a hexagonal outer shape, and that the E inductive coils are arranged in one of a rectangular array and a hexagonal array (see, for example, Figs. 7-8 and their descriptions, especially paragraph 0023). Concerning claims 6-7, Lai et al. discloses that the inductive coils have a cylindrical diameter that is a fraction of the workpiece diameter and/or a fraction of the diameter of the gas distribution plate (see, for example, paragraph 0013 and claims 2 and 12). Therefore, a prima facie case of obviousness still exists because it would have been obvious to one of ordinary skill in the art before the filing date of the instant claimed invention to optimize the outer diameter of the inductive coils during routine experimentation depending upon, for example, the desired plasma characteristics, and such limitation would not lend patentability to the instant application absent the showing of unexpected results. Concerning claims 11-14, it should be noted that in the apparatus of Lai et al. the window is made of a dielectric material and includes a frame portion 152a defining E cavities, wherein the E inductive coils in the first array are arranged in the E cavities of the frame portion; E windows 152b are arranged in a substrate-facing opening of the E cavities; and the dielectric window is arranged on a substrate-facing side of the frame portion; (see, for example Fig. 1 and its description). Claim(s) 8-9 and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Park et al., US 2012/0061022. With respect to claims 8-9, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above but do not expressly disclose wherein the first array further includes F inductive coils having at least one of a size and a shape that is different than the E inductive coils, where F is an integer greater than two; and wherein each of the E inductive coils includes a first inductive coil arranged inside of a second inductive coil. Park et al. discloses a substrate processing system comprising an array of E and F inductive coils 701,702 / 703,704 / 705,706 / 707,708,709 having a first inductive coil arranged inside of a second inductive coil, wherein the coils have at least one of a different size and a different shape, wherein the inductive coils is an integer greater than two (see, for example, Fig. 7 and its disclosure, Fig. 7 is shown below). PNG media_image6.png 508 257 media_image6.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. as to comprise the claimed E and F inductive coils because such configuration is known and used in the art as a suitable configuration to effectively and efficiently control ion density and/or achieve uniformity of the plasma ion density. Regarding claims 27-28, it should be noted that in the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Park et al., the E inductive coils (coil 701, 703, 705 and 707) of the first array are larger than the F inductive coils (702, 704, 706, 708-709) of the third array (see, for example, Figs. 7a-d of Park et al.). Additionally, in the embodiment of Fig. 7d, F would be greater (in number/quantity) than E since the embodiment shows two F coils (708-709) for one E coil (707). Furthermore, it should be noted that the teachings could also be interpreted as the inductive coils 701, 703, 705 and 707 reading on the F inductive coils while the coils 702, 704, 706, 708-709 could read on the E inductive coils, and thereby the F coils would be greater (in size) than the E coils (see, for example, Figs. 7a-d of Park et al.). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Collins, US 6,361,644 or Lo et al., US 2014/0273537 and Koshimizu, US 2010/0243162. Concerning claim 10, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above but do not expressly disclose that the E inductive coils include a first inductive coil inter-wound with a second inductive coil. Collins discloses a substrate processing system having coils 800,810/820,830/840a,840b,840c interwound/connected to each other (see, for example, Figs. 32-34 shown below and their descriptions). PNG media_image7.png 147 291 media_image7.png Greyscale PNG media_image8.png 232 317 media_image8.png Greyscale PNG media_image9.png 125 341 media_image9.png Greyscale Also, Koshimizu discloses a substrate processing system comprising coils 120b1, 120b2 interwound/connected to coils 120c1, 120c2 through conductive wires 125c1 and 125c2, respectively (see, for example, Figs. 11A and 11B shown below and their descriptions). PNG media_image10.png 261 289 media_image10.png Greyscale PNG media_image11.png 236 306 media_image11.png Greyscale Therefore, in view of these disclosures, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. so that the E inductive coils have a first inductive coil inter-wound with a second inductive coil because such configuration is known and used in the art as a suitable configuration to effectively and efficiently supply power to plural inductive coils to generate inductive plasma, control the plasma coupling, and change the plasma distribution. Claim(s) 15-19, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Long et al., US 2019/0385821. With respect to claim 15, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above but do not expressly disclose the claimed RF direct drive circuit. Long et al. discloses a substrate processing system comprising a RF direct drive circuits including: a clock generator 120 to generate a clock signal at a first frequency; a gate driver 122 to receive the clock signal; a bridge circuit 138 including: a first switch 140 with a control terminal connected to the gate driver, a first terminal and a second terminal; a second switch 142 with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal; a first DC supply 410 to supply a first voltage potential to the first terminal of the first switch; and a second DC supply 420 to supply a second voltage potential to the second terminal of the second switch (see, for example, Figs. 1-2, 4 and 6-7, and their descriptions, Fig. 7 is shown below). PNG media_image12.png 373 530 media_image12.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. as to further comprise the claimed RF direct drive circuit because such means is known and used in the art as a suitable means for effectively and efficiently supplying a desired power at a desired frequency. Concerning claims 16-18, Long et al. further discloses wherein the first voltage potential and the second voltage potential have opposite polarity and are approximately equal in magnitude (see, for example, paragraph 0044); wherein the second voltage potential is ground (see, for example, paragraph 0040); a current sensor 640 to sense current at the output node 130 and to generate a current signal; a voltage sensor 642 to sense a voltage at the output node and to generate a voltage signal; and a controller 644 including a phase offset calculator 646 to calculate a phase offset between the voltage signal and the current signal; and a clock adjuster 648 to adjust the first frequency based on the phase offset (see, for example, Figs. 6-7 and their descriptions, especially paragraphs 0006, 0014, 0051, 0055); and wherein the clock adjuster increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current (see, for example, Figs. 6-7 and their descriptions, especially paragraphs 0006-0007, 0014-0015). Regarding claim 24, Long et al. further discloses a controller 54/644 configured to control the RF drive circuits; and S sensors 640/642 configured to sense operational parameters corresponding to the RF drive circuit, respectively, where S is an integer greater than three, wherein the controller is configured to alter operation of the RF direct drive circuits based on the operational parameters sensed by the S sensors, respectively; (see, for example, Figs. 1 and 6-7, their descriptions, especially paragraphs 0014, 0037, 0051, 0055, 0060-0062). Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. as to further comprise the claimed controller and sensors means because such means are known and used in the art as suitable means for effectively and efficiently monitor and control the RF power supplied and thereby control and optimize the method performed within the apparatus. Claim(s) 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Raymond et al., US 2019/0007004. Regarding claim 20, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above but do not expressly disclose the claimed RF direct drive circuit. Raymond et al. discloses a substrate processing system comprising a RF direct drive circuit including a first inductor L1 including a first end and a second end; a second inductor L2 including a first end in communication with the first end of the first inductor and a second end; a first switch 110 including a first terminal, a second terminal and a control terminal; a second switch 112 including a first terminal, a second terminal and a control terminal; a first capacitor C1 including a first end and a second end, wherein the first end of the first capacitor is in communication with the second end of the first inductor and the first terminal of the first switch; and a second capacitor C2 including a first end and a second end, wherein the second end of the second capacitor is in communication with the second end of the second inductor and the second terminal of the second switch, wherein the second terminal of the first switch communicates with the first terminal of the second switch, the second end of the first capacitor and the first end of the second capacitor (see, for example, Figs. 1A, 6, 8, and 13 and their descriptions, Figs. 1A and 6 are shown below). PNG media_image13.png 463 604 media_image13.png Greyscale PNG media_image14.png 271 414 media_image14.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. as to further comprise the claimed RF direct drive circuit because such means is known and used in the art as a high-performance suitable means for effectively and efficiently supplying a desired power at a desired frequency. Concerning claim 21, it should be noted that Raymond et al. discloses a third capacitor Cb1 including a first end in communication with the first end of the first capacitor; and a fourth capacitor Cb2 including a first end in communication with the second end of the second capacitor (see, for example, Fig. 6 and its description). It should be noted that the third capacitor and the fourth capacitor of the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Raymond et al. would comprise a second end in communication with a first end of at least one of the E inductive coils, and a second end in communication with a second end of the at least one of the E inductive coils, respectively. Therefore, the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Raymond et al. would comprise the claimed structure. With respect to claim 22, Raymond et al. further discloses a voltage source 105 having one end connected to the first end of the first inductor and the first end of the second inductor and a second end connected to the second terminal of the first switch and the first terminal of the second switch (see, for example, Figs. 1A, 6, 8, and 13 and their descriptions). Therefore, the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Raymond et al. would comprise the claimed structure. Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Park et al., US 2012/0061022 or Lo et al., US 2014/0273537 or Tomioka et al., US 5,897,713. Concerning claim 23, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above but do not expressly disclose that an inductive coil surrounds the first array. Park et al. discloses a substrate processing system comprising an array of inductive coils 701,702 / 703,704 / 705,706 / 707,708,709 having an inductive coil surrounding a second inductive coil (see, for example, Fig. 7 and its disclosure, Fig. 7 is shown below). PNG media_image6.png 508 257 media_image6.png Greyscale Also, Lo et al., discloses a substrate processing system comprising an array of inductive coils 203/205/207 wherein an inductive coil surrounds a second inductive coil (see, for example, Fig. 2 and its disclosure, Fig. 2 is shown below). PNG media_image15.png 279 355 media_image15.png Greyscale Additionally, Tomioka et al. discloses a substrate processing system comprising an array of inductive coils 134, 135, 136, 137, 138 wherein an inductive coil surrounds a second inductive coil (see, for example, Fig. 14 and its disclosure, Fig. 14 is shown below). PNG media_image16.png 507 377 media_image16.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modify by Yamazawa et al. or Yamawaku et al. as to comprise an inductive coil surrounding the first array because such configuration is known and used in the art as a suitable configuration to effectively and efficiently control ion density and/or achieve uniformity of the plasma ion density within the chamber. Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Ishii, US 5,529,657 or Tomioka et al., US 5,897,713 or Chu et al., US 6,051,073 or Collins, US 6,361,644. Regarding claim 25, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above and it further discloses that the processing chamber includes side walls 102 but does not expressly disclose the claimed one or more inductive coils. Ishii discloses a substrate processing system comprising a chamber 2 including side walls and one or more inductive coils 125 each including one or more turns wound around an upper portion of the side walls, and wherein a first inductive coil 7 is arranged in a first plane above the window and the one or more inductive coils are arranged below the first plane (see, for example, Fig. 16 and its description). PNG media_image17.png 341 566 media_image17.png Greyscale Also, Tomioka et al. discloses a substrate processing system comprising a chamber including side walls and one or more inductive coils 55d/138 each including one or more turns wound around an upper portion of the side walls, and wherein inductive coils 55a-55c/134-137 are arranged in a first plane above the window and the one or more inductive coils are arranged below the first plane (see, for example, Figs. 12 and 14 and their descriptions, Figs. 12 and 14 are shown below). PNG media_image18.png 355 353 media_image18.png Greyscale PNG media_image19.png 508 373 media_image19.png Greyscale Additionally, Chu et al. discloses a substrate processing system comprising a chamber including side walls and one or more inductive coils (bottom coils 40) each including one or more turns wound around an upper portion of the side walls, and wherein inductive coils (top coils 40) are arranged in a first plane above the window and the one or more inductive coils are arranged below the first plane (see, for example, Figs. 1 and 5 and their descriptions, Figs. 1 and 5 are shown below). PNG media_image20.png 534 333 media_image20.png Greyscale PNG media_image21.png 253 235 media_image21.png Greyscale Furthermore, Collins discloses a substrate processing system comprising a chamber including side walls and one or more inductive coils 220 each including one or more turns wound around an upper portion of the side walls, and wherein inductive coils 145/235 are arranged in a first plane above the window and the one or more inductive coils are arranged below the first plane (see, for example, Figs. 10 and 15 and their descriptions, Figs. 1 and 5 are shown below). PNG media_image22.png 272 340 media_image22.png Greyscale PNG media_image23.png 283 349 media_image23.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. as to comprise the claimed inductive coil around an upper portion of the side walls because such configuration is known and used in the art as a suitable configuration to effectively and efficiently control ion density and/or achieve uniformity of the plasma ion density within the chamber. Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063 and Park et al., US 2012/0061022, as applied to claims 8-9 and 27-28 above, and further in view of Weldon et al., US 6,108,189 or Takayuki et al., JP 2010-010417 and Shannon et al., US 2009/0298287. Regarding claim 29, Lai et al., Yamazawa et al., Yamawaku et al., and Park et al., are applied as above but do not expressly disclose the claimed G electrode array. Weldon et al. discloses a substrate processing system comprising an array of G electrodes 110 embedded in the substrate support, wherein G is an integer greater than three; and RF circuit 120 to output RF power to the electrodes; (see, for example, Figs. 2 and 13d, and their descriptions, Figs. 2 and 13d are shown below). PNG media_image24.png 356 489 media_image24.png Greyscale PNG media_image25.png 160 285 media_image25.png Greyscale Also, Takayuki et al. discloses a substrate processing system comprising an array of G electrodes 18 and 19 embedded in the substrate support, wherein G is an integer greater than three; and RF circuits 10A and 10B to output RF power to the electrodes; (see, for example, Figs. 2-6C, and their descriptions, Figs. 4 and 6A are shown below). PNG media_image26.png 271 407 media_image26.png Greyscale PNG media_image27.png 271 406 media_image27.png Greyscale Therefore, in view of these disclosures, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Park et al., so as to comprise the claimed electrodes embedded in the substrate because such structure is known and used in the art as a suitable configuration to effectively and efficiently control and/or change the thickness of the ion sheath of the plasma above the substrate and thereby optimize the apparatus and the method performed within the apparatus. With respect to the claimed fifth array of RF direct drive circuits to output power to the electrodes being greater than three, Shannon et al. discloses a substrate processing system comprising electrodes embedded in the substrate support and more than three RF drive circuits 170d/170e/170f/180/185 to output RF power to the electrodes (see, for example, Figs. 12A and 12B and their descriptions, Fig. 12 A is shown below). PNG media_image28.png 333 491 media_image28.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Park et al. and Weldon et al. or Takayuki et al., so as to comprise the claimed number of RF drive circuits because such structure is known and used in the art as a suitable configuration to effectively and efficiently control the supply of a desired power to the electrodes, thereby optimizing the apparatus and the method performed within the apparatus. Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al., US 2009/0294065 in view of Yamazawa et al., US 2011/0094997 or Yamawaku et al., US 2016/0126063, as applied to claims 1-7 and 11-14, and further in view of Weldon et al., US 6,108,189 or Takayuki et al., JP 2010-010417 and Shannon et al., US 2009/0298287. Concerning claim 30, Lai et al., Yamazawa et al. and Yamawaku et al. are applied as above but do not expressly disclose the claimed G electrode array. Weldon et al. discloses a substrate processing system comprising an array of G electrodes 110 embedded in the substrate support, wherein G is an integer greater than three; and RF circuit 120 to output RF power to the electrodes; (see, for example, Figs. 2 and 13d, and their descriptions, Figs. 2 and 13d are shown below). PNG media_image24.png 356 489 media_image24.png Greyscale PNG media_image25.png 160 285 media_image25.png Greyscale Also, Takayuki et al. discloses a substrate processing system comprising an array of G electrodes 18 and 19 embedded in the substrate support, wherein G is an integer greater than three; and RF circuits 10A and 10B to output RF power to the electrodes; (see, for example, Figs. 2-6C, and their descriptions, Figs. 4 and 6A are shown below). PNG media_image26.png 271 407 media_image26.png Greyscale PNG media_image27.png 271 406 media_image27.png Greyscale Therefore, in view of these disclosures, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. so as to comprise the claimed electrodes embedded in the substrate because such structure is known and used in the art as a suitable configuration to effectively and efficiently control and/or change the thickness of the ion sheath of the plasma above the substrate and thereby optimize the apparatus and the method performed within the apparatus. With respect to the claimed fifth array of RF direct drive circuits to output power to the electrodes being greater than three, Shannon et al. discloses a substrate processing system comprising electrodes embedded in the substrate support and more than three RF drive circuits 170d/170e/170f/180/185 to output RF power to the electrodes (see, for example, Figs. 12A and 12B and their descriptions, Fig. 12 A is shown below). PNG media_image28.png 333 491 media_image28.png Greyscale Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the filing date of the claimed invention to modify the apparatus of Lai et al. modified by Yamazawa et al. or Yamawaku et al. and Weldon et al. or Takayuki et al., so as to comprise the claimed number of RF drive circuits because such structure is known and used in the art as a suitable configuration to effectively and efficiently control the supply of a desired power to the electrodes, thereby optimizing the apparatus and the method performed within the apparatus. Response to Arguments Applicant’s arguments with respect to claim(s) 1-25 and 27-30 have been considered but are moot in view of the new grounds of rejection. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (US 6,527,968) is cited for its teachings of multiple electrodes embedded within the substrate support. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUZ L ALEJANDRO whose telephone number is (571)272-1430. The examiner can normally be reached Monday and Thursday, 8:30 a.m. - 5:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Parviz Hassanzadeh can be reached at 571-272-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LUZ L ALEJANDRO MULERO/Primary Examiner, Art Unit 1716 September 26, 2026
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Prosecution Timeline

Nov 22, 2022
Application Filed
Jan 28, 2026
Non-Final Rejection mailed — §103, §112
May 04, 2026
Applicant Interview (Telephonic)
May 04, 2026
Examiner Interview Summary
May 21, 2026
Response Filed
Sep 30, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772756
INSULATION PLATE AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME
4y 11m to grant Granted Oct 20, 2026
Patent 12763293
SUBSTRATE SUPPORT, PLASMA PROCESSING SYSTEM, AND PLASMA ETCHING METHOD
4y 8m to grant Granted Oct 13, 2026
Patent 12755946
SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
3y 7m to grant Granted Oct 06, 2026
Patent 12749662
SUPPORTING UNIT AND APPARATUS FOR TREATING SUBSTRATE
4y 1m to grant Granted Sep 29, 2026
Patent 12742242
METHODS OF FORMING STRUCTURES, SEMICONDUCTOR PROCESSING SYSTEMS, AND SEMICONDUCTOR DEVICE STRUCTURES
2y 6m to grant Granted Sep 22, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
48%
Grant Probability
88%
With Interview (+39.7%)
4y 2m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 434 resolved cases by this examiner. Grant probability derived from career allowance rate.

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