Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/20/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-7, 10, and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Shiraishi (US 20090085227 A1) in view of Min (US 20180063956 A1) and Caletka (US 20030199121 A1).
Regarding claim 1, Shiraishi discloses a method (Figs. 4A-4E) for joining and insulating (the method step of Fig. 4E) a power electronic semiconductor component (10; [0171]: “a power supply module”) with a multiplicity of contact surfaces (11, 21) to a substrate (40), the method comprising:
preparing the substrate with a metallization (22, 41) defining an installation slot (See annotated figure for dashed reference lines showing where 11 is subsequently installed, thus a slot; similarly shown for a fully assembled embodiment in Fig. 4E) having joining material (30),
wherein the substrate comprises an organic or a ceramic wiring support (40 supports metallization/wirings 41);
arranging a continuous sheet (“continuous” from one horizontal edge to another) of an electrically insulating plastic film (20; [0158]: “thermosetting resin, photo-curable resin, thermoplastic resin and hot-melt-type resin”) on the substrate so that a corresponding multiplicity of recesses in the plastic film align with electrical connections on the substrate for each of the multiplicity of contact surfaces;
applying the semiconductor component on top of the electrically insulating plastic film (the method step of Figs. 4C-4E) such that the multiplicity of contact surfaces facing the substrate contact the substrate (indirect contact) through the electrically insulating plastic film (vertically through) and regions of the semiconductor component (See annotated figure for “regions” designation) between the multiplicity of contact surfaces are insulated at least in part by the electrically insulating plastic film from the substrate (These regions are insulated from substrate 40 because film 20 keeps them spaced from the substrate) and from the multiplicity of contact surfaces (the regions of component 10 are not shown having a direct electrical path through film 20 from contacts 21, therefore electrically insulating); and
joining the semiconductor component to the substrate (the method step of Figs. 4C-4E) with an electrically conductive joining material (50; [0168]: “solder bumps”) and electrically insulating the semiconductor component at least in part by the electrically insulating plastic film in one step (20 is already on 10 before joining component 10 to substrate 40, thus the joining and insulating of 10 to 40 occurs at the same step).
Illustrated below are marked and annotated figures of Figs. 4A-4E of Shiraishi.
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Shiraishi teaches the method includes the substrate, but fails to teach specific materials used for this substrate. Thus, Shiraishi fails to teach “wherein the substrate comprises an organic or a ceramic wiring support”.
Min discloses a method with a substrate in the same field of endeavor (Fig. 11: 11), and teaches a finite selection of known suitable substrate materials ([0055]) wherein the substrate comprises an organic or a ceramic wiring support (selecting “organic”; [0055] “a plastic board or a film”). Modifying the method of Shiraishi by including the substrate material used by Min would arrive at the claimed method and substrate configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success choosing a material disclosed by Min for the substrate of Shiraishi, because in each situation the substrate is performing the same function as a circuitry support (Shiraishi: [0151]: “circuit substrate”; Min: [0055]: “printed circuit board”) for an electronic component (Shiraishi: [0171]: “the semiconductor package”; Min: [0055]: “an integrated circuit chip”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a method with a different material for the substrate. Therefore, the claim would have been obvious because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Illustrated below is Fig. 11 of Min.
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Shiraishi in view of Min teaches the method includes the plastic film, fails to teach the claimed shape configuration “so that a corresponding multiplicity of recesses in the plastic film align with electrical connections on the substrate for each of the multiplicity of contact surfaces”.
Caletka discloses a method (Fig. 2) arranging a continuous sheet of an electrically insulating plastic film (17; [0030]: “Kapton”) on the substrate (13) so that a corresponding multiplicity of recesses in the plastic film ([0030]: “punched or drilled with holes”) align with electrical connections (16) on the substrate for each of the multiplicity of contact surfaces (5).
Modifying the method of Shiraishi in view of Min by incorporating the plastic film shape of Caletka would arrive at the claimed method and film configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the plastic film provides support during a solder manufacturing step (Shiraishi: Figs. 4A-4E illustrate a solder operation; Caletka: [0030]: “reflow”). Caletka provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed method and film shape in that it would enhance strength of the component ([0030]: “acts to provide stress relief to the solder ball interconnections by redistributing stress due to thermal expansion mismatch”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and film configuration because it would enhance strength of the component.
Illustrated below is Fig. 2 of Caletka.
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Regarding claim 2, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Figs. 4C-4E), wherein the semiconductor component contacts the joining material (component 10 directly contacts joining material 30 beginning in Fig. 4C) and/or the electrically insulating plastic film (component 10 includes surfaces 21 which directly contact film 20).
Regarding claim 3, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Fig. 4E), further comprising closing a remaining gap between the metallization, the electrically insulating plastic film, and the semiconductor component using an underfill material (See annotated figure, shown as resin separated from solder 50).
Regarding claim 4, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Figs. 4C-4E), further comprising exerting pressure on the semiconductor component (component 10 is now shown pressed against substrate 40, thus, at least some pressure must be exerted) to join the semiconductor component such that the electrically insulating plastic film is exposed to the pressure at least in part during joining (film 20 is shown touching substrate 40, thus, it must also be exposed to the same exertion to at least some extent).
Regarding claim 5, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Fig. 4C), wherein the electrically insulating plastic film electrically insulates the joining material from the regions of the semiconductor component exposed by the contact surfaces (as reasoned in the claim 1 rejection, the film 20 is electrically insulating, therefore any path between the regions and contacts 11 that have 50 intervening would electrically insulate in the way claimed).
Regarding claim 6, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Fig. 4A), wherein the electrically insulating plastic film insulates a guard ring region of the semiconductor component (See annotated figure for the designated “a guard ring region”; as reasoned in the claim 1 rejection, the film 20 is electrically insulating, therefore any portion of 10 with 20 on it would be insulated in the way claimed).
Regarding claim 7, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Fig. 4E), wherein the electrically insulating plastic film, after joining, protrudes (vertically protrudes) from a gap (See annotated figure for “gap” designation, i.e., the space between 10 and 40) between the metallization of the substrate and the semiconductor component.
Regarding claim 10, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1 (Shiraishi: Fig. 4A), wherein the electrically insulating plastic film comprises an adhesive layer ([0159]: “bonding resin-coated core spacer”).
Regarding independent claim 12, Shiraishi discloses a composite (Fig. 4E) comprising:
a power electronic semiconductor component (10; [0171]: “a power supply module”) with a multiplicity of contact surfaces (11, 21);
a substrate (40) with a structured metallization (22, 41) defining an installation slot (See annotated Fig. 4A for dashed reference lines showing where 11 is subsequently installed, thus a slot; similarly shown for a fully assembled embodiment in Fig. 4E);
wherein the substrate comprises an organic and/or a ceramic wiring support;
wherein the contact surfaces are joined to the structured metallization by an electrically conductive joining material (50; [0168]: “solder bumps”);
a continuous sheet (“continuous” from one horizontal edge to another) of an electrically insulating plastic film (20; [0158]: “thermosetting resin, photo-curable resin, thermoplastic resin and hot-melt-type resin”) arranged between the semiconductor component and the substrate (vertically between), across the installation slot, with recesses at locations of contact surfaces in such a way that regions of the semiconductor component (See annotated figure for “regions” designation) surrounding individual contact surfaces of the multiplicity of contact surfaces are insulated at least in part by the electrically insulating plastic film from the substrate (These regions are insulated from substrate 40 because film 20 keeps them spaced from the substrate) and from the neighboring contact surfaces (the regions of component 10 are not shown having a direct electrical path through film 20 from contacts 21, therefore electrically insulating).
Shiraishi teaches the substrate but fails to teach specific materials used for the substrate. Thus, Shiraishi fails to teach “wherein the substrate comprises an organic and/or a ceramic wiring support”.
Min discloses a substrate in the same field of endeavor (Fig. 11: 11), and teaches a finite selection of known suitable substrate materials ([0055]) • wherein the substrate comprises an organic and/or a ceramic wiring support (selecting “organic”; [0055] “a plastic board or a film”). Modifying the substrate of Shiraishi by including the material used by Min would arrive at the claimed substrate configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success choosing a material disclosed by Min for the substrate of Shiraishi, because in each situation the substrate is performing the same function as a substrate (Shiraishi: [0151]: “circuit substrate”; Min: [0055]: “printed circuit board”) for an electronic component (Shiraishi: [0171]: “the semiconductor package”; Min: [0055]: “an integrated circuit chip”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material for the substrate. Therefore, the claim would have been obvious because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Shiraishi in view of Min teaches the plastic film, fails to teach the claimed shape configuration “a continuous sheet of an electrically insulating plastic film arranged between the semiconductor component and the substrate, across the installation slot, with recesses at locations of contact surfaces in such a way that regions of the semiconductor component surrounding individual contact surfaces of the multiplicity of contact surfaces are insulated at least in part by the electrically insulating plastic film from the substrate and from the neighboring contact surfaces”.
Caletka discloses a continuous sheet of an electrically insulating plastic film (Fig. 2: 17; [0030]: “Kapton”) arranged between the semiconductor component (7) and the substrate (13), across the installation slot, with recesses at locations of contact surfaces (5) in such a way that regions of the semiconductor component surrounding individual contact surfaces of the multiplicity of contact surfaces are insulated at least in part by the electrically insulating plastic film from the substrate (vertically insulated) and from the neighboring contact surfaces (horizontally insulated).
Modifying the plastic film shape configuration of Shiraishi in view of Min by incorporating the plastic film shape of Caletka would arrive at the claimed film configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the plastic film provides support during a solder manufacturing step (Shiraishi: Figs. 4A-4E illustrate a solder operation; Caletka: [0030]: “reflow”). Caletka provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed film shape in that it would enhance strength of the component ([0030]: “acts to provide stress relief to the solder ball interconnections by redistributing stress due to thermal expansion mismatch”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed film configuration because it would enhance strength of the component.
Regarding claim 13, Shiraishi in view of Min and Caletka discloses the composite as claimed in claim 12 (Shiraishi: Fig. 4E), wherein the electrically insulating plastic film protrudes under the semiconductor component (film 20 vertically protrudes under component 10).
Regarding claim 14, Shiraishi in view of Min and Caletka discloses the composite as claimed in claim 12 (Shiraishi: Fig. 4E), wherein the electrically insulating plastic film is completely covered by the semiconductor component (vertically covered, no portion of 20 is not vertically overlapped by component 10).
Regarding claim 15, Shiraishi in view of Min and Caletka discloses the composite as claimed in claim 12 (Shiraishi: Fig. 4E), wherein the electrically insulating plastic film is arranged in such a way that a guard ring region of the semiconductor component (See annotated figure for the designated “a guard ring region”) is electrically insulated from the electrically insulating plastic film (as reasoned in the claim 1 rejection, the film 20 is electrically insulating, therefore any portion of 10 with 20 on it would be insulated in the way claimed).
Regarding claim 16, Shiraishi in view of Min and Caletka discloses the composite as claimed in claim 12 (Shiraishi: Fig. 4E), further comprising an underfill material (See annotated figure, shown as resin separated from solder 50) in a gap between the structured metallization, the electrically insulating plastic film, and the semiconductor component (See annotated figure for “gap” designation, i.e., the space between 10 and 40).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shiraishi, Min, and Caletka as applied to claim 1 above, and further in view of Arvin (US 20190295921 A1).
Regarding claim 8, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1, however fails to teach wherein the electrically insulating plastic film comprises a silicone elastomer.
Arvin discloses a method (Fig. 3: 16 is affixed to 12 by including adhesive 18) wherein a film (16) is affixed to a substrate (12) by including an adhesive (18), and further discloses the adhesive including a silicone elastomer ([0030]: “low modulus silicone-based adhesive”).
Since Shiraishi in view of Min and Caletka, and Arvin each disclose methods attaching films to a substrate (Shiraishi: [0159]: “bonding resin-coated core spacer”; Arvin: Fig. 3: 16 is affixed to 12 by including adhesive 18), a person having ordinary skill in the art before the effective filing date would have readily recognized the finite number of predictable solutions for adhesives useful for attaching the film, including a silicon elastomer (Arvin, [0030]). A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the film includes a rubber (Shiraishi: [0163]: “rubber-based materials”; Arvin: [0030]: “low modulus silicone-based adhesive”) performing the same function (Shiraishi: [0149]: “spacers”; Arvin: [0028]: “stiffener…held flat”). Absent unexpected results, it would have been obvious to try using a different adhesive with the electrically insulating plastic film of Shiraishi, Min, and Caletka, because Arvin teaches the adhesive is useful for performing the same function required by Shiraishi, Min, and Caletka. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. MPEP 2143 (1)(E).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shiraishi, Min, and Caletka as applied to claim 1 above, and further in view of Sawada (US 20100001411 A1).
Regarding claim 9, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1, however fails to teach “wherein the electrically insulating plastic film comprises a ceramic filler”.
Sawada discloses a method (Figs. 2A-2D) wherein the electrically insulating plastic film (20) comprises a ceramic filler ([0070]: “A filler…an alumina particles”). Modifying the film of Shiraishi in view of Min and Caletka by including a ceramic filler in the way disclosed by Sawada would arrive at the claimed film configuration. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the film is performing the same function (Shiraishi: [0149]: “spacers”; Sawada: [0070]: “partition member”). Sawada provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include a ceramic filler in that it would allow adjusting viscosity of the film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed filler configuration because it would allow adjusting viscosity of the electrically insulating plastic film. MPEP 2143 (I)(G).
Regarding claim 11, Shiraishi in view of Min and Caletka discloses the method as claimed in claim 1, however fails to teach “wherein the electrically insulating plastic film comprises a glass fiber filling”.
Sawada discloses a method (Figs. 2A-2D) wherein the electrically insulating plastic film (20) comprises a glass fiber filling ([0070]: “A filler such as a silica particles or an alumina particles”). Modifying the film of Shiraishi in view of Min and Caletka by including a glass fiber filling in the way disclosed by Sawada would arrive at the claimed film configuration. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the film is performing the same function (Shiraishi: [0149]: “spacers”; Sawada: [0070]: “partition member”). Sawada provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include a glass fiber filling in that it would allow adjusting viscosity of the film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed filling configuration because it would allow adjusting viscosity of the electrically insulating plastic film. MPEP 2143 (I)(G).
Claims
12. (Currently Amended) A composite comprising:
a power electronic semiconductor component with a multiplicity of contact surfaces;
a substrate with a structured metallization defining an installation slot;
wherein the substrate comprises an organic and/or a ceramic wiring support;
wherein the contact surfaces are joined to the structured metallization by an electrically conductive joining material;
a continuous sheet of an electrically insulating plastic film arranged between the semiconductor component and the substrate, across the installation slot, with recesses at locations of contact surfaces in such a way that regions of the semiconductor component surrounding individual contact surfaces of the multiplicity of contact surfaces are insulated at least in part by the electrically insulating plastic film from the substrate and from the neighboring contact surfaces.
13. (Previously Presented) The composite as claimed in claim 12, wherein the electrically insulating plastic film protrudes under the semiconductor component.
14. (Previously Presented) The composite as claimed in claim 12, wherein the electrically insulating plastic film is completely covered by the semiconductor component.
15. (Previously Presented) The composite as claimed in claim 12, wherein the electrically insulating plastic film is arranged in such a way that a guard ring region of the semiconductor component is electrically insulated from the electrically insulating plastic film.
16. (Previously Presented) The composite as claimed in claim 12, further comprising an underfill material in a gap between the structured metallization, the electrically insulating plastic film, and the semiconductor component.
Response to Arguments
Applicant's arguments filed 4/20/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 12 that “In the rejection of Independent Claim 1 as previously presented, the Examiner relies on the individual spacers (20) of Shiraishi as equivalent to the recited electrically insulating plastic film (Office Action, Page 3). Without consenting to this interpretation, Applicant respectfully suggests the current amendments clarify that the plastic film is a continuous sheet applied across the installation slot. As described at least in Paragraph 30 of the Specification as published, "the film is arranged on the substrate in such a way that the joining material protrudes through the film. The film therefore has recesses at the points at which the joining material is provided."
The spacers (20) of Shiraishi do not meet this limitation. The remaining references do not cure the identified lack. For at least these reasons, Independent Claim 1 is not rendered obvious by the cited references, whether considered alone or in combination. Independent Claim 12 recites analogous limitations and is allowable for analogous reasons.”. Remarks at pg. 7.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Caletka has been relied upon in the instant Office action to teach a difference in shape consistent with the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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