DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 1 filed on 01/05/2026 has been fully considered for examination based on their merits. The previously presented claim(s) 2-11, and 13-21 have been considered. Claim 12 is canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-12, filed 01/05/2026, with respect to the rejection(s) of claim(s) 1-11, and 13-21 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of SUGIURA.
Regarding Independent Claim 1. The Applicant argues (see Remarks, pages 8-9) that the combination of prior art (MIZUSHIMA, QUDDUS AND YEDINAK) does not disclose or suggest all of the amended limitations to claim 1, now recites, “an upper insulating film…cover at least a part of the Schottky electrode…between the upper insulating film and the main surface insulating film.” The Examiner agrees and, therefore, the rejection of the record has been withdrawn with respect to Claim 1. However, upon further consideration, a new ground(s) of rejection is made for the Claim 1 amendments, as discussed above.
Regarding Claim(s) 2-11, and 13-21. The claims 2-11, and 13-21 depend on the independent claim 1, and therefore, follows the similar arguments as mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9, and 13-14, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIZUSHIMA (prior art used in the previous OA filed 10/09/2025), in view of QUDDUS (prior art used in the previous OA filed 10/09/2025), and Hiroto Sugiura, (hereinafter SUGIURA), US20150228809 A1.
Regarding Claim 1, MIZUSHIMA teaches in Figure 3, a semiconductor device (TMBS diode, [0060]) comprising:
a semiconductor layer (2, n-type drift layer) of a first conductivity type (n-type) which has a main surface (1, n-type semiconductor substrate):
a trench separation structure (7, end portion trench) which includes a separation trench (annotated Figure 3) that is formed in the main surface (1, n-type semiconductor substrate), a separation insulating film (11, oxide film) that covers a wall surface of the separation trench (annotated Figure 3) and a separation electrode (13, polysilicon) that is embedded in the separation trench (7, end portion trench) across the separation insulating film (11, oxide film), trench separation structure (7, end portion trench) demarcating an outer region (22, voltage withstanding structure) and an active region (21, active portion) in the main surface (1, n-type semiconductor substrate);
a floating region of a second conductivity type (10, p-type floating layer) which is formed in an electrically floating state at a surface layer portion (annotated Figure 3) of the main surface (1, n-type semiconductor substrate) along the trench separation structure (7, end portion trench) in the outer region (22, voltage withstanding structure);
a Schottky electrode (3, anode electrode, [0062]) which is electrically connected (annotated Figure 3) to the separation electrode (13, polysilicon) such as to retain the floating region (10, p-type floating layer) in the electrically floating state in the outer region (22, voltage withstanding structure) and which forms a Schottky junction (16, Schottky barrier junction) with the main surface (1, n-type semiconductor substrate) in the active region (21, active portion).
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MIZUSHIMA does not explicitly disclose a semiconductor device comprising:
a main surface insulating film which is formed on the outer region such as to cover an entire area of the floating region.
QUDDUS teaches a semiconductor device (Fig. 1, 10A, an electronic device, semiconductor device, Schottky diode device, or trench Schottky rectifier, [0020]) comprising:
a main surface (Fig. 5, 14, semiconductor layer) insulating film (Fig. 5, 219, dielectric layer) which is formed on the outer region (annotated Figure 5) such as to cover an entire area (dielectric layer, 219 completely overlaps doped regions, 24, [0037]) of the floating region (Fig. 5, 24, doped regions are electrically floating similar to termination trench structures, 100A, [0037]).
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Therefore, it would have been a prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MIZUSHIMA to incorporate teachings of QUDDUS such that a semiconductor device comprising: a main surface insulating film which is formed on the outer region such as to cover an entire area of the floating region, so that the doped regions (24) are electrically floating similar to termination trench structures (100A), wherein no contact is made to conductive material, and thus the device (10A) has better electrical performance than related devices (QUDDUS, [0029], [0037], [0045]).
MIZUSHIMA as modified by QUDDUS does not explicitly disclose a semiconductor device comprising: an upper insulating film which is formed on the main surface insulating film so as to cover at least a part of the Schottky electrode such that the at least a part of the Schottky electrode is between the upper insulating film and the main surface film.
SUGIURA teaches in Figure 1E, a semiconductor device (Fig. 1, Schottky barrier diode, [0020]) comprising: an upper insulating film (Fig. 1E, 11, surface protection film) which is formed on the main surface insulating film (Fig. 1E, 31, oxide film) so as to cover at least a part of the Schottky electrode (Fig. 1E, 9, Schottky metal) such that the at least a part of the Schottky electrode (Fig. 1E, 9, Schottky metal) is between the upper insulating film (Fig. 1E, 11, surface protection film) and the main surface film (Fig. 1E, 31, oxide film).
Therefore, it would have been a prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have MIZUSHIMA as modified by QUDDUS to incorporate teachings of SUGIURA such that a semiconductor device comprising: an upper insulating film which is formed on the main surface insulating film so as to cover at least a part of the Schottky electrode such that the at least a part of the Schottky electrode is between the upper insulating film and the main surface film, so that the a forward voltage can be decreased without scarifying a leakage current (SUGIURA, [0011]).
Regarding Claim 2, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the floating region (10, p-type floating layer) is adjacent (annotated Figure 3) to the trench separation structure (7, end portion trench) in the outer region (22, voltage withstanding structure).
Regarding Claim 3, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, a semiconductor device (TMBS diode, [0060]), wherein
the floating region (10, p-type floating layer) is formed in a depth range (annotated Figure 3) between the main surface (1, n-type semiconductor substrate) and a bottom wall of the trench separation structure (7, end portion trench) in the outer region (22, voltage withstanding structure).
Regarding Claim 4, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the floating region (10, p-type floating layer) is formed deeper (annotated Figure 3) than the trench separation structure (7, end portion trench).
Regarding Claim 5, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the floating region (10, p-type floating layer) has a covering portion (annotated Figure 3) of which covers the bottom wall (annotated Figure 3) of the trench separation structure (7, end portion trench).
Regarding Claim 6, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 5.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the covering portion covers a portion (annotated Figure 3) on the outer region side (22, voltage withstanding structure) such as to expose a portion (annotated Figure 3) on the active region side (21, active portion) in the bottom wall (annotated Figure 3) of the trench separation structure (7, end portion trench).
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Regarding Claim 7, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the trench separation structure (7, end portion trench) is formed in an annular shape (8, guard trench, [0074]) having an inner peripheral wall (annotated Figure 3) and an outer peripheral wall (annotated Figure 3) as viewed in plan (Figs. 12A/12B) and demarcates the outer region and the active region (22, voltage withstanding structure) in the main surface (1, n-type semiconductor substrate) by the inner peripheral wall (annotated Figure 3), and
the floating region (10, p-type floating layer) is formed along the outer peripheral wall (annotated Figure 3) of the trench separation structure (7, end portion trench) in the outer region (22, voltage withstanding structure).
Regarding Claim 8, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 7.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the floating region (10, p-type floating layer) surrounds the trench separation structure (7, end portion trench) as viewed in plan (Figs. 12A/12B).
Regarding Claim 9, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the Schottky electrode (3, anode electrode, [0062]) is connected to a portion of the separation electrode (13, polysilicon) on the active region side (21, active portion) in the separation electrode (13, polysilicon) such as to expose a portion (annotated Figure 3) of the separation electrode (13, polysilicon) on the outer region side (22, voltage withstanding structure).
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Regarding Claim 13, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
QUDDUS further teaches the semiconductor device (Fig. 1, 10A, an electronic device, semiconductor device, Schottky diode device, or trench Schottky rectifier, [0020]), wherein
the main surface (Fig. 5, 14, semiconductor layer) insulating film (Fig. 5, 219, dielectric layer) covers a portion of the separation electrode (Fig. 5, 217, conductivity type of conductivity material (same as 237, a gate electrode), [0034]) on the outer region side (Fig. 5, 100E, termination structure) such as to expose a portion of the separation electrode on the active region side (Fig. 5, 103 active portion, annotated Figure 5).
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Regarding Claim 14, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
QUDDUS teaches the semiconductor device (Fig. 1, 10A, an electronic device, semiconductor device, Schottky diode device, or trench Schottky rectifier, [0020]), wherein
the main surface (Fig. 5, 14, semiconductor layer) insulating film (Fig. 5, 219, dielectric layer has a wall portion (Fig. 5, 219A, edge) which demarcates a through hole (annotated Figure 5) for exposing the active region (Fig. 5, 103 active portion) on the separation electrode (Fig. 5, 217, conductivity type of conductivity material (same as 237, a gate electrode), [0034]), and
the Schottky electrode (Fig. 5, 440, anode electrode) is electrically connected to the main surface and the separation electrode inside the through hole (annotated Figure 5).
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Regarding Claim 17, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), further comprising:
a trench structure (annotated Figure 1) which includes a trench (annotated Figure 1) that is formed in the main surface (1, n-type semiconductor substrate), an insulating film (11, oxide film) that covers a wall surface of the trench (annotated Figure 1) and an electrode (annotated Figure 1) that is embedded in the trench (annotated Figure 1) across the insulating film (11, oxide film), the trench structure (annotated Figure 1) and forming at an interval (annotated Figure 1) on the main surface (1, n-type semiconductor substrate) in the active region (21, active portion);
wherein the Schottky electrode (3, anode electrode, [0062]) is electrically connected (annotated Figure 3) to the electrode (annotated Figure 3) in the active region (21, active portion) and forms the Schottky junction 16, Schottky barrier junction) with the main surface (1, n-type semiconductor substrate).
Regarding Claim 18, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 17.
QUDDUS teaches the semiconductor device (Fig. 1, 10A, an electronic device, semiconductor device, Schottky diode device, or trench Schottky rectifier, [0020]), further comprising:
a protrusion portion (annotated Figure 5) which is constituted of an upper end portion (Fig. 5, 219A, edge) of the insulating film (Fig. 5, 219, dielectric layer) and protrudes as a wall from the main surface (Fig. 5, 14, semiconductor layer) such as to separate the electrode (Fig. 5, 217, conductivity type of conductivity material (same as 237, a gate electrode), [0034]) and the main surface.
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Regarding Claim 19, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 17.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the trench separation structure (7, end portion trench) is formed wider (W1<W2, [0074]) than the trench structure (annotated Figure 1).
Regarding Claim 20, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 17.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein
the trench structure (annotated Figure 1) is connected to the trench separation structure (7, end portion trench).
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Claim(s) 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIZUSHIMA, in view of QUDDUS, and SUGIURA as applied to claim(s) 1-9, and 13-14, 17-20 above, and further in view of SDRULLA (prior art used in the previous OA filed 10/09/2025).
Regarding Claim 10, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA further teaches in Figure 3, the semiconductor device (TMBS diode, [0060]), wherein the main surface (1, n-type semiconductor substrate) inside the active region (21, active portion).
MIZUSHIMA as modified by QUDDUS and SUGIURA fails to teach the semiconductor device, wherein the main surface inside the active region is depressed in a thickness direction with respect to the main surface inside the outer region side.
SDRULLA teaches in Figures 1.7-1.8, the semiconductor device (TVS devices, [0009]) wherein
the main surface (2, epitaxial layer) inside the active region (100, active area) is depressed in a thickness direction (annotated Figure 1.8) with respect to the main surface (2, epitaxial layer) inside the outer region side (101, termination).
Therefore, it would have been a prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MIZUSHIMA as modified by QUDDUS and SUGIURA to incorporate teachings of SDRULLA such that the semiconductor device, wherein the main surface inside the active region is depressed in a thickness direction with respect to the main surface inside the outer region side, so that the semiconductor device for example, SiC TVS structure, enables the fundamental requirement to create a significant termination region (higher breakdown in the termination) and of the active area (lower breakdown by a significant margin in the active area) (SDRULLA, [0030]).
Regarding Claim 11, MIZUSHIMA as modified by QUDDUS, SUGIURA and SDRULLA teaches the semiconductor device according to Claim 10.
SDRULLA further teaches in Figures 1.7-1.8, the semiconductor device (TVS devices, [0009]) according to Claim 10, wherein
the trench separation structure (5, trenches) includes a first portion (annotated Figure 1.8) which is positioned on the outer region side (Fig. 1.8, 101, termination) and a second portion (annotated Figure 1.8) which is positioned on the active region side (Fig. 1.8, 100, active area) and depressed in a thickness direction (annotated Figure 1.8) of the semiconductor layer (Figure 1) with respect to the first portion (annotated Figure 1.8), and
the trench separation structure (5, trenches) demarcates a contact opening which is depressed (annotated Figure 1.8) from the main surface (2, epitaxial layer) inside the outer region (101, termination) in the thickness direction (annotated Figure 1.8) of the semiconductor layer (Figure 1), with the main surface (2, epitaxial layer) inside the active region (Fig. 1.8, 100, active area).
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Claim(s) 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIZUSHIMA, in view of QUDDUS, and SUGIURA as applied to claim(s) 1-9, and 13-14, 17-20 above, and further in view of YEDINAK (prior art used in the previous OA filed 10/09/2025).
Regarding Claim 15, MIZUSHIMA as modified by QUDDUS and SUGIURA teaches the semiconductor according to Claim 1.
MIZUSHIMA as modified by QUDDUS and SUGIURA does not explicitly disclose the semiconductor, wherein the Schottky electrode has a lead-out portion which is led out insulating film and faces a part of the separation electrode and the floating region across the main surface insulating film.
YEDINAK teaches in Figure 32, the semiconductor device (Figures, 32-34, 100″, Schottky barrier diode), wherein
the Schottky electrode (Fig. 6, 224, shield electrode (in other Schottky embodiments, gate electrodes, 126, and 226 along with the gate runners, [0056]) has a lead-out portion which is led out (Fig. 6, 110, source metal layer) on the main surface (Fig. 6, 104, n-type epitaxial layer) insulating film (Fig. 6, 107, dielectric layer) from the active region (Fig. 6, 120, device region) and faces a part of the separation electrode (Fig. 6, 224, shield electrode (in other Schottky embodiments, gate electrodes, 126, and 226 along with the gate runners, [0056]) and the floating region (Fig. 6, 239′, P-type region) across the main surface (Fig. 6, 104, n-type epitaxial layer) insulating film (Fig. 6, 107, dielectric layer).
Therefore, it would have been a prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MIZUSHIMA as modified by QUDDUS and SUGIURA to incorporate teachings of YEDINAK such that the semiconductor device, wherein the Schottky electrode has a lead-out portion which is led out insulating film and faces a part of the separation electrode and the floating region across the main surface insulating film. The above arrangement is thus enable, the p-type region (239) may be directly decoupled from any potential, and left in a floating state, or may be electrically coupled to the source metal layer (110) and the source potential (e.g., it may be grounded). In either case, region (239) reduces the electric fields around the top right corner of broad mesa (238), to eliminate this area as a source of parasitic breakdown mechanism (YEDINAK, [0034]).
Regarding Claim 16, MIZUSHIMA as modified by QUDDUS, SUGIURA and YEDINAK teaches the semiconductor device according to Claim 15.
YEDINAK further teaches in Figure 32, the semiconductor device (Figures, 32-34, 100″, Schottky barrier diode), wherein
the lead-out portion (Fig. 6, 110, source metal layer) faces an entire area of the floating region (Fig. 6, 239′, P-type region/first field termination region) across the main surface (Fig. 6, 104, n-type epitaxial layer) insulating film (Fig. 6, 107, dielectric layer).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIZUSHIMA, in view of QUDDUS, and SUGIURA as applied to claim(s) 1-9, and 13-14, 17-20 above, and further in view of WERBER (prior art used in the previous OA filed 10/09/2025).
Regarding Claim 21, MIZUSHIMA as modified by QUDDUS, and SUGIURA teaches the semiconductor device according to Claim 1.
MIZUSHIMA as modified by QUDDUS, and SUGIURA does not explicitly teaches the semiconductor device, wherein the upper insulating film overlaps the trench separation structure and the floating region in plan view.
WERBER teaches in Figure 5B, the semiconductor device (Fig. 1, 10), wherein the upper insulating film (Fig. 5B, 205, dielectric liner) overlaps the trench separation structure (Fig. 5B, 210, electrode structure) and the floating region (Fig. 5B, 115/119, (body zones/floating zones) in plan view ([0014]).
Therefore, it would have been a prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MIZUSHIMA as modified by QUDDUS and SUGIURA to incorporate teachings of WERBER such that the semiconductor device, , wherein the upper insulating film overlaps the trench separation structure and the floating region in plan view, so that the IGBT cell, (420a) and a body zone (115) are formed in the semiconductor body (100) within a ring-shaped buried electrode structure (210) and facilitated the formation of p-n junction for enabling an adequate device performance with respect to low switching losses (WERBER, [0002], [0055]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 8912621 B1 – Figure 6
STATEMENT OF RELEVANCE – Flow diagram illustrating a method as in cell region 120, metal layer 130 and semiconductor layer 114 between trenches 116 may form a Schottky diode (such as a trench Schottky diode).
US 20180315749 A1 – Figure 2A
STATEMENT OF RELEVANCE – A cross-sectional schematic diagram of portions of a trench MOSFET device, a Schottky diode is formed at the contact between the lightly doped source region (240) and the source contact (272).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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