DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 28, 2025 has been entered.
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on March 11, 2026 was considered by the Examiner.
Response to Arguments
RE: the rejection of claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new ground of rejection presented herein. Note the current US20200152595A1 (“Fuijita”) reference is newly cited.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-12, 16, 21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over US6320268B1 to Lang et al. (hereinafter “Lang”) and further in view of US20200152595A1 to Fujita et al. (hereinafter “Fujita”).
RE: Claim 1, Lang discloses A semiconductor device (FIG. 1), comprising:
a housing (2, 3, Col. 3, lines 1-5) comprising a first housing electrode (3) and a second housing electrode (2) which are arranged at opposite sides of the housing, wherein the first housing electrode and the second housing electrode are separated in a first direction (vertical direction; FIG. 1 shows electrodes 2 and 3 are separated in the vertical direction);
a plurality of semiconductor units (4, Col. 3, line 7) arranged within the housing between the first and second housing electrodes;
a plurality of pressure applicators (spring elements 7, Col. 3, lines 23-25) configured to apply pressure to the plurality of semiconductor units, wherein the plurality of pressure applicators are arranged between the plurality of semiconductor units and the first housing electrode (spring elements 7 are between 3 and 4 in FIG. 1);
a first conductive structure (11 and/or 6; 11 is conductive as it electrically connects chips to one another; 6 is considered conductive as discussed below; Col. 4, lines 24-25; compensation film 11 connects the second main electrodes 41 on the semiconductor chips 4 to one another electrically and mechanically, Col. 5, lines 10-15) arranged between the plurality of pressure applicators and the plurality of semiconductor units (11 is between 7 and 4 in FIG. 1; bottom portion of 6 in FIG. 1 is between 7 and 4), wherein the plurality of semiconductor units are electrically connected in parallel between the second housing electrode and the first conductive structure (FIG. 1 shows chips 4 are electrically connected in parallel); and
a second conductive structure (8 including 80, 81, 82, Col. 3, lines 8-11, Col. 3, lines 19-30, Col. 3, lines 39-42) configured to provide a current flow path from the first conductive structure to the first housing electrode (The second main electrode 41 of each semiconductor chip is electrically connected via a contact element 8 to the cover plate 3, Col. 3, lines 8-11), the second conductive structure comprising a first part (81, Col. 3, line 23) that is fixedly connected to the first conductive structure (81 is fixedly connected to 6, 11 in FIG. 1 by pressure since the spring 7 would clamp 81 onto 6, 11 and therefore fix 81 onto 6, 11 since spring element 7 is compressed when clamped and the spring would provide a counteracting clamping force to 81 and 82; The spring element 7 is further compressed while the module is being clamped in, to be precise at most until the cover plate 3 rests on the supporting elements 10, Col. 4, lines 5-10) and a second part (82, Col. 3, line 27) that is fixedly connected to the first housing electrode (82 is fixedly connected to 3 by pressure since the spring 7 would clamp 82 onto 3 and therefore fix 82 onto 3 since spring element 7 is compressed when clamped and the spring would provide a counteracting clamping force to 81 and 82).
Lang does not explicitly disclose that the stamp 6 is conductive.
However, Lang discloses that The second main electrode 41 of each semiconductor chip is electrically connected via a contact element 8 to the cover plate 3, Col. 3, lines 8-11.
Lang further discloses second main electrodes of the chips make electrical contact with a plurality of contact stamps, Col. 1, lines 13-17.
Accordingly, the stamp 6 is considered at least partially conductive since if stamp 6 was instead electrically insulating, the contact element 8 would be electrically insulated from the second main electrode 41 of each semiconductor chip, because the bottom portion of stamp 6 is between the contact element 8 and the second main electrode 41, and this would prevent the second main electrode 41 from being electrically connected to the cover plate 3 via the contact element 8. Therefore, stamp 6 is understood to be at least partially electrically conductive so that the second main electrode 41 of each semiconductor chip is electrically connected via a contact element 8 to the cover plate 3 as taught by Lang.
Lang does not explicitly disclose that the second conductive structure (8 including 80, 81, 82) comprises a tubular conductive structure arranged within the housing, and
wherein the tubular conductive structure surrounds the plurality of pressure applicators in a plane that is perpendicular to the first direction.
However, Lang discloses The spring element 7 may be a spiral spring, may comprise one or more plate springs, or may be manufactured as a cylinder composed of an elastic material, Col. 5, lines 1-5.
Lang further discloses Since the distance between the two contact surfaces 81, 82 of the contact element 8 no longer changes once the module has been clamped in, it must be bridged by a flexible conductive connecting element 80, Col. 3, lines 39-42. Lang teaches The connecting element 80 according to the invention is used exclusively for electrical conduction, Col. 3, lines 45-49.
Each contact element is spread by a spring element. In this case, contact surfaces are pressed on the one hand against the cover plate and on the other hand onto the semiconductor chip, thus allowing a low contact resistance, Col. 1, lines 60-65.
In the same field of endeavor, Fujita discloses:
FIG. 2 is a configuration diagram of a spring electrode 101 according to a first embodiment. The spring electrode 101 is a spring electrode for a press-pack power semiconductor module, and includes a lower electrode 11, an upper electrode 12, and pressure pads 13, [0035].
Fujita further discloses The pressure pads 13 have flexibility in the normal direction of the opposing surfaces of the lower electrode 11 and the upper electrode 12. Therefore, the distance between the lower electrode 11 and the upper electrode 12 decreases as the pressure pads 13 bend, [0036].
Fujita further discloses the pressure pad is a cylindrical conductor having a cylindrical axis in the normal direction of the opposing surfaces of the first electrode and the second electrode, [0013]. The upper electrode and the lower electrode are arranged to face each other with the cylindrical conductor 14 interposed therebetween and are connected by the cylindrical conductor 14, [0045].
Further, FIG. 1 shows an upper electrode 5 and a lower electrode 3 are separated in a vertical direction, [0033].
Fujita further discloses Although not shown in FIG. 3, the upper end of the cylindrical conductor 14 is in contact with an upper electrode, and the lower end is in contact with a lower electrode, [0044]. A power semiconductor chip is bonded to either the upper electrode or the lower electrode, [0046].
Fujita further discloses the cylindrical conductor 14 is thin enough to be flexible with respect to the pressure contact in the cylindrical axial direction, and functions as a pressure pad in the press-pack semiconductor module, [0047].
Fujita further discloses The internal spring 19 is inserted into the cylindrical conductor 14. That is, the spring electrode 108 is obtained by inserting the internal spring 19 into the internal space surrounded by the lower electrode, the upper electrode, and the cylindrical conductor 14 in the spring electrode 102, [0072].
By arranging the internal spring 19 in the cylindrical conductor 14, the flexibility of the spring electrode 108 can be enhanced. One or more internal springs 19 may be used, [0074].
FIG. 11 shows the cylindrical conductor surrounding the spring electrode 108 in a horizontal plane that is perpendicular to the vertical direction.
Fujita further discloses The surface of the cylindrical conductor 14 is divided into a plurality of divided regions 14 a by slits 15. The short-circuit current generated when the power semiconductor chip is short-circuited branches into the divided regions 14 a and flows between the upper electrode and the lower electrode. Here, the short-circuit current flowing through one divided region 14 a becomes smaller correspondingly to the number of divided regions 14 a, that is, the number of slits 15. Therefore, heat generation in the divided regions 14 a is suppressed, and the electromagnetic attractive force generated between the divided regions 14 a is reduced, [0048].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each flexible conductive connecting element 80 to surround a respective spring element 7 in a horizontal plane as taught by Fujita in order to suppress heat generation and/or improve flexibility.
Note the word “tubular” is not defined in the instant specification. The word “tubular” is defined as “made or provided with tubes,” see definition 1b by Merriam-Webster.
As a result, each spring 7 would be surrounded by a modified connecting element 80 included in a contact element 8 which also includes 81, 82; each modified contact element 8 would be considered a tubular / cylindrical conductive element arranged within the housing that surrounds a spring 7. Under a broad reasonable interpretation, the combination of modified contact elements 8 is therefore considered to be a tubular conductive structure that surrounds the plurality of springs 7.
RE: Claim 2, modified Lang discloses A semiconductor device according to claim 1, wherein the plurality of semiconductor units are electrically and thermally coupled to one another via the first conductive structure (A compensation film 11, which is shown only in FIG. 1, connects the second main electrodes 41 on the semiconductor chips 4 to one another electrically and mechanically, Col. 5, lines 10-15; the chips 4 are thermally coupled through the compensation film 11, the stamps 6 and the intermediate layers 5).
RE: Claim 3, modified Lang discloses A semiconductor device according to claim 1, wherein the first conductive structure (11) is a unitary one-piece structure ( a unitary one-piece film 11 is shown in FIG. 1; alternatively, a unitary one-piece stamp 6 is shown in FIG. 1).
RE: Claim 4, modified Lang discloses A semiconductor device according to claim 1, wherein the first conductive structure (6) comprises a base plate (top portion of 6, labelled as 62 in FIG. 2) and a plurality of pillars (narrower portions between the tops and bottoms of 6, labelled as 61 in FIG. 2), and wherein the base plate comprises a first surface facing the plurality of semiconductor units (top portion of 6 has a bottom surface facing the chips 4) and a second surface (top surface of top portion of 6) opposite to the first surface, and the plurality of pillars extend from the first surface of the base plate (narrower portion of 6 extends from the bottom surface of top portion of 6), and are electrically coupled to the plurality of semiconductor units, respectively (6 is considered electrically conductive as discussed above for claim 1 and would therefore be electrically coupled to 4).
RE: Claim 5, modified Lang discloses A semiconductor device according to claim 1, wherein at least one of the plurality of pressure applicators are elastic (The spring element 7 may be a spiral spring, may comprise one or more plate springs, or may be manufactured as a cylinder composed of an elastic material, Col. 5, lines 1-3).
RE: Claim 6, modified Lang discloses A semiconductor device according to claim 1, wherein the plurality of pressure applicators are configured to apply pressure to the plurality of semiconductor units when the plurality of pressure applicators are compressed between the first housing electrode and the first conductive structure (The contact force transmitted by the stressed spring element 7 to the semiconductor chips 4 and the cover plate 3 is compensated for by the pressure which is exerted on the main connecting surfaces 20, 30 of the module when it is clamped in, Col. 3, lines 34-38; 20 and 30 are from 2 and 3, Col. 3, lines 1-5; spring element 7 is a module which is expanded more before being fitted, that is to say it is less stressed, than once it has been clamped in, Col. 3, lines 42-45).
RE: Claim 7, modified Lang discloses A semiconductor device according to claim 1, wherein at least one of the plurality of pressure applicators comprises a spring (7 is a spring element, Col. 5, lines 1-3).
RE: Claim 8, modified Lang discloses A semiconductor device according to claim 1, further comprising a plurality of holders (90 labelled in FIG. 2 and shown in FIG. 1) for keeping the plurality of pressure applicators in place within the housing (O-ring 90 is underneath, which is placed between the stamp head 62 and the second contact surface 82, Col. 4, lines 31-34; the O-ring 90 prevents the unloaded spring element 7 from expanding beyond the stamp head 62, Col. 4, lines 39-42).
RE: Claim 9, modified Lang discloses A semiconductor device according to claim 8, wherein the first conductive structure comprises a plurality of recesses (91, 92 in FIG. 1, Col. 4, lines 58-62) for engaging with the plurality of holders, respectively (91, 92 are shown partially defined by 82 in FIG. 1; an O-ring 90 underneath, which is placed between the stamp head 62 and the second contact surface 82, Col. 4, lines 31-33; in FIG. 1, 82 is shown engaging with O-ring 90).
RE: Claim 10 modified Lang discloses A semiconductor device according to claim 9, wherein the plurality of pressure applicators are configured to apply pressure to the plurality of semiconductor units when the plurality of recesses engage with the plurality of holders, respectively (FIG. 1 shows O-rings 90 resting on 82; The contact force transmitted by the stressed spring element 7 to the semiconductor chips 4 and the cover plate 3 is compensated for by the pressure which is exerted on the main connecting surfaces 20, 30 of the module when it is clamped in, Col. 3, lines 34-38; spring element 7 is a module which is expanded more before being fitted, that is to say it is less stressed, than once it has been clamped in, Col. 3, lines 42-45; as the O-rings 90 are resting on 82 in FIG. 1, O-rings 90 would continue to rest on 82 as 3 is compressed toward 2).
RE: Claim 11, modified Lang discloses A semiconductor device according to claim 1, wherein the pressure applicators are configured to apply maximum pressure to the plurality of semiconductor units when the first housing electrode is pressed flat by an external clamping system (Supporting elements 10 are provided in order to protect the semiconductor chips 4 against unacceptable mechanical loads and mechanical overloading. Specifically, if the pressure on the main connecting surfaces 20, 30 becomes excessive when the module is being clamped in a stack, the pressure can be absorbed by the supporting elements 10, Col. 3 line 66 to Col. 4 line 5; accordingly, there is maximum pressure exerted on the chips 4 when the module is clamped, beyond this maximum pressure there is an excessive pressure that would be absorbed by 10).
RE: Claim 12, modified Lang discloses A semiconductor device according to claim 11, wherein the housing further comprises a tubular housing element (10, Col. 3, line 66) arranged between the first and second housing electrodes and surrounding the plurality of semiconductor units, wherein the tubular housing element is configured to electrically isolate the first and second housing electrodes from one another (10 is composed of ceramic; Note the reference US 20200098673 A1 discloses The substrate 32a is constituted of an insulator such as, for example, glass or ceramic, and electrically isolates the plurality of signal transmission paths 32b from the first conductor plate 22, [0049]; Accordingly in Lang, ceramic 10 would electrically isolate 2 from 3 to prevent a short circuit between 2 and 3, Col. 3, line 66); and wherein the tubular housing element is configured such that, once the first housing electrode is pressed flat by the external clamping system, further mechanical loading provided by the external clamping system is applied to the tubular housing element (Supporting elements 10 composed of ceramic are provided in order to protect the semiconductor chips 4 against unacceptable mechanical loads and mechanical overloading. Specifically, if the pressure on the main connecting surfaces 20, 30 becomes excessive when the module is being clamped in a stack, the pressure can be absorbed by the supporting elements 10, Col. 3 line 66 to Col. 4 line 5; accordingly, there is maximum pressure exerted on the chips 4 when the module is clamped, beyond this maximum pressure is an excessive pressure that would be absorbed by 10; The supporting element 10 may be in the form of individual posts or in the form of a supporting ring in the interior of the module, or may be identical to the casing wall, Col. 4, lines 11-12).
RE: Claim 16, modified Lang discloses A semiconductor device according to claim 1, wherein at least a part of a wall of the tubular conductive structure has a curved contour along a direction parallel to a central axis of the tubular conductive structure (In FIG. 1, 8 has a vertical contour along a direction parallel to a vertical central axis of 8, modified 8 would continue to have this vertical contour; Alternatively, FIG. 11 Fujita shows cylindrical conductor 14 has a curved contour along a horizontal direction parallel to a horizontal central axis of 14; Accordingly modified 8 would have a curved contour along a horizontal direction parallel to a horizontal central axis of 8).
RE: Claim 21, modified Lang discloses A semiconductor device according to claim 1, wherein: the housing further comprises a tubular housing element (10, Col. 3, line 66) arranged between the first and second housing electrodes and surrounding the plurality of semiconductor units, wherein the tubular housing element is configured to electrically isolate the first and second housing electrodes from one another (10 is composed of ceramic; Note the reference US 20200098673 A1 discloses The substrate 32a is constituted of an insulator such as, for example, glass or ceramic, and electrically isolates the plurality of signal transmission paths 32b from the first conductor plate 22, [0049]; Accordingly in Lang, ceramic 10 would electrically isolate 2 from 3 to prevent a short circuit between 2 and 3, Col. 3, line 66); and the tubular conductive structure is attached to an inner surface of the tubular housing element (if the pressure on the main connecting surfaces 20, 30 becomes excessive when the module is being clamped in a stack, the pressure can be absorbed by the supporting elements 10, Col. 4, lines 3-6; therefore, when the module is clamped, 10 would be clamped and pressed between 3 and 4 and would therefore be attached to 3; as discussed above for claim 1, 82 of 8 is fixedly connected to and therefore attached to 3; accordingly, 82, 80 which is part of 8 is attached to 10 and therefore attached to an inner surface of 10).
RE: Claim 24, Lang discloses A method of manufacturing a semiconductor device (FIGs. 1-2), comprising:
providing a housing (2, 3, Col. 3, lines 1-5), wherein the housing comprises a first housing electrode (3) and a second housing electrode (2) which are arranged at opposite sides of the housing,
arranging a plurality of semiconductor units (4, Col. 3, line 7) within the housing between the first and second housing electrodes, wherein the first housing electrode and the second housing electrode are separated in a first direction (vertical direction; FIG. 1 shows electrodes 2 and 3 are separated in the vertical direction);
providing a plurality of pressure applicators (7, Col. 3, lines 23-25) configured to apply pressure to the plurality of semiconductor units, wherein the plurality of pressure applicators are arranged between the plurality of semiconductor units and the first housing electrode (spring elements 7 are between 3 and 4 in FIG. 1);
arranging a first conductive structure (11 and/or 6; 11 is conductive as it electrically connects chips to one another; 6 is considered conductive as discussed below; Col. 4, lines 24-25; compensation film 11 connects the second main electrodes 41 on the semiconductor chips 4 to one another electrically and mechanically, Col. 5, lines 10-15; Col. 5, line 10-15) between the plurality of pressure applicators and the plurality of semiconductor units (11 is between 7 and 4 in FIG. 1; bottom portion of 6 in FIG. 1 is between 7 and 4), wherein the plurality of semiconductor units are electrically connected in parallel between the second housing electrode and the first conductive structure (FIG. 1 shows chips 4 are electrically connected in parallel); and
providing a second conductive structure (8 including 80, 81, 82, Col. 3, lines 8-11, Col. 3, lines 19-30, Col. 3, lines 39-42) for providing a current flow path from the first conductive structure to the first housing electrode (The second main electrode 41 of each semiconductor chip is electrically connected via a contact element 8 to the cover plate 3, Col. 3, lines 8-11), the second conductive structure comprising a first part (81, Col. 3, line 23) that is fixedly connected to the first conductive structure (81 is fixedly connected to 11 in FIG. 1 by pressure since the spring 7 would clamp 81 onto 11 and therefore fix 81 onto 11 since spring element 7 is compressed when clamped and the spring would provide a counteracting clamping force to 81 and 82; The spring element 7 is further compressed while the module is being clamped in, to be precise at most until the cover plate 3 rests on the supporting elements 10, Col. 4, lines 5-10) and a second part (82, Col. 3, line 27) that is fixedly connected to the first housing electrode (82 is fixedly connected to 3 by pressure since the spring 7 would clamp 82 onto 3 and therefore fix 82 onto 3 since spring element 7 is compressed when clamped and the spring would provide a counteracting clamping force to 81 and 82).
Lang does not explicitly disclose that the stamp 6 is conductive.
However, Lang discloses that The second main electrode 41 of each semiconductor chip is electrically connected via a contact element 8 to the cover plate 3, Col. 3, lines 8-11.
Lang further discloses second main electrodes of the chips make electrical contact with a plurality of contact stamps, Col. 1, lines 13-17.
Accordingly, the stamp 6 is considered at least partially conductive since if stamp 6 was instead electrically insulating, the contact element 8 would be electrically insulated from the second main electrode 41 of each semiconductor chip, because the bottom portion of stamp 6 is between the contact element 8 and the second main electrode 41, and this would prevent the second main electrode 41 from being electrically connected to the cover plate 3 via the contact element 8. Therefore, stamp 6 is understood to be at least partially electrically conductive so that the second main electrode 41 of each semiconductor chip is electrically connected via a contact element 8 to the cover plate 3 as taught by Lang.
Lang does not explicitly disclose that the second conductive structure (8 including 80, 81, 82) comprises a tubular conductive structure arranged within the housing, and
wherein the tubular conductive structure surrounds the plurality of pressure applicators in a plane that is perpendicular to the first direction.
However, Lang discloses The spring element 7 may be a spiral spring, may comprise one or more plate springs, or may be manufactured as a cylinder composed of an elastic material, Col. 5, lines 1-5.
Lang further discloses Since the distance between the two contact surfaces 81, 82 of the contact element 8 no longer changes once the module has been clamped in, it must be bridged by a flexible conductive connecting element 80, Col. 3, lines 39-42. Lang teaches The connecting element 80 according to the invention is used exclusively for electrical conduction, Col. 3, lines 45-49.
Each contact element is spread by a spring element. In this case, contact surfaces are pressed on the one hand against the cover plate and on the other hand onto the semiconductor chip, thus allowing a low contact resistance, Col. 1, lines 60-65.
In the same field of endeavor, Fujita discloses:
FIG. 2 is a configuration diagram of a spring electrode 101 according to a first embodiment. The spring electrode 101 is a spring electrode for a press-pack power semiconductor module, and includes a lower electrode 11, an upper electrode 12, and pressure pads 13, [0035].
Fujita further discloses The pressure pads 13 have flexibility in the normal direction of the opposing surfaces of the lower electrode 11 and the upper electrode 12. Therefore, the distance between the lower electrode 11 and the upper electrode 12 decreases as the pressure pads 13 bend, [0036].
Fujita further discloses the pressure pad is a cylindrical conductor having a cylindrical axis in the normal direction of the opposing surfaces of the first electrode and the second electrode, [0013]. The upper electrode and the lower electrode are arranged to face each other with the cylindrical conductor 14 interposed therebetween and are connected by the cylindrical conductor 14, [0045].
Further, FIG. 1 shows an upper electrode 5 and a lower electrode 3 are separated in a vertical direction, [0033].
Fujita further discloses Although not shown in FIG. 3, the upper end of the cylindrical conductor 14 is in contact with an upper electrode, and the lower end is in contact with a lower electrode, [0044]. A power semiconductor chip is bonded to either the upper electrode or the lower electrode, [0046].
Fujita further discloses the cylindrical conductor 14 is thin enough to be flexible with respect to the pressure contact in the cylindrical axial direction, and functions as a pressure pad in the press-pack semiconductor module, [0047].
Fujita further discloses The internal spring 19 is inserted into the cylindrical conductor 14. That is, the spring electrode 108 is obtained by inserting the internal spring 19 into the internal space surrounded by the lower electrode, the upper electrode, and the cylindrical conductor 14 in the spring electrode 102, [0072].
By arranging the internal spring 19 in the cylindrical conductor 14, the flexibility of the spring electrode 108 can be enhanced. One or more internal springs 19 may be used, [0074].
FIG. 11 shows the cylindrical conductor surrounding the spring electrode 108 in a horizontal plane that is perpendicular to the vertical direction.
Fujita further discloses The surface of the cylindrical conductor 14 is divided into a plurality of divided regions 14 a by slits 15. The short-circuit current generated when the power semiconductor chip is short-circuited branches into the divided regions 14 a and flows between the upper electrode and the lower electrode. Here, the short-circuit current flowing through one divided region 14 a becomes smaller correspondingly to the number of divided regions 14 a, that is, the number of slits 15. Therefore, heat generation in the divided regions 14 a is suppressed, and the electromagnetic attractive force generated between the divided regions 14 a is reduced, [0048].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each flexible conductive connecting element 80 to surround a respective spring element 7 in a horizontal plane as taught by Fujita in order to suppress heat generation and/or improve flexibility.
Note the word “tubular” is not defined in the instant specification. The word “tubular” is defined as “made or provided with tubes,” see definition 1b by Merriam-Webster.
As a result, each spring 7 would be surrounded by a modified connecting element 80 included in a contact element 8 which also includes 81, 82; each modified contact element 8 would be considered a tubular /cylindrical conductive element arranged within the housing that surrounds a spring 7. Under a broad reasonable interpretation, the combination of modified contact elements 8 is therefore considered to be a tubular conductive structure that surrounds the plurality of springs 7.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lang in view of Fujita as applied to claim 1 and further in view US 9780492 B1 to Wang et al. (hereinafter “Wang”).
RE: Claim 15, modified Lang does not explicitly disclose A semiconductor device according to claim 1, wherein the tubular conductive structure comprises a wall, and a thickness of the wall is between 0.1mm and 0.5mm.
However, Lang discloses In order to keep the contact resistance between the second main electrode 41 of a semiconductor chip 4 and the contact element 8 low, the latter comprises a first planar contact surface 81, Col. 3, lines 19-24.
In a similar field of endeavor, Wang discloses The upper grounding terminal assembly 31, the upper power terminal assembly 32, the lower grounding terminal assembly 41, and the lower power terminal assembly 42 are provided with contact sections 7. Each of the contact sections 7 is located at one side of each of the extension sections 6 that is opposite to each of the soldering sections 5. Each of the contact sections 7 has a width between 0.285 mm and 0.295 mm, a preferable width being 0.29 mm. Each of the contact sections 7 has a thickness between 0.1 mm and 0.2 mm, a preferable thickness being 0.15 mm, Col. 3, lines 19-28.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the thickness of the contact surface 81 of contact element between 0.1mm and 0.2mmm as taught by Wang to satisfy the need for a large electrical current and prevent noise interference (Wang, Col. 1 line 65 to Col. 2 line 2).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lang in view of Fujita as applied to claim 1 and further in view of US20130119427A1 to Zhang et al. (hereinafter “Zhang”).
RE: Claim 17, modified Lang does not explicitly disclose A semiconductor device according to claim 1, wherein the tubular conductive structure is formed integrally with the first conductive structure.
However, in a similar field of endeavor, Zhang discloses The part of the conductive structure formed on the first surface and the part of the conductive structure formed on the second surface may be integrally formed to electrically connect with each other, [0028].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form contact element 8 or contact surface 81 of 8 integrally with compensation film 11 as both 8 and 11 are conductive in order to avoid contact resistance between 8 and 11.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lang in view of Fujita as applied to claim 1 and further in view of US 20180090401 A1 to Mohn et al. (hereinafter “Mohn”).
RE: Claim 19, modified Lang discloses A semiconductor device according to claim 1, wherein the housing further comprises a tubular housing element (10, Col. 3, line 66) arranged between the first and second housing electrodes and surrounding the plurality of semiconductor units, wherein the tubular housing element is configured to electrically isolate the first and second housing electrodes from one another (10 is composed of ceramic; Note the reference US 20200098673 A1 discloses The substrate 32a is constituted of an insulator such as, for example, glass or ceramic, and electrically isolates the plurality of signal transmission paths 32b from the first conductor plate 22, [0049]; Accordingly in Lang, ceramic 10 would electrically isolate 2 from 3 to prevent a short circuit between 2 and 3, Col. 3, line 66).
Modified Lang does not explicitly disclose wherein the housing further comprises a first flange connecting the first housing electrode to the tubular housing element, and a second flange connecting the second housing electrode to the tubular housing element.
However, in the same field of endeavor, Mohn discloses The electrodes 12a, 12b comprise thin flexible flanges 22 (which may be also made of copper), which extend in a radial direction from the electrodes 12a, 12b and/or which surround the contact faces 14 in the form of a ring, [0045].
Mohn further discloses Each of the electrodes may comprise a massive, circular body, which has ring-shaped flanges on each side, which are used for attaching the outer insulating ring, [0031].
Mohn further discloses an An outer insulating ring 24 of ceramics is attached to the flanges 22, [0046].
FIG. 1 shows an upper flange 22 attaching the electrode 12a to the outer insulating ring 24, and a lower flange attaching the electrode 12b to the outer insulating ring 24, [0046].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach the first housing electrode 3 to the tubular housing element 10 with a first upper flange, and to attach the second housing electrode 2 to the tubular housing element 10 with a second lower flange as taught by Mohn to restrain 10 and prevent its lateral movement relative to the first and second housing electrodes 2, 3.
RE: Claim 20, modified Lang discloses A semiconductor device according to claim 19, wherein the second conductive structure further comprises the first flange (upper flange as discussed above for claim 19), and the first flange is fixedly connected to the tubular conductive structure (the first flange attaches 10 to 3 and therefore the first flange would be fixedly connected to the upper electrode 3 and as discussed above for claim 1, 82 is fixedly connected to 3, therefore, the upper flange would be fixedly connected to 82 which is part of 8), and wherein the tubular conductive structure comprises the first part (81), and the first flange comprises the second part (the upper flange is fixedly connected to 3 therefore the claimed second part is considered to correspond to the combination of the upper flange and 82; Accordingly, the upper flange would comprise a portion of the second part).
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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