DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant replied on 13 Nov 2025 in response to the previous office action, which was a non-final rejection dated 24 July 2025, with the following amendments:
Specification
Replacement for ¶[0005] to correct a minor informality
Replacement for ¶[0038] in response to examiner’s objection
Drawings
Replacement sheet containing Fig. 3 in response to examiner’s objection
Claims
Claims 14 and 24 have been cancelled
Claims 2, 3, 5, and 26 have been amended to correct minor informalities in response to examiner’s objections
Claim 4 has been amended to correct a minor informality
Claims 20 and 23 have been amended in response to examiner’s rejections under 35 USC § 112(b)
Claim 22 has been amended to add “each of” in the phrase “… coupling each of a plurality of die interconnects …”
Independent claims 1 and 19 have been amended to include limitations similar to those found in cancelled claims 14 and 24, respectively, but also changing the “capacitors” to “deep trench capacitors”, increasing the number of stacked metallization layers in the capacitors from two to four, and increasing the number of dielectric layers in the capacitor from one to four, as supported by Fig. 4 and ¶[0034].
Response to Arguments
Applicant’s arguments, see page 12, filed 13 Nov 2025, with respect to the previous objections to claims 2, 3, 5, 14, 24, and 26 have been fully considered and are persuasive. The previous objections to claims 2, 3, 5, and 26 have been withdrawn based on applicant’s amendments to these claims. The previous objections to claims 14 and 24 are no longer applicable because applicant has cancelled these claims.
Applicant’s arguments, see page 13, filed 13 Nov 2025, with respect to the rejections of claims 20 and 23 under 35 USC § 112(b) have been fully considered and are persuasive. The rejections of claims 20 and 23 under 35 USC § 112(b) have been withdrawn based on applicant’s amendments to these claims.
Applicant’s arguments, see pages 13–14, filed 13 Nov 2025, with respect to the rejections of independent claims 1 and 19 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejections of independent claims 1 and 19 under 35 USC § 102 have been withdrawn based on applicant’s amendments to these claims. However, upon further consideration of the amended claims 1 and 19, new grounds of rejection are made in view of newly found prior art references: patent application publication US 2023/0387330 A1 (by Lai et al.) and patent application publication US 2022/0199759 A1 (by Chyi Liu et al.).
Applicant’s arguments on pages 13–17, filed 13 Nov 2025, with respect to the rejections of dependent claims 2–18 (excluding 14) and 20–29 (excluding 24) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. That is, applicant argues that these claims are allowable based on claims 2–18 depending on independent claim 1, and claims 20–29 depending on claim 19; and based on applicant’s amendments to independent claims 1 and 19 to overcome the rejections of the independent claims under 35 USC § 102. However, this argument is moot due to the new grounds of rejection of independent claims 1 and 19 under 35 USC § 103 in light of newly found prior art.
The previous rejections of claims 14 and 24 under 35 USC § 103 are no longer applicable because these claims have been cancelled by the applicant.
Also in applicant’s reply filed 13 Nov 2025, applicant requests traversal of examiner’s objection to the previous version of ¶[0038] (filed 9 May 2023) of the specification, and at the same time provides a new version of ¶[0038] to overcome the examiner’s objection. However, applicant has not made any specific arguments to support traversal of the objection; i.e., applicant has not explained why it is believed that the previous 9 May 2023 version of ¶[0038] is correct and the new 13 Nov 2025 version of ¶[0038] is incorrect, the latter being the amendment suggested by the examiner in the previous office action. Therefore, applicant’s traversal is rejected, and the new ¶[0038] dated 13 Nov 2025 is accepted as overcoming the examiner’s previous objection. See the “Specification” section below for a detailed explanation as to why the examiner believes the new ¶[0038] to be correct.
Specification
Examiner acknowledges receipt of replacements for ¶[0005] and ¶[0038] in the amendments to the specification dated 13 Nov 2025. The amendment to ¶[0005] corrects a minor informality. The amendment to ¶[0038] is in response to the examiner’s objection in the previous office action dated 24 July 2025. Both of these replacement paragraphs are acceptable, and the new ¶[0038] overcomes the previous objection to this paragraph.
In the reply dated 13 Nov 2025, the applicant has requested traversal of the examiner’s previous objection to ¶[0038], by which the examiner assumes that the applicant requests to revert to the previous version of ¶[0038] from applicant’s previous amendment dated 9 May 2023. The applicant has not provided an argument as to why the applicant believes the 9 May 2023 version of ¶[0038] to be correct and the 13 Nov 2025 version of ¶[0038] to be incorrect. The examiner respectfully asserts that the 13 Nov 2025 version of ¶[0038], which matches the amendment suggested by the examiner in the previous office action dated 24 July 2025, is correct for the following reasons:
The previous (9 May 2023) version of ¶[0038] begins with “Then, as shown in fabrication stage 700E in Figure 7E, the die wafer 702 in the fabrication stage 700B in Figure 7B is singulated to create separate dies 204 (block 608 in Figure 6B).” However, the examiner asserts that the progression from the fabrication stage 700D in Fig. 7D to the fabrication stage 700E in Fig. 7E corresponds to block 610 (not to block 608) in Fig. 6B because the text in block 610 states: “SINGULATE DIES (204) COUPLED TO INTERPOSER SUBSTRATE (202) TO FORM IC PACKAGES (200)”. That is, in block 610, the object being singulated is not the die wafer 702, as by the time of fabrication stage 700D in Fig. 7D, the die wafer 702 had already been singulated to create the separate dies 204, which had already been attached to the top of the interposer substrate 202 as shown in Fig. 7D; rather, in block 610 the object being singulated in the progression from Fig. 7D to Fig. 7E is the previously formed combination of the interposer substrate 202 with the previously separated dies 204.
Note also that the progression from fabrication stage 700C of Fig. 7C to fabrication stage 700D of Fig. 7D corresponds to block 608 in Fig. 6B because the text in block 608 states: “SINGLULATE DIE WAFER (702) TO CREATE SEPARATE DIES (204) AND COUPLE DIES (204) TO INTERPOSER SUBSTRATE (202)”. That is, by the time of fabrication stage 700D in Fig. 7D, the separate dies 204 already exist and are coupled to the top surface of the interposer substrate 202 as shown in Fig. 7D.
The examiner also asserts that since the progression from fabrication stage 700C in Fig. 7C to the fabrication stage 700D in Fig. 7D (corresponding to block 608 in Fig. 6B) comprises two steps—first, singulating the die wafer 702 to create separate dies 204; second, coupling the dies 204 to the interposer substrate 202—there is no figure provided that shows an intermediate fabrication stage after creating the separate dies 204 and before coupling the dies 204 to the interposer substrate 202. Therefore, it would be somewhat confusing if the first sentence of ¶[0038] were amended to say, “Then, as shown in fabrication stage 700D in Figure 7D, the die wafer 702 in the fabrication stage 700B in Figure 7B is singulated to create separate dies 204 (block 608 in Figure 6B)”, because by the time of fabrication stage 700D, in addition to creating the separated dies 204, the separated dies 204 have also been coupled to the interposer substrate 202—this latter step not being described until the third sentence of ¶[0038].
This is why in the examiner’s suggested amendment to ¶[0038] in the office action dated 24 July 2025, the examiner suggested to remove the text “as shown in fabrication stage 700E in Figure 7E” from the first sentence (rather than amending said text to refer to 700D and Figure 7D, which would be more correct but still somewhat confusing), and add the text “As shown in fabrication stage 700D in Figure 7D” to the third sentence because that is the sentence where it is stated that “the singulated dies 204 are then placed on the second surface 216(2) of the interposer substrate 202 (block 608 in Figure 6B)”. As can be seen in Fig. 7D, fabrication state 700D shows the state in the manufacturing process after the singulated dies have been attached to the top surface of the interposer substrate 202 as described in block 608 of Fig. 6B, and before the combined object shown in Fig. 7D has been singulated to form the separate IC packages 200 shown in Fig. 7E as described in block 610 of Fig. 6B.
Based on the above arguments, the examiner concludes that the applicant’s amended ¶[0038] dated 13 Nov 2025 is correct. With this amendment, there is no disagreement between ¶[0038] and Figs. 6–7. Therefore, applicant’s traversal of the objection to ¶[0038] in the office action dated 24 July 2025 is rejected, and applicant’s amended ¶[0038] dated 13 Nov 2025 is accepted.
Drawings
The replacement drawing sheet containing an amended Fig. 3 was received on 13 November 2025; this replacement drawing sheet overcomes the objection in the previous office action dated 24 July 2025 by correcting the label “CAPACITOR INTERPOSE SUBSTRATE” to “CAPACITOR INTERPOSER SUBSTRATE 202”.
However, in the course of writing this office action, the examiner noticed other problems with the drawings, described in the objections below:
Fig. 5, box 506: “FORMING A SUBSTRATE LAYER …”
Fig. 5, box 508: “… SUCH THAT THE SECOND METALLIZATION LAYER (214(2)) COMPRISES …”
Fig. 5, box 510: “COUPLING A PACKAGE SUBSTRATE …”
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, referring to claims 1 and 19, the “fourth dielectric layer” that is “disposed between the respective adjacent first, second, third, and fourth trench metallization layers” must be shown or the feature canceled from the claims. No new matter should be entered. That is, Fig. 4 shows that the fourth dielectric layer 404(4) is disposed in a trench formed by the fourth trench metallization layer 402(4). Since the fourth dielectric layer 404(4) is shown to be disposed between two parts of the same (fourth) trench metallization layer 402(4), it cannot be said that the fourth dielectric layer 404(4) is disposed between adjacent trench metallization layers 402(1)–402(4). This drawing objection can be overcome by rewording portions of claims 1 and 19 to describe “a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer arranged in an alternating layer stack with the respective first, second, third, and fourth trench metallization layers” or similar. A portion of ¶[0034] of the specification may need to be reworded accordingly.
Referring to claim 17, the “a third metallization layer disposed between the first metallization layer and the substrate layer in the first direction” must be shown or the feature canceled from the claims. No new matter should be entered. That is, Fig. 3 shows that the substrate layer 222 is directly on top of the first metallization layer 214(1), and there is no metallization layer disposed between the first metallization layer 214(1) and the substrate layer 222 in the vertical direction.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities: subject-verb disagreement based on a plural subject. Appropriate correction is required. Suggested correction: “… wherein the first and third trench metallization layers [[is]]are coupled to a first, second metal interconnect of the plurality of second metal interconnects, and the second and fourth trench metallization layers [[is]]are coupled to a second, second metal interconnect of the plurality of second metal interconnects …”
Claim 19 is objected to because of the following informalities: subject-verb disagreement based on a plural subject. Appropriate correction is required. Suggested correction: “… wherein the first and third trench metallization layers [[is]]are coupled to a first, second metal interconnect of the plurality of second metal interconnects, and the second and fourth trench metallization layers [[is]]are coupled to a second, second metal interconnect of the plurality of second metal interconnects …”
Claim 19 is also objected to because of the following informality: a redundant/repeated phrase. Appropriate correction is required. Suggested correction: “… the substrate layer comprising one or more deep trench capacitors, …”
Claim 22 is objected to because of the following informality: referring to “the second metal interconnect” before introducing “a second metal interconnect”. Suggested correction: “… to a corresponding second metal interconnect of the plurality of second metal interconnects.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1–4, 6–13, 19–23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over patent application publication US 2010/0044089 A1 (by Shibuya et al., from the IDS, “Shibuya” hereafter) in view of patent application publication US 2023/0387330 A1 (by Lai et al., “Lai” hereafter) and patent application publication US 2022/0199759 A1 (by Chyi Liu et al., “Chyi Liu” hereafter).
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Regarding claim 1, Shibuya teaches:
An integrated circuit (IC) package (Fig. 3), comprising:
an interposer substrate 100 (“interposer integrated with capacitors 100” ¶[0029]) comprising a first surface S1 (see annotated Figs. 2–3) and a second surface S2 opposite of the first surface;
the interposer substrate 100 further comprising:
a first metallization layer 10 (Fig. 2, “plug substrate 10” ¶[0029]) comprising a plurality of first metal interconnects 14 (“electrode pads 14” ¶[0032], “Cu was used for […] electrode pads 13 and 14” ¶[0071]) exposed from the first surface S1;
a second metallization layer ML2 (see annotated Fig. 2) comprising a plurality of second metal interconnects 24 (“electrode pads 24” ¶[0031], “electroplating was performed […] to form a Cu layer […] and thereby form the via-plugs 23 and electrode pads 24” ¶[0073]) exposed from the second surface S2; and
a substrate layer 20 (“capacitor substrate 20” ¶[0029]) disposed between the first metallization layer 10 and the second metallization layer ML2 in a first direction Z (see annotated Fig. 2), the substrate layer 20 comprising one or more capacitors 22 (“The capacitor substrate 20 includes a substrate body 21 and capacitors 22 formed on the substrate body 21” ¶[0031]);
each first metal interconnect 14 of the plurality of first metal interconnects 14 intersecting a first axis Z1, Z2, or Z3 (see annotated Fig. 2) in the first direction Z that intersects a second metal interconnect 24 of the plurality of second metal interconnects 24;
a package substrate 111 (Fig. 3, “wiring board 111” ¶[0035]) coupled to the first surface S1 of the interposer substrate 100; and
a die 112 (“LSI 112” ¶[0035], “semiconductor device (LSI)” ¶[0002]) coupled to the second surface S2 of the interposer substrate 100.
However, Shibuya fails to teach that the capacitors 22 are deep trench capacitors, each deep trench capacitor comprising:
a first trench metallization layer, a second trench metallization layer, a third trench metallization layer, and a fourth trench metallization layer disposed in trenches in the substrate layer adjacent to each other;
a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer disposed between the respective adjacent first, second, third, and fourth trench metallization layers;
wherein the first and third trench metallization layer is coupled to a first, second metal interconnect of the plurality of second metal interconnects, and the second and fourth trench metallization layer is coupled to a second, second metal interconnect of the plurality of second metal interconnects.
In the same field of endeavor, Lai teaches that an interposer 120 (Fig. 1, ¶[0031]) includes deep trench capacitors (DTCs) 310, 320, 330, and 340 (Figs. 4–5, “sub-capacitors 310, 320, 330, and 340” ¶[0038], and “In the present disclosure, a novel design of DTCs and surrounding structures can provide several advantages over the current technology. The DTCs can be formed in the interposer with multiple via contacts formed in order to reduce the ESR and increase the capacitance” ¶[0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibuya’s interposer substrate 100 by replacing the capacitors 22, which are parallel plate capacitors, with deep trench capacitors similar to those disclosed by Lai in Figs. 4–5 because Lai’s deep trench capacitors have the advantage of reducing the equivalent series resistance (ESR) and increasing the capacitance (see Lai ¶[0029–0030]). Shibuya’s parallel plate capacitors 22 and Lai’s deep trench capacitors 310–340 are each included in an interposer for the same purpose of reducing fluctuations in voltage supplied to an IC chip (“As a countermeasure against the switching noise in the LSI, a decoupling capacitor is provided between the LSI and a wiring board mounting thereon the LSI” ¶[0004] of Shibuya; “Within the interposer, deep trench capacitors (DTCs) may be formed which can help remove noise and provide stable voltages” ¶[0028] of Lai).
However, Lai’s deep trench capacitors comprise only two trench metallization layers 350 and 360 (Figs. 4–5, “the top plate 350 and the bottom plate 360” ¶[0041]), whereas the present claim requires four trench metallization layers.
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In the same field of endeavor, Chyi Liu teaches that a deep trench capacitor UC (“unit capacitor region UC” ¶[0038]; “deep trench capacitor, which is herein referred to as a unit capacitor region” ¶[0029]) comprises four trench metallization layers, including:
a first trench metallization layer 10A, a second trench metallization layer 20A, a third trench metallization layer 10B, and a fourth trench metallization layer 20B (“metallic electrode plates (10A, 20A, 10B, 20B)” ¶[0033]) disposed in trenches 9 in the substrate layer 8 (“Deep trenches 9 vertically extending into the substrate 8” ¶[0028]) adjacent to each other (as shown in Fig. 13A);
a first dielectric layer 15, a second dielectric layer 15, a third dielectric layer 15 (“node dielectric layers 15” ¶[0033]), and a fourth dielectric layer 32 (“node dielectric material layer 32” ¶[0037]) disposed between the respective adjacent first 10A, second 20A, third 10B, and fourth 20B trench metallization layers (i.e., the three node dielectric layers 15 are between adjacent trench metallization layers, and the fourth dielectric layer 32 is on top of the fourth trench metallization layer 20B, as shown in Fig. 13A);
wherein the first 10A and third 10B trench metallization layer[s] is [are] coupled (as shown in Fig. 13A) to a first, second metal interconnect (“pad region” of the “first metal line 62” ¶[0075]) of the plurality of second metal interconnects 62 and 64 (“metal interconnect structures (62, 64)” ¶[0081]), and the second 20A and fourth 20B trench metallization layer[s] is [are] coupled (as shown in Fig. 13A) to a second, second metal interconnect (“pad region” of the “second metal line 64” ¶[0075]) of the plurality of second metal interconnects 62 and 64.
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From ¶[0036] of Chyi Liu: “The metallic electrode plates (10A, 20A, 10B, 20B) may be sequentially numbered in the order of deposition. For example, the metallic electrode plates (10A, 20A, 10B, 20B) may include a first metallic electrode plate 10A, a second metallic electrode plate 20A, a third metallic electrode plate 10B, a fourth metallic electrode plate 20B, etc. Patterned portions of each odd-numbered metallic electrode plate (10A, 10B) may be subsequently used to form a primary electrode assembly that functions as a primary node, i.e., a first node, of a deep trench capacitor, and patterned portions of each even-numbered metallic electrode plate (20A, 20B) may be subsequently used to form a complementary electrode assembly that functions as a complementary node, i.e., a second node, of the deep trench capacitor.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shibuya’s interposer substrate 100, after replacing Shibuya’s parallel plate capacitors 22 with deep trench capacitors similar to those of Lai as described above, by using four trench metallization layers (instead of Lai’s two trench metallization layers 350 and 360 in Figs. 4–5) similar to Chyi Liu’s four metallic electrode plates 10A, 20A, 10B, and 20B (Fig. 13A) because Chyi Liu teaches that a larger capacitance can be achieved from the combined capacitor in which the first conductor is the combination of the odd-numbered metallic electrode plates 10A and 10B, and the second conductor is the combination of the even-numbered metallic electrode plates 20A and 20B. Similar to Shibuya and Lai, each of whom included a capacitor in an interposer for the purpose of reducing the fluctuations in voltage supplied to an attached IC die, Chyi Liu states: “Deep trench capacitors may be used as an integrated passive device to provide large capacitance, which can be used to stabilize a power supply and function as a noise filter in handheld devices” ¶[0024].
Regarding claim 2, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that each first metal interconnect 14 of the plurality of first metal interconnects 14 is aligned with (as shown in Fig. 2) the second metal interconnect 24 of the plurality of second metal interconnects 24 in the first direction Z.
Regarding claim 3, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that each first metal interconnect 14 of the plurality of first metal interconnects 14 partially overlaps (as shown in Fig. 2) the second metal interconnect 24 of the plurality of second metal interconnects in the first direction Z.
Regarding claim 4, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that:
the plurality of first metal interconnects 14 has a first pitch P1 (see annotated Fig. 2) in a second direction X orthogonal to the first direction Z; and
the plurality of second metal interconnects 24 has the first pitch P1 in the second direction X.
Regarding claim 6, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that the package substrate 111 comprises:
a third surface S3 (see annotated Fig. 3) adjacent to the first surface S1 of the interposer substrate 100; and
a plurality of third metal interconnects 113 (“electrode pads” ¶[0076]) exposed from the third surface S3;
each of the plurality of third metal interconnects 113 coupled to the first metal interconnect 14 of the plurality of first metal interconnects 14 (“electrode pads 14 of the plug substrate was connected to the electrode pads of the wiring board” ¶[0076]).
Regarding claim 7, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 6, wherein Shibuya additionally teaches that each of the plurality of third metal interconnects 113 intersects the first axis Z1, Z2, or Z3 (see annotated Fig. 2 and compare with Fig. 3) in the first direction Z that intersects the first metal interconnect 14 of the plurality of first metal interconnects 14.
Regarding claim 8, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 7, wherein Shibuya additionally teaches that the die 112 comprises:
a fourth surface S4 (see annotated Fig. 3) adjacent to the second surface S2 of the interposer substrate 100; and
a plurality of die interconnects 114 (“electrode pads of the LSI” ¶[0084]) exposed from the fourth surface S4;
each of the plurality of die interconnects 114 coupled to (as shown in Figs. 2–3) the second metal interconnect 24 of the plurality of second metal interconnects 24 (“The electrode pads 24 of the capacitor substrate were connected to the electrode pads of the LSI” ¶[0084]).
Regarding claim 9, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 8, wherein Shibuya additionally teaches that each of the plurality of die interconnects 114 intersects the first axis Z1, Z2, or Z3 (see annotated Fig. 2 and compare with Fig. 3) in the first direction Z that intersects the second metal interconnect 24 of the plurality of second metal interconnects 24.
Regarding claim 10, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that the die 112 comprises:
a third surface S4 (see annotated Fig. 3) adjacent to the second surface S2 of the interposer substrate 100; and
a plurality of die interconnects 114 (“electrode pads of the LSI” ¶[0084]) exposed from the third surface S4;
each of the plurality of die interconnects 114 coupled to (as shown in Figs. 2–3) the second metal interconnect 24 of the plurality of second metal interconnects 24 (“The electrode pads 24 of the capacitor substrate were connected to the electrode pads of the LSI” ¶[0084]).
Regarding claim 11, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 10, wherein Shibuya additionally teaches that each of the plurality of die interconnects 114 intersects the first axis Z1, Z2, or Z3 (see annotated Fig. 2 and compare with Fig. 3) in the first direction Z that intersects the second metal interconnect 24 of the plurality of second metal interconnects 24.
Regarding claim 12, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that at least one capacitor 22 of the one or more capacitors 22 is coupled to a second metal interconnect 24 of the plurality of second metal interconnects 24 (as shown in Fig. 2, the leftmost of the three interconnects 24 is coupled to the top electrode 41 of a capacitor 22, through the intervening conductive elements 23 and 26).
Recall that in the rejection of claim 1, Shibuya’s interposer substrate 100 was modified in view of Lai and Chyi Liu to replace Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC. Although Chyi Liu’s deep trench capacitors UC comprise “An alternating layer stack 30 of metallic electrode plates (10A, 20A, 10B, 20B) and node dielectric layers 15” ¶[0033]—i.e., four electrodes, analogous to the four “trench metallization layers” of the present application—as a whole the deep trench capacitors UC still function as a single capacitor having two conductors: a “primary electrode assembly” formed from the electrical interconnection of the first and third metallic electrode plates 10A and 10B, and a “complimentary electrode assembly” formed from the electrical interconnection of the second and fourth metallic electrode plates 20A and 20B.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the previously described modification of Shibuya’s interposer substrate 100 in view of Lai and Chyi Liu would necessarily require coupling (interpreted as forming an electrical connection) at least one of Chyi Liu’s deep trench capacitors UC (Fig. 13A) to at least one of Shibuya’s second metal interconnects 24 (Fig. 2), e.g., by an electrical connection between the complimentary electrode assembly (Chyi Liu’s 20A, 20B, 52B, 54B, and 64 in Fig. 13A) of the deep trench capacitors UC and Shibuya’s leftmost of the three interconnects 24. The reason for obviousness is that Shibuya shows a similar electrical connection between the top electrode 41 of a parallel plate capacitor 22 and the leftmost of the three interconnects 24 (through the intervening conductive elements 23 and 26), and after replacing Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC, it would obviously still be necessary to electrically connect one of the two conductors of the deep trench capacitors UC to an external interconnect such as one of Shibuya’s second metal interconnects 24. The general principle at work here is that in all cases, in order for a capacitor to function (i.e., to store electrical charge), separate electrical leads/wirings must connect to the two conductors of the capacitor in order to supply a voltage difference between the two conductors. The present claim describes the electrical connection between one of the two conductors of the capacitor and an external contact, in this case referring to an external contact (i.e., one of Shibuya’s second metal interconnects 24 in Fig. 2) that is on the top surface of the interposer substrate.
Note that in Shibuya’s Fig. 2, each of the second metal interconnects 24 is part of a conductive column comprising conductive elements (from bottom to top) 14, 12, 13, 31, 26, 23, and 24; therefore, in the prior art of Shibuya it would be equally true to say that the leftmost of the three interconnects 14 on the bottom surface of the interposer substrate (previously identified with the “first metal interconnects” of the present application) is coupled to the top electrode 41 of a capacitor 22. In other words, in the prior art of Shibuya, the entire leftmost conductive column (14, 12, 13, 31, 26, 23, and 24) is coupled to the top electrode 41 of the capacitor 22, and it would have been obvious to extend this idea by coupling Shibuya’s leftmost conductive column to one of the two conductors, e.g., to the complimentary electrode assembly, of Chyi Lui’s deep trench capacitors UC.
Regarding claim 13, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, wherein Shibuya additionally teaches that at least one capacitor 22 of the one or more capacitors 22 is coupled to a first metal interconnect 14 of the plurality of first metal interconnects 14 (as shown in Fig. 2, the middle of the three interconnects 14 is coupled to the bottom electrode 43 of a capacitor 22, through intervening conductive elements 44, 26, 31, 13, and 12).
Recall that in the rejection of claim 1, Shibuya’s interposer substrate 100 was modified in view of Lai and Chyi Liu to replace Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC. Although Chyi Liu’s deep trench capacitors UC comprise “An alternating layer stack 30 of metallic electrode plates (10A, 20A, 10B, 20B) and node dielectric layers 15” ¶[0033]—i.e., four electrodes, analogous to the four “trench metallization layers” of the present application—as a whole the deep trench capacitors UC still function as a single capacitor having two conductors: a “primary electrode assembly” formed from the electrical interconnection of the first and third metallic electrode plates 10A and 10B, and a “complimentary electrode assembly” formed from the electrical interconnection of the second and fourth metallic electrode plates 20A and 20B.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the previously described modification of Shibuya’s interposer substrate 100 in view of Lai and Chyi Liu would necessarily require coupling (interpreted as forming an electrical connection) at least one of Chyi Liu’s deep trench capacitors UC (Fig. 13A) to at least one of Shibuya’s first metal interconnects 14 (Fig. 2), e.g., by an electrical connection between the primary electrode assembly (Chyi Liu’s 10A, 10B, 52A, 54A, and 62 in Fig. 13A) of the deep trench capacitors UC and Shibuya’s middle of the three interconnects 14. The reason for obviousness is that Shibuya shows a similar electrical connection between the bottom electrode 43 of a parallel plate capacitor 22 and the middle of the three interconnects 14 (through the intervening conductive elements 44, 26, 31, 13, and 12), and after replacing Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC, it would obviously still be necessary to electrically connect one of the two conductors of the deep trench capacitors UC to an external interconnect such as one of Shibuya’s first metal interconnects 14. The general principle at work here is that in all cases, in order for a capacitor to function (i.e., to store electrical charge), separate electrical leads/wirings must connect to the two conductors of the capacitor in order to supply a voltage difference between the two conductors. The present claim describes the electrical connection between one of the two conductors of the capacitor and an external contact, in this case referring to an external contact (i.e., one of Shibuya’s first metal interconnects 14 in Fig. 2) that is on the bottom surface of the interposer substrate.
Note that in Shibuya’s Fig. 2, each of the first metal interconnects 14 is part of a conductive column comprising conductive elements (from bottom to top) 14, 12, 13, 31, 26, 23, and 24; therefore, in the prior art of Shibuya it would be equally true to say that the middle of the three interconnects 24 on the top surface of the interposer substrate (previously identified with the “second metal interconnects” of the present application) is coupled to the bottom electrode 43 of a capacitor 22. In other words, in the prior art of Shibuya, the entire middle conductive column (14, 12, 13, 31, 26, 23, and 24) is coupled to the bottom electrode 43 of the capacitor 22, and it would have been obvious to extend this idea by coupling Shibuya’s middle conductive column to one of the two conductors, e.g., to the primary electrode assembly, of Chyi Lui’s deep trench capacitors UC.
Regarding claim 19, Shibuya teaches:
A method of fabricating (shown in the sequence of Figs. 7A–7F ¶[0053–0057] and Figs. 9–12 ¶[0064–0076]) a plurality of IC packages (i.e., multiple copies of the IC package of Fig. 3), comprising for each IC package (Fig. 3) of one or more IC packages:
forming an interposer substrate 100 (Fig. 7F and Fig. 2, “interposer integrated with capacitors 100” ¶[0029]) comprising:
forming a first metallization layer 10 (“plug substrate 10” ¶[0029], see Fig. 2 and compare with forming step in Fig. 7B and Fig. 10) comprising a plurality of first metal interconnects 14 (“electrode pads 14” ¶[0032], “Cu was used for […] electrode pads 13 and 14” ¶[0071]) exposed from a first surface S1 (see annotated Fig. 2) and intersecting a first axis Z1, Z2, or Z3 in a first direction Z;
forming a substrate layer 20 (“capacitor substrate 20” ¶[0029], see Fig. 2 and compare with forming step shown in Fig. 7E and Fig. 12) adjacent to the first metallization layer 10, the substrate layer 20 comprising one or more capacitors 22 (“The capacitor substrate 20 includes a substrate body 21 and capacitors 22 formed on the substrate body 21” ¶[0031]); and
forming a second metallization layer ML2 (see annotated Fig. 2 and compare with forming step shown in Fig. 7E and Fig. 12) adjacent to the substrate layer 20 such that the substrate layer 20 is disposed between the first metallization layer 10 and the second metallization layer ML2 in the first direction Z (as shown in annotated Fig. 2, a bottom portion of the substrate layer 20 is between the first metallization layer 10 and the second metallization layer ML2), the second metallization layer ML2 comprising a plurality of second metal interconnects 24 (“electrode pads 24” ¶[0031], “electroplating was performed […] to form a Cu layer […] and thereby form the via-plugs 23 and electrode pads 24” ¶[0073]) exposed from a second surface S2 (see annotated Fig. 2) opposite the first surface S1 and intersecting the first axis Z1, Z2, or Z3 in the first direction Z;
coupling a package substrate 111 to the first surface S1 of the interposer substrate 100 (“FIG. 3 is a sectional view showing the state of mounting the interposer integrated with capacitors 100. Upon mounting the interposer integrated with capacitors 100, the plug substrate 10 is coupled to the side of wiring board 111” ¶[0035]); and
coupling one or more dies 112 (“LSI 112” ¶[0035], “semiconductor device (LSI)” ¶[0002]) to the second surface S2 of the interposer substrate 100 (“the capacitor substrate 20 is coupled to the side of LSI 112” ¶[0035]).
However, Shibuya fails to teach that the capacitors 22 are deep trench capacitors, each deep trench capacitor comprising:
a first trench metallization layer, a second trench metallization layer, a third trench metallization layer, and a fourth trench metallization layer disposed in trenches in the substrate layer adjacent to each other;
a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer disposed between the respective adjacent first, second, third, and fourth trench metallization layers;
wherein the first and third trench metallization layer is coupled to a first, second metal interconnect of the plurality of second metal interconnects, and the second and fourth trench metallization layer is coupled to a second, second metal interconnect of the plurality of second metal interconnects.
In the same field of endeavor, Lai teaches that an interposer 120 (Fig. 1, ¶[0031]) includes deep trench capacitors (DTCs) 310, 320, 330, and 340 (Figs. 4–5, “sub-capacitors 310, 320, 330, and 340” ¶[0038], and “In the present disclosure, a novel design of DTCs and surrounding structures can provide several advantages over the current technology. The DTCs can be formed in the interposer with multiple via contacts formed in order to reduce the ESR and increase the capacitance” ¶[0030]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibuya’s interposer substrate 100 by replacing the capacitors 22, which are parallel plate capacitors, with deep trench capacitors similar to those disclosed by Lai in Figs. 4–5 because Lai’s deep trench capacitors have the advantage of reducing the equivalent series resistance (ESR) and increasing the capacitance (see Lai ¶[0029–0030]). Shibuya’s parallel plate capacitors 22 and Lai’s deep trench capacitors 310–340 are each included in an interposer for the same purpose of reducing fluctuations in voltage supplied to an IC chip (“As a countermeasure against the switching noise in the LSI, a decoupling capacitor is provided between the LSI and a wiring board mounting thereon the LSI” ¶[0004] of Shibuya; “Within the interposer, deep trench capacitors (DTCs) may be formed which can help remove noise and provide stable voltages” ¶[0028] of Lai).
However, Lai’s deep trench capacitors comprise only two trench metallization layers 350 and 360 (Figs. 4–5, “the top plate 350 and the bottom plate 360” ¶[0041]), whereas the present claim requires four trench metallization layers.
In the same field of endeavor, Chyi Liu teaches that a deep trench capacitor UC (“unit capacitor region UC” ¶[0038]; “deep trench capacitor, which is herein referred to as a unit capacitor region” ¶[0029]) comprises four trench metallization layers, including:
a first trench metallization layer 10A, a second trench metallization layer 20A, a third trench metallization layer 10B, and a fourth trench metallization layer 20B (“metallic electrode plates (10A, 20A, 10B, 20B)” ¶[0033]) disposed in trenches 9 in the substrate layer 8 (“Deep trenches 9 vertically extending into the substrate 8” ¶[0028]) adjacent to each other (as shown in Fig. 13A);
a first dielectric layer 15, a second dielectric layer 15, a third dielectric layer 15 (“node dielectric layers 15” ¶[0033]), and a fourth dielectric layer 32 (“node dielectric material layer 32” ¶[0037]) disposed between the respective adjacent first 10A, second 20A, third 10B, and fourth 20B trench metallization layers (i.e., the three node dielectric layers 15 are between adjacent trench metallization layers, and the fourth dielectric layer 32 is on top of the fourth trench metallization layer 20B, as shown in Fig. 13A);
wherein the first 10A and third 10B trench metallization layer[s] is [are] coupled (as shown in Fig. 13A) to a first, second metal interconnect (“pad region” of the “first metal line 62” ¶[0075]) of the plurality of second metal interconnects 62 and 64 (“metal interconnect structures (62, 64)” ¶[0081]), and the second 20A and fourth 20B trench metallization layer[s] is [are] coupled (as shown in Fig. 13A) to a second, second metal interconnect (“pad region” of the “second metal line 64” ¶[0075]) of the plurality of second metal interconnects 62 and 64.
From ¶[0036] of Chyi Liu: “The metallic electrode plates (10A, 20A, 10B, 20B) may be sequentially numbered in the order of deposition. For example, the metallic electrode plates (10A, 20A, 10B, 20B) may include a first metallic electrode plate 10A, a second metallic electrode plate 20A, a third metallic electrode plate 10B, a fourth metallic electrode plate 20B, etc. Patterned portions of each odd-numbered metallic electrode plate (10A, 10B) may be subsequently used to form a primary electrode assembly that functions as a primary node, i.e., a first node, of a deep trench capacitor, and patterned portions of each even-numbered metallic electrode plate (20A, 20B) may be subsequently used to form a complementary electrode assembly that functions as a complementary node, i.e., a second node, of the deep trench capacitor.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shibuya’s interposer substrate 100, after replacing Shibuya’s parallel plate capacitors 22 with deep trench capacitors similar to those of Lai as described above, by using four trench metallization layers (instead of Lai’s two trench metallization layers 350 and 360 in Figs. 4–5) similar to Chyi Liu’s four metallic electrode plates 10A, 20A, 10B, and 20B (Fig. 13A) because Chyi Liu teaches that a larger capacitance can be achieved from the combined capacitor in which the first conductor is the combination of the odd-numbered metallic electrode plates 10A and 10B, and the second conductor is the combination of the even-numbered metallic electrode plates 20A and 20B. Similar to Shibuya and Lai, each of whom included a capacitor in an interposer for the purpose of reducing the fluctuations in voltage supplied to an attached IC die, Chyi Liu states: “Deep trench capacitors may be used as an integrated passive device to provide large capacitance, which can be used to stabilize a power supply and function as a noise filter in handheld devices” ¶[0024].
Regarding claim 20, Shibuya (as modified by Lai and Chyi Lui) teaches the method of claim 19, wherein Shibuya additionally teaches that:
forming the first metallization layer 10 further comprises forming the first metallization layer 10 comprising the plurality of first metal interconnects 14 having a first pitch P1 (see annotated Fig. 2) in a second direction X orthogonal to the first direction Z; and
forming the second metallization layer ML2 further comprises forming the second metallization layer ML2 comprising the plurality of second metal interconnects 24 having the first pitch P1 in the second direction X.
Regarding claim 21, Shibuya (as modified by Lai and Chyi Lui) teaches the method of claim 19, wherein Shibuya additionally teaches that coupling the package substrate 111 to the first surface S1 of the interposer substrate 100 comprises coupling a plurality of third metal interconnects 113 (“electrode pads” ¶[0076]) exposed from a third surface S3 (see annotated Fig. 3) of the package substrate 111 adjacent to the first surface S1 of the interposer substrate 100 to a first metal interconnect 14 of the plurality of first metal interconnects 14 (“electrode pads 14 of the plug substrate was connected to the electrode pads of the wiring board” ¶[0076]).
Regarding claim 22, Shibuya (as modified by Lai and Chyi Lui) teaches the method of claim 19, wherein Shibuya additionally teaches that coupling the one or more dies 112 to the second surface S2 of the interposer substrate 100 comprises coupling (as shown in Figs. 2–3) each of a plurality of die interconnects 114 (“electrode pads of the LSI” ¶[0084]) exposed from a third surface S4 (see annotated Fig. 3) of the one or more dies 112 adjacent to the second surface S2 of the interposer substrate 100, to the second metal interconnect 24 of the plurality of second metal interconnects (“The electrode pads 24 of the capacitor substrate were connected to the electrode pads of the LSI” ¶[0084]).
Regarding claim 23, Shibuya (as modified by Lai and Chyi Lui) teaches the method of claim 22, wherein Shibuya additionally teaches that:
forming the interposer substrate 100 further comprises coupling at least one capacitor 22 of the one or more capacitors 22 to a second metal interconnect 24 of the plurality of second metal interconnects 24 (as shown in Fig. 2, the leftmost of the three interconnects 24 is coupled to the top electrode 41 of a capacitor 22, and the middle of the three interconnects 24 is coupled to the bottom electrode 43 of a capacitor 22).
Recall that in the rejection of claim 19, Shibuya’s interposer substrate 100 was modified in view of Lai and Chyi Liu to replace Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC. Although Chyi Liu’s deep trench capacitors UC comprise “An alternating layer stack 30 of metallic electrode plates (10A, 20A, 10B, 20B) and node dielectric layers 15” ¶[0033]—i.e., four electrodes, analogous to the four “trench metallization layers” of the present application—as a whole the deep trench capacitors UC still function as a single capacitor having two conductors: a “primary electrode assembly” formed from the electrical interconnection of the first and third metallic electrode plates 10A and 10B, and a “complimentary electrode assembly” formed from the electrical interconnection of the second and fourth metallic electrode plates 20A and 20B.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that forming the previously described modification of Shibuya’s interposer substrate 100 in view of Lai and Chyi Liu would necessarily require coupling (interpreted as forming an electrical connection) at least one of Chyi Liu’s deep trench capacitors UC (Fig. 13A) to at least one of Shibuya’s second metal interconnects 24 (Fig. 2), e.g., by an electrical connection between the complimentary electrode assembly (Chyi Liu’s 20A, 20B, 52B, 54B, and 64 in Fig. 13A) of the deep trench capacitors UC and Shibuya’s leftmost of the three interconnects 24. The reason for obviousness is that Shibuya shows a similar electrical connection between the top electrode 41 of a parallel plate capacitor 22 and the leftmost of the three interconnects 24 (through the intervening conductive elements 23 and 26), and after replacing Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC, it would obviously still be necessary to electrically connect one of the two conductors of the deep trench capacitors UC to an external interconnect such as one of Shibuya’s second metal interconnects 24. The general principle at work here is that in all cases, in order for a capacitor to function (i.e., to store electrical charge), separate electrical leads/wirings must connect to the two conductors of the capacitor in order to supply a voltage difference between the two conductors. The present claim describes the electrical connection between one of the two conductors of the capacitor and an external contact, in this case referring to an external contact (i.e., one of Shibuya’s second metal interconnects 24 in Fig. 2) that is on the top surface of the interposer substrate.
Regarding claim 25, Shibuya (as modified by Lai and Chyi Lui) teaches the method of claim 19, Shibuya additionally teaches that the method further comprises forming an interposer substrate wafer comprising the interposer substrate 100 for each IC package (Fig. 3) of the plurality of IC packages (“an interposer integrated with capacitors similar to that shown in FIG. 2 was actually manufactured in accordance with the procedure of FIGS. 7A to 7F. To begin with, a 4-inch silicon wafer was prepared as the base substrate 21a” ¶[0064], and “Subsequently, the plug substrate 10 and capacitor substrate 20 which are unified together are subjected to cutting in accordance with LSIs [large scale integrations with dies 112 of Fig. 3], as shown in FIG. 7F, thereby manufacturing the interposer integrated with capacitors 100 shown in FIG. 1” ¶[0057]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over patent application publication US 2010/0044089 A1 (by Shibuya et al., from the IDS, “Shibuya” hereafter) in view of patent application publication US 2023/0387330 A1 (by Lai et al., “Lai” hereafter), patent application publication US 2022/0199759 A1 (by Chyi Liu et al., “Chyi Liu” hereafter), and patent US 6,961,231 B1 (to Alexander et al., from the IDS, “Alexander” hereafter).
Regarding claim 5, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 4, as shown above.
However, Shibuya fails to teach that:
the plurality of first metal interconnects 14 has a second pitch in a third direction Y orthogonal to the second direction X (see annotated Fig. 2 from Shibuya); and
the plurality of second metal interconnects 24 has the second pitch in the third direction Y.
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In the same field of endeavor, Alexander teaches that a capacitive interposer 103 has first metal interconnects MI1 and second metal interconnects MI2 (see annotated Figs. 1–2 from Alexander) each having a first pitch D1 in a second direction X and a second pitch D2 in a third direction Y.
Alexander’s capacitive interposer 103 is similar to Shibuya’s interposer substrate 100 in that both interposers include capacitors; both interposers have first and second interconnects on the bottom and top sides, respectively, of the interposers; and in both interposers the first interconnects are aligned with the corresponding second interconnects along a direction Z that is perpendicular to the top and bottom sides of the interposers (i.e., Z is the thickness direction of the interposers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Shibuya’s interposer substrate 100 has an unshown third direction Y that is perpendicular to the page in Shibuya’s Figs. 2–3, and that Shibuya’s first metal interconnects 14 may be spaced apart by a second pitch along an axis parallel to the third direction Y. Similarly, Shibuya’s second metal interconnects 24 may be spaced apart by the second pitch along an axis parallel to the third direction Y since each first metal interconnect 14 is aligned with a corresponding second metal interconnect 24 along a direction Z that is the thickness direction of the interposer substrate 100. The reason for obviousness is that it is known in the prior art that interposers may have vertically aligned interconnects on their top and bottom sides that are arranged in a two-dimensional grid so that adjacent interconnects are spaced apart by a first pitch along a direction X and a second pitch along a direction Y that is orthogonal to the direction X, as shown by Alexander’s Figs. 1–2.
Claims 15–17 are rejected under 35 U.S.C. 103 as being unpatentable over patent application publication US 2010/0044089 A1 (by Shibuya et al., from the IDS, “Shibuya” hereafter) in view of patent application publication US 2023/0387330 A1 (by Lai et al., “Lai” hereafter), patent application publication US 2022/0199759 A1 (by Chyi Liu et al., “Chyi Liu” hereafter), and patent application publication US 2007/0076348 A1 (by Shioga et al., “Shioga” hereafter).
Regarding claim 15, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, as shown above. However, Shibuya fails to teach that:
the first metallization layer 10 comprises a plurality of first metal lines each coupled to a first metal interconnect of the plurality of first metal interconnects; and
the second metallization layer ML2 (see annotated Fig. 2) comprises a plurality of second metal lines each coupled to a second metal interconnect of the plurality of second metal interconnects.
In the same field of endeavor, Shioga teaches an IC package (Fig. 4, “electronic device” ¶[0029]) comprising an interposer 2 disposed between a package substrate 4 (“substrate 4” ¶[0088]) and a die 6 (“semiconductor integrated circuit device 6” ¶[0093]), wherein the interposer 2 comprises capacitors 12 (“thin-film capacitors 12” ¶[0047]), which are analogous to Shibuya’s IC package (Fig. 3), interposer substrate 100, package substrate 111, die 112, and capacitors 22, respectively.
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Shioga’s interposer 2 comprises a first metallization layer MET1 and a second metallization layer MET2 (see annotated Fig. 4) that are located in a bottom portion and a top portion, respectively, of the interposer 2.
Shioga teaches that:
the first metallization layer MET1 comprises a plurality of first metal lines 32a (“interconnections 32a” ¶[0049]) each coupled to (as shown in Fig. 4) a first metal interconnect 60a (“electrode pads 60a” ¶[0080]) of the plurality of first metal interconnects 60a, 60b, and 60c (“electrode pads 60a–60c” ¶[0080]); and
the second metallization layer MET2 comprises a plurality of second metal lines 48 and 50 (“interconnections 48” and “other interconnections 50” ¶[0070]) each coupled to (as shown in Fig. 4) a second metal interconnect 58b of the plurality of second metal interconnects 58a, 58b, and 58c (“partial electrodes 58a–58c” ¶[0075]).
As to the purpose of the first metal lines 32a, Shioga states: “The interconnections 32a are for electrically interconnecting the plural through-electrodes 14a electrically connected to the lower electrodes 20 of the thin-film capacitors 12” ¶[0049]. In other words, the first metal lines 32a electrically connect the plural through electrodes 14a (one of which is shown in the cross section in Fig. 1) to each other; electrically connect the plural through electrodes 14a to the lower electrodes 20 of the capacitors 12; and electrically connect the lower electrodes 20 to each other.
As to the purpose of the second metal lines 48 and 50, Shioga states: “an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48” (abstract); and “a plurality of the interconnections 48 are formed, and the plural interconnections 48 are electrically connected to each other by other interconnections 50. Thus, the upper electrodes 24 of the plural thin-film capacitors 12 are connected to each other by the interconnections 48, etc.” ¶[0070]. In other words, the second metal lines 48 and 50 electrically connect the plural through electrodes 14b (two of which are shown in the cross section in Fig. 1) to each other; electrically connect the plural through electrodes 14b to the upper electrodes 24 of the capacitors 12; and electrically connect the upper electrodes 24 to each other.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibuya’s interposer substrate 100 (Fig. 2) by having the first metallization layer 10 comprise first metal lines coupled to a first metal interconnect 14 of the plurality of first metal interconnects 14, and by having the second metallization layer ML2 (see annotated Fig. 2 from Shibuya) comprise second metal lines coupled to a second metal interconnect 24 of the plurality of second metal interconnects 24. The reason for obviousness is that Shioga shows that first metal lines 32a (Fig. 4) may be used to provide horizontal interconnection between the lower electrodes 20 of the capacitors 12 and the first metal interconnects 60a (which are analogous Shibuya’s first metal interconnects 14), and second metal lines 48 and 50 may be used to provide horizontal interconnection between the upper electrodes 24 of the capacitors 12 and the second metal interconnects 58b (which are analogous to Shibuya’s second metal interconnects 24).
That is, both Shibuya’s Fig. 2 and Shioga’s Fig. 4 disclose means of electrically connecting the upper and lower electrodes of the capacitors to different conductive columns (e.g., Shibuya’s stack of conductive elements 14, 12, 13, 31, 26, 23, 24 or Shioga’s stack of conductive elements 60a, 28a, 30a, 32a, 36a, 45a, 46a, 54a, 58a [altogether comprising a through-electrode 14a]) that pass through the interposer in the vertical direction. As a means of electrical connection, Shioga’s first metal lines 32a and second metal lines 48 and 50 may be considered to be functionally equivalent substitutes for Shibuya’s terminal electrodes 26.
Recall that in the rejection of claim 1, Shibuya’s interposer substrate 100 was modified in view of Lai and Chyi Liu to replace Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC. Although Chyi Liu’s deep trench capacitors UC comprise “An alternating layer stack 30 of metallic electrode plates (10A, 20A, 10B, 20B) and node dielectric layers 15” ¶[0033]—i.e., four electrodes, analogous to the four “trench metallization layers” of the present application—as a whole the deep trench capacitors UC still function as a single capacitor having two conductors: a “primary electrode assembly” formed from the electrical interconnection of the first and third metallic electrode plates 10A and 10B, and a “complimentary electrode assembly” formed from the electrical interconnection of the second and fourth metallic electrode plates 20A and 20B.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shibuya’s interposer substrate (after the previous modifications in view of Lai and Chyi Liu described in the rejection of claim 1) to include metal lines similar to Shioga’s first and second metal lines 32a and 48/50 to provide electrical connection between the primary electrode assembly (Chyi Liu’s 10A, 10B, 52A, 54A, and 62 in Fig. 13A) of the deep trench capacitors and a first metal interconnect; and between the complimentary electrode assembly (Chyi Liu’s 20A, 20B, 52B, 54B, and 64 in Fig. 13A) and a second metal interconnect.
Here the claimed “first metal lines” are represented by the addition of Shioga’s first metal lines 32a (Fig. 4) to Shibuya’s first metallization layer 10 (Fig. 2) of the interposer substrate 100 to connect to one of the first metal interconnects 14, which may be called “a first metal interconnect of the plurality of first metal interconnects”, as claimed. Note that Shioga’s first metal lines 32a are located in the first metallization layer MET1 (see annotated Fig. 4) in the bottom portion of the interposer 2 in an analogous location to Shibuya’s first metallization layer 10 (Fig. 2) which is located in the bottom portion of the interposer substrate 100. The purpose of adding Shioga’s first metal lines 32a to Shibuya’s first metallization layer 10 would be to provide horizontal electrical connections between a first set of “same potential” conductive columns (each conductive column being a stack of conductive elements 14, 12, 13, 31, 26, 23, 24 in Shibuya’s Fig. 2), where by “same potential” it is meant that this first set of conductive columns is meant to be supplied with a first voltage (i.e., electric potential) to be supplied to the primary electrode assembly (Chyi Liu’s 10A, 10B, 52A, 54A, and 62 in Fig. 13A) of the deep trench capacitors. It was known in the prior art of Shioga (Fig. 4) to use a plurality of “same potential” conductive columns 14a (“plural through electrodes 14a” comprising the stack of conductive elements 60a, 28a, 30a, 32a, 36a, 45a, 46a, 54a, 58a) to connect to the lower electrodes 20 of the capacitors 12 in order to achieve a combined capacitor (i.e., capacitors connected in parallel) having a larger capacitance than the individual capacitors 12.
Similarly, here the claimed “second metal lines” are represented by the addition of Shioga’s second metal lines 48 and/or 50 (Fig. 4) to Shibuya’s second metallization layer ML2 (see annotated Fig. 2) of the interposer substrate 100 to connect to one of the second metal interconnects 24, which may be called “a second metal interconnect of the plurality of second metal interconnects”, as claimed. Note that Shioga’s second metal lines 48 and 50 are located in the second metallization layer MET2 (see annotated Fig. 4) in the top portion of the interposer 2 in an analogous location to Shibuya’s second metallization layer ML2 (see annotated Fig. 2) which is located in the top portion of the interposer substrate 100. Note also that Shioga’s second metal lines 48 and 50 and second metal interconnects 58a–58c in the second metallization layer MET2 in the top portion of annotated Fig. 4 are analogous, respectively, to Chyi Lui’s second metal lines 64 and second metal interconnects (“pad region” of the “second metal line 64” ¶[0075]) in the top portion of Fig. 13A. The purpose of adding Shioga’s second metal lines 48 and/or 50 to Shibuya’s second metallization layer ML2 would be to provide horizontal electrical connections between a second set of “same potential” conductive columns (each conductive column being a stack of conductive elements 14, 12, 13, 31, 26, 23, 24 in Shibuya’s Fig. 2), where by “same potential” it is meant that this second set of conductive columns is meant to be supplied with a second voltage (i.e., electric potential) to be supplied to the complimentary electrode assembly (Chyi Liu’s 20A, 20B, 52B, 54B, and 64 in Fig. 13A) of the deep trench capacitors, wherein the second voltage is different from the first voltage supplied to the primary electrode assembly, thereby providing a potential difference between the primary and complimentary electrode assemblies of the deep trench capacitors as needed in order to store charge in the capacitors. It was known in the prior art of Shioga (Fig. 4) to use a plurality of “same potential” conductive columns 14b (“plural through electrodes 14b” comprising the stack of conductive elements 60b, 28b, 30b, 32b, 36b, 46b, 54b, 58b) to connect to the upper electrodes 24 of the capacitors 12 in order to achieve a combined capacitor (i.e., capacitors connected in parallel) having a larger capacitance than the individual capacitors 12.
Regarding claim 16, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, as shown above.
However, Shibuya (as modified by Lai and Chyi Lui) fails to teach that:
the interposer substrate further comprises a third metallization layer disposed between the second metallization layer and the substrate layer in the first direction;
the third metallization layer comprising a plurality of third metal interconnects each coupled to a via of a plurality of vias each coupled to a second metal interconnect of the plurality of second metal interconnects; and
each via of the plurality of vias coupled to a capacitor of the one or more capacitors.
In the same field of endeavor, Shioga teaches an IC package (Fig. 4, “electronic device” ¶[0029]) comprising an interposer 2 disposed between a package substrate 4 (“substrate 4” ¶[0088]) and a die 6 (“semiconductor integrated circuit device 6” ¶[0093]), wherein the interposer 2 comprises capacitors 12 (“thin-film capacitors 12” ¶[0047]), which are analogous to Shibuya’s IC package (Fig. 3), interposer substrate 100, package substrate 111, die 112, and capacitors 22, respectively.
Shioga’s interposer 2 comprises a first metallization layer MET1 and a second metallization layer MET2 (see annotated Fig. 4) that are located in a bottom portion and a top portion, respectively, of the interposer 2. These are analogous to Shibuya’s first metallization layer 10 and second metallization layer ML2 (see annotated Fig. 2), which are located in a bottom portion and a top portion, respectively, of the interposer substrate 100.
Shioga teaches that:
the interposer substrate 2 (“interposer 2” ¶[0090]) further comprises a third metallization layer (the layer comprising the “conductor plugs 46d” ¶[0066] in the “resin layer 42” ¶[0062]) disposed between the second metallization layer MET2 and the substrate layer SL (see annotated Fig. 4) in the first direction (vertical direction);
the third metallization layer comprising a plurality of third metal interconnects 46d (“conductor plugs 46d” ¶[0066]) each coupled to (by “interconnections 48” ¶[0067] as shown in Fig. 4) a via 14b of a plurality of vias 14b (“a plurality of the through-electrodes 14b formed of the partial electrodes 30b, 36b, 46b, 54b, 58b” ¶[0076]) each coupled to (as shown in Fig. 4) a second metal interconnect 58b of the plurality of second metal interconnects 58b; and
each via 14b of the plurality of vias 14b coupled to a capacitor 12 of the one or more capacitors 12 (as shown in Fig. 4, the plurality of vias 14b is electrically connected to the top electrodes 24 of the capacitors 12 through the interconnections 48, conductor plugs 46d, and conductive barrier film 45b).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shibuya’s interposer substrate 100, after the previously described modification in view of Lai and Chyi Liu that replaced Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC,
by including a plurality of vias similar to Shibuya’s leftmost conductive column (the stack of conductive elements 14, 12, 13, 31, 26, 23, 24 in Fig. 2), wherein each via is coupled to a second metal interconnect 24, and wherein each via is also coupled to Chyi Liu’s complimentary electrode assembly (20A, 20B, 52B, 54B, and 64 in Fig. 13A) of the deep trench capacitors UC in the same way that Shioga’s Fig. 4 shows a plurality of vias 14b each electrically coupled to a second metal interconnect 58b and also electrically coupled to the top electrodes 24 of capacitors 12;
by including a plurality of third metal interconnects in a third metallization layer located above the deep trench capacitors (which replaced Shibuya’s capacitors 22) and below the second metallization layer ML2 (expanding the substrate layer 20 as necessary to allow space for the third metallization layer), wherein the third metal interconnects each couple to the plurality of vias in the same way that Shioga’s third metal interconnects 46d couple to the plurality of vias 14b (through interconnections 48).
The reason for obviousness is that Shibuya’s interposer substrate 100 (Figs. 2–3) and Shioga’s interposer 2 (Fig. 4) are closely analogous devices, both being capacitive interposers comprising vias (i.e., vertical “through electrodes” or conductive columns), wherein a purpose of the vias is to provide external connection pads (on the tops and bottoms of the vias) whereby the first and second electrodes of the capacitors can be held at different electric potentials (thereby charging the capacitors). As shown by Shibuya’s Fig. 2 and Shioga’s Fig. 4, various arrangements are possible for the metal interconnects that electrically couple the “first electrodes” (e.g., the bottom electrodes of Shibuya’s or Shioga’s parallel plate capacitors, or Chyi Liu’s “primary electrode assembly”) to a first set of “like potential” vias; and likewise, various arrangements are possible for the metal interconnects that electrically couple the “second electrodes” (e.g., the top electrodes of Shibuya’s or Shioga’s parallel plate capacitors, or Chyi Liu’s “complimentary electrode assembly”) to a second set of “like potential” vias. Connecting a plurality of capacitors in parallel in this way obviously increases the amount of capacitance available to the capacitive interposer for reducing the voltage fluctuations delivered to an IC die attached to the top of the interposer. Furthermore, Chyi Liu’s deep trench capacitors, with their primary and complimentary electrode assemblies formed from the electrical connection of the odd- and even-numbered electrode layers, respectively, effectively increase the charge-storage area of the capacitors, thereby increasing the capacitance without increasing the horizontal extent of the capacitors so that a larger capacitance can be achieved in a given horizontal area of the interposer substrate. As stated by Chyi Liu: “Capacitors are employed in semiconductor chips for many applications such as power supply stabilization. Capacitors tend to take up a significant amount of device area, and thus, capacitors that can provide high capacitance with a small device footprint are desirable” ¶[0001]; and “Deep trench capacitors may be used as an integrated passive device to provide large capacitance, which can be used to stabilize a power supply and function as a noise filter in handheld devices” ¶[0024].
Regarding claim 17, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, as shown above.
However, Shibuya (as modified by Lai and Chyi Lui) fails to teach that:
the interposer substrate further comprises a third metallization layer disposed between the first metallization layer and the substrate layer in the first direction;
the third metallization layer comprising a plurality of third metal interconnects each coupled to a via of a plurality of vias each coupled to a second metal interconnect of the plurality of second metal interconnects; and
each via of the plurality of vias coupled to a capacitor of the one or more capacitors.
In the same field of endeavor, Shioga teaches an IC package (Fig. 4, “electronic device” ¶[0029]) comprising an interposer 2 disposed between a package substrate 4 (“substrate 4” ¶[0088]) and a die 6 (“semiconductor integrated circuit device 6” ¶[0093]), wherein the interposer 2 comprises capacitors 12 (“thin-film capacitors 12” ¶[0047]), which are analogous to Shibuya’s IC package (Fig. 3), interposer substrate 100, package substrate 111, die 112, and capacitors 22, respectively.
Shioga’s interposer 2 comprises a first metallization layer MET1 and a second metallization layer MET2 (see annotated Fig. 4) that are located in a bottom portion and a top portion, respectively, of the interposer 2. These are analogous to Shibuya’s first metallization layer 10 and second metallization layer ML2 (see annotated Fig. 2), which are located in a bottom portion and a top portion, respectively, of the interposer substrate 100.
Shioga teaches that:
the interposer substrate 2 (“interposer 2” ¶[0090]) further comprises a third metallization layer (the layer comprising the “conductive barrier film 45a” ¶[0066] in the “insulating barrier film 38” ¶[0053]) disposed between the first metallization layer MET1 and the substrate layer SL (see annotated Fig. 4) in the first direction (vertical direction);
the third metallization layer comprising a plurality of third metal interconnects 45a (“conductive barrier film 45a” ¶[0066] made of TaSiN, TiN, or TiAlN ¶[0064–0065], tantalum and titanium being metals) each coupled to (as shown in Fig. 4) a via 14a of a plurality of vias 14a (“a plurality of the through-electrodes 14a formed of the partial electrodes 30a, 36a, 46a, 54a, 58a” ¶[0076]) each coupled to (as shown in Fig. 4) a second metal interconnect 58a of the plurality of second metal interconnects 58a; and
each via 14a of the plurality of vias 14a coupled to a capacitor 12 of the one or more capacitors 12 (“The plural through-electrodes 14a are electrically connected to the lower electrodes 20 of the plural thin-film capacitors 12” ¶[0078]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Shibuya’s interposer substrate 100, after the previously described modification in view of Lai and Chyi Liu that replaced Shibuya’s parallel plate capacitors 22 with Chyi Liu’s deep trench capacitors UC,
by including a plurality of vias similar to Shibuya’s middle conductive column (the stack of conductive elements 14, 12, 13, 31, 26, 23, 24 in Fig. 2), wherein each via is coupled to a second metal interconnect 24, and wherein each via is also coupled to Chyi Liu’s primary electrode assembly (10A, 10B, 52A, 54A, and 62 in Fig. 13A) of the deep trench capacitors UC in the same way that Shioga discloses a plurality of vias 14a each electrically coupled to a second metal interconnect 58a and also electrically coupled to the bottom electrodes 20 of capacitors 12;
by including a plurality of third metal interconnects in a third metallization layer located below the deep trench capacitors (which replaced Shibuya’s capacitors 22) and above the first metallization layer 10, wherein the third metal interconnects each couple to the plurality of vias in the same way that Shioga’s third metal interconnects 45a couple to the plurality of vias 14a.
The reason for obviousness is that Shibuya’s interposer substrate 100 (Figs. 2–3) and Shioga’s interposer 2 (Fig. 4) are closely analogous devices, both being capacitive interposers comprising vias (i.e., vertical “through electrodes” or conductive columns), wherein a purpose of the vias is to provide external connection pads (on the tops and bottoms of the vias) whereby the first and second electrodes of the capacitors can be held at different electric potentials (thereby charging the capacitors). As shown by Shibuya’s Fig. 2 and Shioga’s Fig. 4, various arrangements are possible for the metal interconnects that electrically couple the “first electrodes” (e.g., the bottom electrodes of Shibuya’s or Shioga’s parallel plate capacitors, or Chyi Liu’s “primary electrode assembly”) to a first set of “like potential” vias; and likewise, various arrangements are possible for the metal interconnects that electrically couple the “second electrodes” (e.g., the top electrodes of Shibuya’s or Shioga’s parallel plate capacitors, or Chyi Liu’s “complimentary electrode assembly”) to a second set of “like potential” vias. Connecting a plurality of capacitors in parallel in this way obviously increases the amount of capacitance available to the capacitive interposer for reducing the voltage fluctuations delivered to an IC die attached to the top of the interposer. Furthermore, Chyi Liu’s deep trench capacitors, with their primary and complimentary electrode assemblies formed from the electrical connection of the odd- and even-numbered electrode layers, respectively, effectively increase the charge-storage area of the capacitors, thereby increasing the capacitance without increasing the horizontal extent of the capacitors so that a larger capacitance can be achieved in a given horizontal area of the interposer substrate. As stated by Chyi Liu: “Capacitors are employed in semiconductor chips for many applications such as power supply stabilization. Capacitors tend to take up a significant amount of device area, and thus, capacitors that can provide high capacitance with a small device footprint are desirable” ¶[0001]; and “Deep trench capacitors may be used as an integrated passive device to provide large capacitance, which can be used to stabilize a power supply and function as a noise filter in handheld devices” ¶[0024].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over patent application publication US 2010/0044089 A1 (by Shibuya et al., from the IDS, “Shibuya” hereafter) in view of patent application publication US 2023/0387330 A1 (by Lai et al., “Lai” hereafter), patent application publication US 2022/0199759 A1 (by Chyi Liu et al., “Chyi Liu” hereafter), and patent application publication US 2019/0051591 A1 (by Kabir et al., “Kabir” hereafter).
Regarding claim 18, Shibuya (as modified by Lai and Chyi Lui) teaches the IC package of claim 1, as shown above. However, Shibuya fails to teach that the IC package (Fig. 3) is
integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
In the same field of endeavor, Kabir teaches an IC package 1 (Fig. 1, “electronic assembly 1” ¶[0047]) comprising an interposer substrate 4 (“energy storing interposer device 4” ¶[0047]) arranged between a die 3 (“integrated circuit (IC) 3” ¶[0047]) and a package substrate 2 (“printed circuit board (PCB) 2” ¶[0047]), which are analogous to Shibuya’s IC package (Fig. 3), interposer substrate 100, die 112, and package substrate 111, respectively. Like Shibuya’s interposer substrate 100, Kabir’s interposer substrate 4 includes a capacitor 14 (“the nanostructure energy storage device 14 may be a nanostructure capacitor” ¶[0055]) for the purpose of improving the stability of DC voltage supplied to the die 3 (“the nanostructure energy providing device may be configured to store a relatively small amount of energy needed to, for instance, allow the nanostructure energy providing device to function as a de-coupling capacitor to act as an electrical short for RF frequency, limiting the disturbance on the DC lines from voltage harmonic(s) or transient variations” ¶[0030]). Kabir states that “the energy storage device (or the above-mentioned interposer device) may be comprised in an energy supply system of an electronic device (smart phone, laptop, sensor or any other handheld battery driven device) ¶[0034]”. Thus, Kabir teaches the claim limitation that an IC package with a capacitive interposer (such as the IC packages in Kabir’s Fig. 1 and Shibuya’s Fig. 3) may be used in a smart phone, a laptop (i.e., portable computer), or a computer (since a laptop is a type of computer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Shibuya’s IC package in a smart phone, laptop- (i.e., portable computer), or computer because Kabir discloses the use of a similar IC package comprising an interposer substrate which includes a capacitor, wherein the purpose of including the capacitor in the interposer substrate is to improve the stability of DC voltage supplied to a die that is coupled to the interposer substrate.
Claims 26–27 are rejected under 35 U.S.C. 103 as being unpatentable over patent application publication US 2010/0044089 A1 (by Shibuya et al., from the IDS, “Shibuya” hereafter) in view of patent application publication US 2023/0387330 A1 (by Lai et al., “Lai” hereafter), patent application publication US 2022/0199759 A1 (by Chyi Liu et al., “Chyi Liu” hereafter), and international (PCT) patent application publication WO 97/08748 A1 (by Kato et al., “Kato” hereafter, relying on machine translation included with the previous office action).
Regarding claim 26, Shibuya (as modified by Lai and Chyi Lui) teaches the method of claim 25, further comprising forming the one or more dies 112 comprises forming a plurality of die interconnects 114 (Fig. 3) on a surface S4 (see annotated Fig. 3) of the die 112.
However, Shibuya fails to teach that forming the one or more dies 112 comprises forming a plurality of dies 112 comprising forming a die wafer, comprising:
forming a semiconductor layer;
forming a third metallization layer adjacent to the semiconductor layer; and
forming the plurality of die interconnects 114 in the third metallization layer, the plurality of die interconnects 114 coupled to the semiconductor layer.
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In the same field of endeavor, Kato teaches that forming one or more dies 10 (“chip 10” ¶[0263]) comprises forming a plurality of dies 10 comprising forming a die wafer (“In the process of Figure 3(A), the wafer after probe testing is diced into chips 10” ¶[0272]), comprising:
forming a semiconductor layer 10 (“The chip 10 is made of a silicon semiconductor element” ¶[0263]);
forming a third metallization layer 11 (“large-scale integrated
circuit 11” ¶[0263]) adjacent to (as shown in Fig. 3A) the semiconductor layer 10; and
forming the plurality of die interconnects 12 (“connection pads 12” ¶[0263]) in the third metallization layer 11, the plurality of die interconnects 12 coupled to the semiconductor layer 10.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Shibuya’s die 112 (Fig. 3) may be one of a plurality of dies that are formed together as a die wafer comprising a semiconductor substrate (i.e., a silicon wafer) and a third metallization layer (i.e., an integrated circuit) because this is typically how integrated circuit dies are formed, as shown by the example of Kato wherein a die wafer (Fig. 3A) is cut or diced into a plurality of individual dies 10 (Fig. 3B). Furthermore, it would have been obvious that Shibuya’s die interconnects 114 are coupled to the third metallization layer and to the semiconductor substrate because such coupling is necessary for the interconnects to enable the flow of electric current to and from the integrated circuits within the dies.
Regarding claim 27, Shibuya (as modified by Lai, Chyi Lui, and Kato) teaches the method of claim 26, as shown above.
However, Shibuya fails to teach singulating the die wafer into the plurality of dies 112.
In the same field of endeavor, Kato teaches singulating a die wafer (Fig. 3A) into a plurality of dies 10 (Fig. 3B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Shibuya’s die 112 (Fig. 3) may be formed by singulating (i.e., cutting or dicing) a die wafer because this is typically how integrated circuit dies are formed, as shown by the example of Kato wherein a die wafer (Fig. 3A) is cut or diced into a plurality of individual dies 10 (Fig. 3B).
Claims 28–29 are rejected under 35 U.S.C. 103 as being unpatentable over patent application publication US 2010/0044089 A1 (by Shibuya et al., from the IDS, “Shibuya” hereafter) in view of patent application publication US 2023/0387330 A1 (by Lai et al., “Lai” hereafter), patent application publication US 2022/0199759 A1 (by Chyi Liu et al., “Chyi Liu” hereafter), international (PCT) patent application publication WO 97/08748 A1 (by Kato et al., “Kato” hereafter, relying on machine translation included with the previous office action), and patent application publication US 2020/0381391 A1 (by Yu et al., “Yu” hereafter).
Regarding claim 28, Shibuya (as modified by Lai, Chyi Lui, and Kato) teaches the method of claim 27, as shown above.
However, Shibuya fails to teach placing each of the plurality of dies 112 on the second surface S2 (see annotated Fig. 3) of the interposer substrate wafer (Fig. 7E) to form the plurality of IC packages. That is, Shibuya’s Fig. 3 only shows a single IC package consisting of a single die 112 attached to a single interposer substrate 100, and the forming step from Fig. 7E to Fig. 7F shows that the interposer substrate wafer of Fig. 7E is singulated into a plurality of interposer substrates 100 in Fig. 7F without first attaching a plurality of dies 112 to the interposer substrate wafer prior to singulation.
In the same field of endeavor, Kato teaches placing each die 10 of a plurality of dies 10 on a common substrate 70 (Fig. 3B, “large-area sheet substrate 70” ¶[0273]), but Kato fails to teach that this common substrate is an interposer substrate wafer.
In the same field of endeavor, Yu teaches the placement of each die 42 of the plurality of dies 42 (Fig. 2, “Package components 42 may be device dies comprising logic circuits, memory circuits, or the like. Accordingly, package components 42 are alternatively referred to as dies 42” ¶[0017]) on the top surface of an interposer substrate wafer 20 (“interposer wafer 20” ¶[0013]) to form a plurality of IC packages 54 (“individual packages 54” ¶[0023]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Shibuya’s forming step from Fig. 7E to Fig. 7F to instead place singulated dies 112 on the interposer substrate wafer of Fig. 7E before singulating the interposer substrate wafer into the plurality of interposer substrates 100 shown in Fig. 7F. This modification would predictably result in forming a plurality of IC packages with each IC package consisting of a single interposer substrate 100 attached to a die 112 as shown in Fig. 3. The reason for obviousness is that Yu shows that it was known in the prior art that a plurality of IC packages similar to the IC package of Shibuya’s Fig. 3 could be obtained by attaching the dies to the interposer substrate wafer prior to cutting the interposer substrate wafer into singulated interposer substrates.
Regarding claim 29, Shibuya (as modified by Lai, Chyi Lui, Kato, and Yu) teaches the method of claim 28, as shown above.
Yu further teaches singulating the interposer substrate wafer 20 between adjacent dies 42 of the plurality of dies 42 to provide the plurality of IC packages 54 (“a singulation process is performed to separate reconstructed wafer 48 into individual packages 54. The respective process is illustrated as process 206 in the process flow 200 shown in FIG. 26. The singulation process may be performed along the scribe lines 50 of interposer wafer 20. One of the resulting packages 54 (sometimes referred to as a CoW die or a CoW package) is illustrated in FIG. 3” ¶[0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that multiple copies Shibuya’s IC package of Fig. 3 (without the package substrate 111) would be obtained by (1) placing singulated dies 112 on the interposer substrate wafer of Fig. 7E; (2) singulating the interposer substrate wafer of Fig. 7E into individual interposer substrates 100, each of which would already have a die 112 attached from the previous step. Following this order of operations, which is a known manufacturing method as shown by Yu, provides a means of producing many copies of an IC package.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0215909 A1 (Chen et al.)
US 2011/0316147 A1 (Shih et al.)
US 2022/0361338 A1 (Hsu et al.)
US 2021/0118789 A1 (Chu et al.)
US 2018/0190582 A1 (Shih et al.)
US 8,062,968 B1 (Conn)
US 2022/0344250 A1 (Choi et al.)
Deep trench capacitors having four stacked electrodes wherein the first and third electrodes are electrically connected to a first contact, and the second and fourth electrodes are electrically connected to a second contact:
US 2020/0161235 A1 (Kwon et al.)—Fig. 3
US 2021/0202761 A1 (Cheng et al.)—Fig. 1
US 2021/0273042 A1 (Kim et al.)—Fig. 1 and ¶[0036]
US 2021/0391314 A1 (Jeng et al.)—Fig. 3 and ¶[0026–0027]
US 2022/0028825 A1 (Jeng et al.)—Fig. 3 and ¶[0025–0026]
US 2022/0367734 A1 (Kuo)—Fig. 7G and ¶[0066]
US 2023/0069774 A1 (Chang et al.)—Fig. 10A and ¶[0065, 0069]
US 2023/0060558 A1 (Chang)—Fig. 5A and ¶[0058]
US 2024/0047513 A1 (Su et al.)—Fig. 1I and ¶[0036]
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
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/A.J.M./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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