Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 23, 2026 has been entered.
Election/Restrictions
Claims 1-17 and 20 are pending in this application.
Applicant elected without traverse Invention I, Species A in the reply filed on April 22, 2025.
Claims 16-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 22, 2025.
The Examiner notes that claims 1-15 and 20 are examined and claims 16-17 are withdrawn.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2022-046753, filed on March 23, 2022.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 23, 2026. Claims 1 and 20 are amended. Claims 16-17 remain withdrawn. The Examiner notes that claims 1-15 and 20 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim (US 2021/0066346 A1).
With respect to claim 1, Lim teaches in Fig. 4C:
A semiconductor memory device (semiconductor device 100c) comprising:
a substrate (substrate 101);
a layer stack (stack including gate electrodes 130, insulating layers 120, and blocking insulating layers 146) in a first direction (vertical direction) above the substrate;
and a pillar (includes tunnel insulating layer 142, charge storage layers 143, blocking insulating layers 144, channel layer 140, and channel insulating layer 150) penetrating the layer stack in the first direction,
wherein the layer stack includes:
a first conductor (130); and
a first insulator (120) on an upper surface of the first conductor along the first direction,
the pillar includes a second insulator (combination of 142 and 143) extending along an extending direction of the pillar,
the second insulator includes a first part located in a first layer in which the first conductor is located, a second part located in a second layer in which the first insulator is located, and a third part located in the first layer and disposed at an interface between the first insulator and the first conductor, the first part including a portion thicker than the second part, and the third part including a portion thinner than the second part (see annotated Fig. 4C below), a diameter of the pillar in the first layer is larger than a diameter of the pillar in the second layer (pillar includes 142, 143, and 144 and diameter of pillar is larger in layer with conductive portions),
a thickness of the second insulator is greatest near a central part in the first direction of the first conductor (143 is thickest at center part of conductor), and
the first part overlaps the first conductor when viewed from a second direction intersecting the first direction (lateral direction in Fig. 4C).
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With respect to claim 2, Lim further teaches:
wherein the first part includes a portion thicker by 2 nm or more than the second part (first part includes charge storage layer 143, para 38 “A thickness T1 of the charge storage layer 143 in the x direction may be in a range of about 4 nanometers (nm) to about 6 nm”)
With respect to claim 3, Lim further teaches:
wherein a difference between a maximum thickness and a minimum thickness in the first part is 2 nm or more. (first part includes charge storage layer 143 and ends at the portion where 143 tapers away, para 38 “A thickness T1 of the charge storage layer 143 in the x direction may be in a range of about 4 nanometers (nm) to about 6 nm”)
With respect to claim 4, Lim further teaches:
wherein the first part includes a first region at or near a middle of the first part (region where 143 is thickest) in the first direction and a second region (region where 143 is tapering) at or near an end of the first part in the first direction, and the first region is thicker than the second region.
With respect to claim 5, Lim further teaches:
wherein the first region includes a portion thicker by 2 nm or more than the second region. (143 is 4 to 6 nm wide. The second region includes the portion where 143 tapers away which is more than 2 nm thinner than the thickest region)
With respect to claim 6, Lim further teaches:
wherein the first region (region that includes thickest portion of 143) includes a portion thicker than the second part (thinner portion of 142),
and the second part (portion of 142 and 143 where 143 tapers away that includes the thicker part of 142) includes a portion thicker than the second region (thin portion of 142).
With respect to claim 9, Lim further teaches:
wherein the second insulator is a charge storage layer (second insulator includes 143 which is a charge storage layer).
With respect to claim 10, Lim further teaches:
wherein the second insulator contains silicon nitride. (para. 36 “the charge storage layers 143, and may include, for example, silicon oxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), silicon oxynitride (SiON), or a combination thereof.”)
With respect to claim 11, Lim further teaches:
wherein the first conductor is a word line (gate electrode 130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 7, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2017/0271527 A1) in view of Yoo (US 2015/0333186 A1).
With respect to claim 1, Higuchi teaches in Figs. 3 and 17:
A semiconductor memory device comprising:
a substrate (Fig. 3, substrate 11);
a layer stack (conductive layers 14 and insulating layers 15) in a first direction (up/down) above the substrate (11);
and a pillar (pillar 13, not labeled in Fig. 17, includes 20, 30, 40, and 50) penetrating the layer stack (14 and 15) in the first direction (up/down),
wherein the layer stack includes:
a first conductor (conductive layers 14);
and a first insulator (insulator layers 15) on an upper surface of the first conductor along the first direction,
the pillar (13, comprising 20, 30, 40, and 50) includes a second insulator (charge-storing film 40 which includes 41 and 42) extending along an extending direction (up/down) of the pillar (13),
the second insulator (40) includes a first part located in a first layer in which the first conductor (para. 16 “second portions facing the conductive layers”) is located, a second part located in a second layer in which the first insulator is located (para. 16 “first portions facing the insulating layers”) (see annotated Fig. 17 below),
the first part including a portion thicker than the second part (para. 16 “the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers),
and a diameter of the pillar (13 including 20, 30, 40, and 50) in the first layer (14) is larger than a diameter of the pillar in the second layer (15) (see Fig. 17).
a thickness of the second insulator is greatest near a central part in the first direction of the first conductor (40 has its maximum thickness at the elevation of the conductor),
and the first part overlaps the first conductor when viewed from a second direction intersecting the first direction (overlaps the conductor layer in the lateral direction).
Higuchi fails to teach:
and a third part located in the first layer and included in a boundary between the first insulator and the first conductor
and the third part including a portion thinner than the second part,
Yoo teaches in Fig. 1 (see annotated Fig. 1 of Yoo below)
the second insulator (multifunction layer 141 which includes charge storage patterns 141_M and 141_D and blocking insulation patterns 141_O) includes a first part located in a first layer in which the first conductor (conductive pattern 171) is located, a second part located in a second layer in which the first insulator is located (interlayer insulating pattern 111E),
the first part including a portion thicker than the second part (see annotated Fig. 1 of Yoo below),
and a third part located in the first layer and dispose at an interface between the first insulator and the first conductor (see annotated Fig. 1 below. Third part is located in the first layer in line with the overlap of the conductive and insulating patterns.)
and the third part including a portion thinner than the second part (see annotated Fig. 1 of Yoo below),
Higuchi discloses the claimed invention except for the shape and dimensions of the second insulating layer. Yoo teaches that it is known to include a second insulating layer with parts that have dimensions described above. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Higuchi as taught by Yoo, since Yoo states para. 30 that such a modification would prevent the vertical movement of charges along the multifunction layer. See MPEP 2144.
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With respect to claim 4, Higuchi further teaches:
wherein the first part includes a first region at or near a middle of the first part in the first direction and a second region at or near an end of the first part in the first direction,
and the first region is thicker than the second region. (see Fig. 17 (cropped) below)
With respect to claim 7, Higuchi further teaches:
wherein the first region includes a portion closer to the first conductor (14) than the second region is. (see Fig. 17 (cropped) below)
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With respect to claim 9, Higuchi further teaches:
wherein the second insulator (charge-storing film 40 which includes 41 and 42) is a charge storage layer.
With respect to claim 10, Higuchi further teaches:
wherein the second insulator (40, including 41 and 42) contains silicon nitride (para 52 “the first-composition film 41 may include, but are not limited to, silicon nitride (SiN)”, para. 53 “The second-composition film 42 may be formed of, but not limited to, silicon nitride (SiN)”.)
With respect to claim 11, Higuchi further teaches:
wherein the first conductor (14) is a word line (para. 33 “The plurality of conductive layers 14 forms the plurality of word lines WL”).
Claims 2-5 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2017/0271527 A1) and Yoo (US 2015/0333186 A1) as applied to independent claim 1 above and in view of Ozawa (US 2009/0294828 A1)
With respect to claim 2, Higuchi/Yoo teaches all limitations of claim 1 upon which claim 2 depends. Higuchi/Yoo is silent to the dimensions of the insulator layer and fails to teach:
wherein the first part includes a portion thicker by 2 nm or more than the second part.
Ozawa teaches in Fig. 25:
wherein the first part (part of 207 in layer 203) includes a portion thicker by 2 nm or more than the second part (part of 207 in layer 202). (see annotated Fig. 25 (cropped below). Para. 211 teaches “the side surface of the through hole 204, the silicon film 203 is set back by approximately 20 nm relative to the silicon oxide film 202” the jog portion of 207 is 20 nm thicker than the second part, which is 5 nm thick per para. 211”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ozawa into the device of Higuchi/Yoo to include a portion thicker by 2 nm in the second insulating layer. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner set forth above for the purpose of forming a through hole with a corrugated surface (para. 209 of Ozawa) and/or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
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With respect to claim 3, Higuchi/Yoo teaches all limitations of claim 1 upon which claim 3 depends. Higuchi/Yoo is silent to the dimensions of the insulator layer and fails to teach:
wherein a difference between a maximum thickness (jog portion labeled “maximum thickness in annotated and cropped Fig. 25 above), with total thickness of 25 nm) and a minimum thickness (labeled “minimum thickness” in annotated Fig. 25 above, total thickness of 5 nm) in the first part is 2 nm or more (difference between thicknesses is 20 nm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ozawa into the device of Higuchi/Yoo to include a portion thicker by 2 nm in the second insulating layer. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner set forth above for the purpose of forming a through hole with a corrugated surface (para. 209 of Ozawa) and/or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
With respect to claim 5, Higuchi/Yoo teaches all limitations of claim 4 upon which claim 5 depends. Higuchi/Yoo is silent to the dimensions of the insulator layer and fails to teach:
wherein the first region includes a portion thicker by 2 nm or more than the second region.
Ozawa teaches in Fig. 25:
wherein the first region (see annotated Fig. 25 above, region labeled “maximum thickness” with thickness of 25 nm that is closer to the middle of the region within layer 23 than the region labeled “minimum thickness”) includes a portion thicker by 2 nm or more (difference of 20 nm) than the second region (region labeled “minimum thickness in annotated Fig. 25 above, thickness of 5 nm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ozawa into the device of Higuchi/Yoo to include a portion thicker by 2 nm in the second insulating layer. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner set forth above for the purpose of forming a through hole with a corrugated surface (para. 209 of Ozawa) and/or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
With respect to claim 12, Higuchi/Yoo teaches all limitations of claim 1 upon which claim 12 depends. Higuchi/Yoo further teaches:
wherein the pillar (13, including 20, 30, 40, and 50) further includes:
a first semiconductor (semiconductor body 20) inward of the second insulator (40) and extending along the extending direction (up/down) of the pillar;
a third insulator (tunnel insulating film 30) between the first semiconductor (20) and the second insulator (40) and extending along the extending direction (up/down) of the pillar;
and a fourth insulator (blocking insulating film 50) between the second insulator (40) and the layer stack (14 and 15) and extending along the extending direction (up/down) of the pillar,
Higuchi/Yoo fails to teach:
and a portion of the first semiconductor in the first layer Is thicker than a portion of the first semiconductor in the second layer.
Ozawa teaches:
and a portion of the first semiconductor (silicon pillar 209) in the first layer (layer 203) Is thicker than a portion of the first semiconductor (209) in the second layer (layer 202) (para. 211 “In the through hole 204, the portion made of the silicon oxide film 202 has a diameter of e.g. approximately 60 nm, and the portion made of the silicon film 203 has a diameter of e.g. approximately 100 nm.” Silicon pillar 209 fills in the center of the through hole 204 and the thicker portion can be seen in Fig. 25.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ozawa into the device of Higuchi/Yoo to a portion of semiconductor layer that is thicker than a second portion of the semiconductor layer. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner set forth above for the purpose of forming a through hole with a corrugated surface (para. 209 of Ozawa) and/or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
With respect to claim 13, Higuchi/Yoo teaches all limitations of claim 1 upon which claim 13 depends. Higuchi/Yoo further teaches:
wherein the pillar (13, including 20, 30, 40, and 50) further includes:
a third insulator (tunnel insulating film 30) inward of the second insulator (40) and extending along the extending direction (up/down) of the pillar;
Higuchi/Yoo fails to teach:
and a region of the third insulator in the first layer that is located at or near a middle of the third insulator thereof in the first direction is thicker than a region of the third insulator in the first layer that is located at or near an end of the third insulator in the first direction.
Ozawa teaches in Fig. 25:
and a region (thicker yellow box in annotated Fig. 25 above) of the third insulator (tunnel dielectric 208) in the first layer (203) that is located at or near a middle (closer to middle than smaller yellow box in annotated Fig. 25 above) of the third insulator (208) thereof in the first direction (up/down) is thicker (25 nm) than a region (smaller yellow box in annotated Fig. 25 above) of the third insulator (208) in the first layer (203) that is located at or near an end of the third insulator in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ozawa into the device of Higuchi/Yoo to a portion of third insulating layer that is thicker than a second portion of the third insulating layer. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner set forth above for the purpose of forming a through hole with a corrugated surface (para. 209 of Ozawa) and/or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)).
With respect to claim 14 Higuchi/Yoo/Ozawa further teaches:
wherein the third insulator is a tunnel insulating film (para. 216 of Ozawa “208 serving as a tunnel dielectric layer,” tunnel insulating film 30 of Higuchi.)
With respect to claim 15, Higuchi/Yoo/Ozawa further teaches:
wherein the third insulator contains silicon oxide (para. 216 “a silicon oxide layer 208” of Ozawa, para. 41 “Examples of the tunnel insulating film 30 may include, but are not limited to, silicon oxide (SiO.sub.2)” of Higuchi).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Higuchi in view of Yoo and Ozawa as explained above.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2017/0271527 A1) and Yoo (US 2015/0333186 A1) as applied to claim 4 above and in view of Lee (US 2016/0225786 A1).
With respect to claim 6, Higuchi/Yoo teaches all limitations of claim 4 upon which claim 6 depends. Higuchi/Yoo further teaches:
wherein the first region (see annotated Fig. 17(cropped) above) includes a portion thicker than the second part (see annotated Fig. 17 above),
Higuchi/Yoo fails to teach:
and the second part includes a portion thicker than the second region.
Lee teaches in Fig. 5D:
and the second part (CR2) includes a portion thicker (para 78-79, “the third regions CR3 may be defined as a portion that is positioned adjacent to the overlapping portions P2a of the first blocking insulating region BCL1 and has a thickness less than that of the first and second regions CR1 and CR2.”) than the second region (CR3a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee into the device of Higuchi/Yoo include a thinned portion of the charge storage layer that is thinner than the portions in the layered regions. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner set forth above for the purpose of increasing the integration of a memory device by reducing the area occupied by a single memory cell (para 3 of Lee).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2017/0271527 A1) and Yoo (US 2015/0333186 A1) as applied to independent claim 1 above and in view of Taekyung (US 2015/0060992 A1).
With respect to claim 8, Higuchi/Yoo teaches all limitations of independent claim 1 upon which claim 8 depends. Higuchi/Yo/o fails to teach:
wherein the first conductor is thicker than the first insulator in the first direction.
Taekyung teaches:
wherein the first conductor (word lines WL1 to WL8 with thickness Lg) is thicker (para 96, “the ratio of the thickness Lg to the space Ls (Lg/Ls) may be in the range of about 1.2 to 1.4”) than the first insulator (integrate dielectric layer 150 with thickness Ls) in the first direction (direction of the stack).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Taekyung into the device of Higuchi/Yoo so that conductive layers that are thicker than the first insulator in the first direction. The ordinary artisan would have been motivated to modify Higuchi/Yoo in the manner for the purpose of tuning the resistance and breakdown voltage of the word lines (para 111-112 of Taekyung).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2019/0198509 A1) in view of Fujii (US 2020/0075622 A1).
With respect to claim 20, Kim teaches in Fig. 16:
semiconductor memory device (construction 10) comprising:
a substrate (base 22);
a layer stack (stack 12) in a first direction above the substrate; and
a pillar (channel material pillar that includes insulative material 48, channel material 46, tunneling materials 40, 42, and 44) penetrating the layer stack in the first direction, wherein the layer stack includes:
a first conductor (conductive material 58); and
a first insulator (second material 20, which is insulative per para. 22) on an upper surface of the first conductor along the first direction,
the pillar includes:
a second insulator (insulative material 48) extending along an extending direction of the pillar;
a semiconductor layer (channel material 46) covering a circumference of the second insulator; and
a stacked film (tunneling layers 40, 42, and 44) covering a side surface of the semiconductor layer at a height of the layer stack, and
a diameter of a first part of the second insulator at a height of the first conductor is larger than a diameter of a part of the second insulator at a height of the first insulator, as viewed in the first direction (see Fig. 16, 48 is thicker in conductive layers,
Kim fails to teach:
and the first part includes a void.
Fujii teaches:
and the first part (portion of core layer 30 at the level of the word lines WL) includes a void (void VD).
Kim discloses the claimed invention except for the void within the first part of the insulative layer. Fujii discloses that it is known in the art to provide a void within the insulative layer in a memory pillar. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a void within the insulative layer for the purpose of having flexibility in manufacturing processes that allows for a method of forming the core layer that includes a void. See MPEP 2144.
Response to Arguments
Applicant’s arguments, see page 7 and 8, filed January 23, 2026, with respect to claim objections and 112 rejections have been fully considered and are persuasive. The claim objections and 112 rejections have been withdrawn.
Applicant’s arguments with respect to claims 1-15 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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