Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: 1) the term “conductor” which, despite being used throughout multiple claims, lacks any real definition within the specification itself, and 2) the term “contact” which is used broadly without any real definition or clarity to describe a variety of features throughout the specification.
Claim Rejections - 35 USC § 112
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claims 1-4, 6-9, and 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the claims make use of the term “conductor”, which fails to properly point out and distinctly claim any subject matter described in the specification. Despite the fact that the claimed invention discloses up to ten different conductors throughout the claims mentioned, the specification itself only labels one feature as a “conductor”, that being the contact LI as seen in [0055] and Fig. 4; the word “contact” is also used to describe other features, but there is no indication that every contact is a conductor, nor any indication as to which contact, if any, line up with the specific conductors disclosed (first conductor, second conductor, etc.). For the sake of further analysis, the term “conductor” will be interpreted to mean any feature comprising a conductive material or exhibiting conductive properties/characteristics.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the claim makes use of the terms “first region” and “second region”, which fail to properly point out and distinctly claim any subject matter described in the specification. As best shown in Fig. 3, the substrate as described in claim 1 is shown to consist of at least 4 regions: CR, C3T, WR, and ER. Neither claim 1 nor the specification explicitly label any of these areas as the “first region” and “second region”. For the sake of further analysis, it is interpreted that the term “first region” corresponds to the innermost region CR, and the term “second region” corresponds to the area surrounding CR, comprising C3T, WR, and/or ER.
Claims 1 and 8-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the claims use the term “layer stack" in such a way as to fail to particularly point out and distinctly claim the subject matter as described in the specification. Although there is a layer stack SLP mentioned throughout the specification, this seems to contradict with the term’s use throughout the claims, such as in claim 10 which describes the “layer stack” as including a plurality of word lines; these word lines WL0-WL7, shown in multiple figures including Fig. 9, are never shown within the layer stack SLP, but rather above said stack and within the insulating layer 36/36b. For the sake of further analysis, the term “layer stack” will thus be interpreted as an area comprising a plurality of word lines.
Claim Rejections - 35 USC § 102
Claim(s) 1-6, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Ito (PGPub No. 20210066329).
Regarding claim 1, Ito teaches a substrate including a substrate including a first region and a second region that surrounds the first region in a first direction (Fig. 3 and [0049-50] point to a planar layout of a semiconductor storage device comprising a core region CR (first region) provided in a central portion of a semiconductor substrate 20 and surrounded by a wall region WR, a kerf region KR, a contact region C3T, and an end region ER (second region).); a layer stack provided above the substrate in the first region as viewed in a first direction (Fig. 6, [0064], and [0079] point to a memory area MA when viewed in the x-direction (first direction), which occupies most of the core region CR (first region), comprising a plurality of conductor layers 32 (layer stack) provided above a semiconductor substrate 20.); a first conductor provided on the substrate in the second region and extending in the first direction (Fig. 9 and [0101-108] point to a cross-section of the wall region WR and end region ER (second region) comprising a crack stopper CS2 consisting of contact C1W (first conductor) located on the semiconductor substrate 20.); a second conductor provided on the first conductor and extending in a direction approaching the second region from the first region (Id. points to crack stopper CS2 further comprising a contact C2W (second conductor). The term “extending in a direction approaching the second region from the first region” is interpreted to mean the same as the width of C2W.); and a third conductor provided on the second conductor and extending in the first direction, an upper surface of the third conductor reaching at least a height of an upper surface of the layer stack (Figs. 9, 17 & 18, and [0101-108] point to crack stopper CS2 further comprising a contact C3W (third conductor), which has a height surpassing the upper surface of the plurality of conductor layers 32 (layer stack).), wherein the third conductor is positioned farther from the first region than the first conductor (Fig. 9 points to contact C3W (third conductor) having a larger width than contact C1W (first conductor).), the third conductor is not opposed to the first conductor in the first direction (Id. points to contact C3W (third conductor) located above contact C1W (first conductor) such that neither contact interferes/opposes each other in the x-direction (first direction).), and a set of the first conductor, the second conductor, and the third conductor surrounds the first region as viewed from above (Fig. 4 points to crack stopper CS2 (the first conductor, the second conductor, and the third conductor) in a planar layout, showing said crack stopper surrounding the core region CR (first region)).
Regarding claim 2, Ito teaches wherein the set of the first conductor, the second conductor, and the third conductor includes a portion extending in a second direction and a portion extending in a third direction, and thereby surrounds the first region as viewed from above, the second direction intersecting the first direction, and the third direction intersecting the first and second directions (Figs. 4 and 9 points to crack stopper CS2 (the first conductor, the second conductor, and the third conductor) extending in an x-direction (first direction), y-direction (second direction), and a z-direction (third direction) and surrounding the core region CR (first region)).
Regarding claim 3, Ito teaches a fourth conductor extending in the first direction and positioned closer to the first region than the third conductor, wherein the fourth conductor does not abut on the second conductor and the third conductor, is provided above the second conductor in the first direction, and surrounds the first region as viewed from above (Figs. 4 and 16-18 point to a contact C3 (fourth conductor) located in the region C3T, which surrounds the core region CR (first region).).
Regarding claim 4, Ito teaches wherein the substrate includes a first insulator provided in a region that is below a region between the first conductor and a region below the third conductor and that includes an upper surface of the substrate (Figs. 13-18 and [0077-0082] point to an unlabeled interlayer insulating film (first insulator) encompassing the upper surface of the semiconductor substrate 20 and all other areas above it.).
Regarding claim 5, Ito teaches wherein the first insulator includes a portion extending in a second direction and a portion extending in a third direction, and thereby surrounds the first region as viewed from above, the second direction intersecting the first direction, and the third direction intersecting the first and second directions (Figs. 13-18 and [0077-0082] point to an unlabeled interlayer insulating film encompassing the upper surface of the semiconductor substrate 20 and all other areas above it. By extension, this unlabeled interlayer insulating film also includes an area surrounding the core region CR (first region) and extending in the x-direction (first direction), y-direction (second direction, and z-direction (third direction). It is interpreted as obvious that this unlabeled interlayer insulating film is meant to act as an insulator, as if this is not the case then the multiple conductive components throughout the invention, such as the plurality of conductive layer 32, would collectively interfere with each other and likely cause damage.).
Regarding claim 6, Ito teaches a fifth conductor provided farther from the first region than the first conductor and extending in the first direction, wherein the fifth conductor does not abut on the second conductor, the fifth conductor is opposed to the third conductor in the first direction, and the fifth conductor surrounds the first region as viewed from above (Fig. 9 points to a dividing portion DP including a contact C3L (fifth conductor) located in the end region ER (provided farther from the first region than the first conductor) and parallel to the contact C3W in crack stopper CS2 (opposed to the third conductor). Fig. 4 further points to said dividing portion DP surrounding the core region CR (first region).).
Regarding claim 8, Ito teaches a first conductive layer provided on the layer stack and a pillar penetrating the layer stack in the first direction, wherein an upper portion of the pillar is included in the first conductive layer (Fig. 6 points to a conductor layer 33 (first conductive layer) formed on a plurality of conductor layers 32 (layer stack), and memory pillars MP (pillar).), and the upper surface of the third conductor reaches at least a height of a lower surface of the first conductive layer (Figs. 9, 17 & 18, and [0101-108] point to crack stopper CS2 further comprising a contact C3W (third conductor), which has a height surpassing memory pillar MP (pillar; first conductive layer).).
Regarding claim 10, Ito teaches wherein the layer stack includes a plurality of word lines aligned in the first direction, and a memory cell is formed at an intersection of a pillar penetrating the word lines in the first direction and one of the word lines (Fig. 6 and [0079] point to word lines WL0 to WL7 (a plurality of word lines) and a memory pillar MP that intersects said word lines. It is considered obvious to one of ordinary skill in the art that such a structure would form a memory cell.).
Claim Rejections - 35 USC § 103
Claim(s) 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (PGPub No. 20210066329).
Regarding claim 11, Ito teaches a sixth conductor provided on the substrate in the second region and extending in the first direction (Fig. 9 and [0101-108] point to a cross-section of the wall region WR and end region ER (second region) comprising a crack stopper CS1 consisting of contact C1W (sixth conductor) located on the semiconductor substrate 20.); a seventh conductor provided on the sixth conductor and extending in a direction approaching the first region from the second region (Id. points to crack stopper CS1 further comprising a contact C2W (seventh conductor). The term “extending in a direction approaching the second region from the first region” is interpreted to mean the same as the width of C2W.); and an eighth conductor provided on the seventh conductor and extending in the first direction, an upper surface of the eighth conductor reaching at least the height of the upper surface of the layer stack, the eighth conductor being positioned farther from the first region than the third conductor, wherein the sixth conductor is positioned farther from the first region than the eighth conductor, the eighth conductor is not opposed to the sixth conductor in the first direction (Id. points to crack stopper CS1 further comprising a contact C3W (eighth conductor), which has a height surpassing the upper surface of the plurality of conductor layers 32 (layer stack). Based on the broad definition associated with the term “conductor”, it is considered obvious that one of ordinary skill in the art could alternatively determine that the “sixth conductor” includes not only contact C1W but also conductor layer 26 and/or layer 27, which each have a larger width than the previously mentioned contact C3W (eighth conductor) extending away from the core region CR (the sixth conductor is positioned farther from the first region).), and a set of the sixth conductor, the seventh conductor, and the eighth conductor surrounds the first region as viewed from above (Fig. 4 points to the crack stopper CS1 surrounding the core region CR (first region).).
Regarding claim 12, Ito teaches wherein the eighth conductor is positioned farther from the first region than the third conductor by a first distance, the third conductor is positioned farther from the first region than the first conductor by a second distance, the sixth conductor is positioned farther from the first region than the eighth conductor by a third distance, and the first distance, the second distance, and the third distance are substantially identical in length (Figs. 4 and 9 point to a crack stopper CS2 comprising contacts C1W (first conductor) and C3W (third conductor), and a crack stopper CS1 comprising contacts C1W (sixth conductor) and C3W (eighth conductor). Fig. 6 points to a configuration of contacts C0-C2, including a C0-C2 structure that places the contacts C1 and C2 above but slightly offset from contact C0. In light of this, it is interpreted that one of ordinary skill in the art would find it obvious to at least attempt to apply the structure described in Fig. 6 to the one described in Figs. 4 and 9, where the contacts comprising crack stoppers CS1 and CS2 are formed in a similar offset shape to the one shown by contacts C0-C2. It is also considered obvious that the distances created by these offset shapes (first distance; second distance; third distance) would be substantially identical in order to streamline the manufacturing process via uniformity.).
Regarding claim 13, Ito teaches wherein the set of the first conductor, the second conductor, and the third conductor includes a portion extending in a second direction and a portion extending in a third direction, and thereby surrounds the first region as viewed from above, the second direction intersecting the first direction, and the third direction intersecting the first and second distances, and the set of the sixth conductor, the seventh conductor, and the eighth conductor includes a portion extending in the second direction and a portion extending in the third direction, and thereby surrounds the first region as viewed from above (Figs. 4 and 9 points to crack stopper CS2 (the first conductor, the second conductor, and the third conductor) and crack stopper CS1 (the sixth conductor, the seventh conductor, and the eighth conductor) each extending in an x-direction (first direction), y-direction (second direction), and a z-direction (third direction) and surrounding the core region CR (first region).).
Regarding claim 14, Ito teaches a plurality of fifth conductors extending in the first direction between the first conductor and the sixth conductor, wherein the fifth conductors do not abut on each other, and do not abut on the first conductor, the second conductor, the sixth conductor, and the seventh conductor, the fifth conductors are not positioned below a region between the third conductor and the eighth conductor, and the fifth conductors surround the first region as viewed from above (Figs. 4 and 9 point to a crack stopper CS2 comprising contacts C1W (first conductor), C2W (second conductor), and C3W (third conductor), and a crack stopper CS1 comprising contacts C1W (sixth conductor), C2W (seventh conductor), and C3W (eighth conductor). Fig. 6 points to a configuration of contacts C0-C2, including a C0-C2 structure that places the contacts C1 and C2 above but slightly offset from contact C0, and an additional contact C0 placed in-between the configuration on its own. In light of this, it is interpreted that one of ordinary skill in the art would find it obvious to at least attempt to apply the structure described in Fig. 6 to the one described in Figs. 4 and 9, where the contacts comprising crack stoppers CS1 and CS2 are formed in a similar offset shape to the one shown by contacts C0-C2, and an additional contact C0 (plurality of fifth conductors) is formed in between said crack stoppers and surrounds the core region CR (first region) as well.).
Regarding claim 15, Ito teaches wherein the set of the first conductor, the second conductor, and the third conductor includes a portion extending in a second direction and a portion extending in a third direction, and thereby surrounds the first region as viewed from above, the second direction intersecting the first direction, and the third direction intersecting the first and second directions, the set of the sixth conductor, the seventh conductor, and the eighth conductor includes a portion extending in the second direction and a portion extending in the third direction, and thereby surrounds the first region as viewed from above (Figs. 4 and 9 points to crack stopper CS2 (the first conductor, the second conductor, and the third conductor) and crack stopper CS1 (the sixth conductor, the seventh conductor, and the eighth conductor) each extending in an x-direction (first direction), y-direction (second direction), and a z-direction (third direction) and surrounding the core region CR (first region).), and each of the fifth conductors includes a portion extending in the second direction and a portion extending in the third direction, and thereby surrounds the first region as viewed from above (Fig. 6 points to a configuration of contacts C0-C2, including a C0-C2 structure that places the contacts C1 and C2 above but slightly offset from contact C0, and an additional contact C0 placed in-between the configuration on its own. it is interpreted that one of ordinary skill in the art would find it obvious to at least attempt to apply the structure described in Fig. 6 to the one described in Figs. 4 and 9, where the contacts comprising crack stoppers CS1 and CS2 are formed in a similar offset shape to the one shown by contacts C0-C2, and an additional contact C0 (fifth conductors) is formed in between said crack stoppers and surrounds the core region CR (first region) as well.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to form an embodiment alternative to the one already anticipated by Ito, such that the structures created by the first-third conductors and sixth-eighth conductors, respectively, are altered to create slightly offset shapes and allow additional “fifth conductors” to be formed underneath said shapes in order to improve efficiency through staggered cell placement while avoiding parasitic leakage and/or signal interference.
Regarding claim 16, Ito teaches wherein the first conductor, the sixth conductor, and the fifth conductors are arranged at substantially equal intervals in a second direction intersecting the first direction (Figs. 4 and 9 point to a crack stopper CS2 comprising a contact C1W (first conductor) and a crack stopper CS1 comprising contacts C1W (sixth conductor). Fig. 6 points to a configuration of contacts C0-C2, including a C0-C2 structure that places the contacts C1 and C2 above but slightly offset from contact C0, and an additional contact C0 placed in-between the configuration on its own. In light of this, it is interpreted that one of ordinary skill in the art would find it obvious to at least attempt to apply the structure described in Fig. 6 to the one described in Figs. 4 and 9, where the contacts comprising crack stoppers CS1 and CS2 are formed in a similar offset shape to the one shown by contacts C0-C2, and an additional contact C0 (fifth conductors) is formed in between said crack stoppers and surrounds the core region CR (first region) as well. By extension, it is considered obvious that one or ordinary skill in the art would arrange the first, sixth, and fifth conductors at substantially equal intervals along the y-direction (second direction) so as to ensure uniformity.).
Regarding claim 17, Ito teaches a fourth conductor extending in the first direction and positioned closer to the first region than the third conductor; and a ninth conductor extending in the first direction and positioned farther from the first region than the eighth conductor, wherein the fourth conductor does not abut on the second conductor and the third conductor, the ninth conductor does not abut on the seventh conductor and the eighth conductor, the fourth conductor is provided above the second conductor in the first direction, the ninth conductor is provided above the seventh conductor in the first direction, the fourth conductor surrounds the first region as viewed from above, and the ninth conductor surrounds the first region as viewed from above (Figs. 4 and 16-18 point to a contact C3 (fourth conductor) located in the region C3T, and a contact C3L (ninth conductor) located in the end region ER, both of which surround the core region CR (first region).
Regarding claim 18, Ito teaches an insulator provided on the substrate (Figs. 13-18 and [0077-0082] point to an unlabeled interlayer insulating film (insulator) provided on the semiconductor substrate 20.); and a tenth conductor partially provided on the second insulator, the tenth conductor not being provided below a region between the third conductor and the eighth conductor (Id. points to the unlabeled interlayer insulating film (second insulator) reaching a maximum height equal to the upper surface of contacts C3W (third conductor; eighth conductor). Fig. 9 points to a contact V0W (tenth conductor) directly in contact with and extending away from contacts C3W and by extension the unlabeled interlayer insulating film (partially provided on the second insulator).).
Regarding claim 19, Ito teaches wherein the substrate includes an insulator provided in a region that is below a region between the third conductor and the eighth conductor and that includes an upper surface of the substrate (Figs. 13-18 and [0077-0082] point to an unlabeled interlayer insulating film (insulator) encompassing the upper surface of the semiconductor substrate 20 and all other areas above it).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ito (PGPub No. 20210066329) in further view of Watanabe (PGPub No. 20220077089).
Regarding claim 7, Ito teaches a first insulating layer provided on the substrate (Figs. 13-18 and [0077-0082] point to an unlabeled interlayer insulating film encompassing the upper surface of the semiconductor substrate 20 (first insulating layer) and all other areas above it.); and a second insulating layer provided on the first insulating layer (Id. points to an unlabeled interlayer insulating film encompassing the upper surface of the semiconductor substrate 20 and all other areas above it (second insulating layer).).
Ito fails to teach wherein the third conductor includes a first bonding pad provided in the first insulating layer and a second bonding pad provided in the second insulating layer, and an upper surface of the first bonding pad abuts on a bottom surface of the second bonding pad.
Watanabe teaches wherein the third conductor includes a first bonding pad provided in the first insulating layer (Fig. 6 points to pads 21A (first bonding pad) positioned in the insulating film 25 (first insulating layer).) and a second bonding pad provided in the second insulating layer (Fig. 5 points to pads 26A (second bonding pad) positioned in the insulating film 29 (second insulating layer).), and an upper surface of the first bonding pad abuts on a bottom surface of the second bonding pad (Fig. 1 and [0057] point to a semiconductor storage device comprising the pads 21A (first bonding pad) and 26A (second bonding pad) being bonded to each other.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Ito and Watanabe, such that the third conductor includes two bonding pads coupled to each other in order to allow two chips to communicate with each other by creating a common electrical path.
Claim(s) 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (PGPub No. 20210066329) in further view of Akada (PGPub No. 20200185340).
Regarding claim 9, Akada teaches a resin film provided above the layer stack in the first direction, wherein the resin film is not provided at a position farther from the first region than the third conductor (Fig. 10 and [0043] point to a passivation film 50 (resin film) comprising polyimide (see [0101] of the claimed invention).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ito and Akada, such that a resin film is formed above the layer stack and extends up to the third conductor in order to selectively provide electrical insulation and heat dissipation to the covered region while leaving the remaining portions of the structure exposed to still allow for access and/or minimize costs.
Regarding claim 20, Ito teaches an insulating layer provided above the third conductor and the eighth conductor (Figs. 13-18 and [0077-0082] point to an unlabeled interlayer insulating film (insulating layer) encompassing the upper surface of the semiconductor substrate 20 and reaching a maximum height equal to the upper surface of contacts C3W (third conductor; eighth conductor).).
Ito fails to teach wherein the insulating layer includes, above a region between the third conductor and the eighth conductor, a trench provided in an upper surface of the insulating layer.
Akada teaches wherein the insulating layer includes, above a region between the third conductor and the eighth conductor, a trench provided in an upper surface of the insulating layer (Fig. 16 points to a passivation film 50 (insulating layer) comprising a trench TR. It is considered obvious that one of ordinary skill in the art would at least attempt to experiment with the location of the trench TR, such that it could be located above and between adjacent conductors.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ito and Akada, such that the third insulating layer comprises a trench located on the upper surface of said layer and between the third and eighth conductors in order to provide alignment for future etching(s) and/or prevent delamination or cracking.
Response to Arguments
Applicant’s arguments, see pg. 9 of Remarks, filed 10/16/2025, with respect to the objection of claim 2 have been fully considered and are persuasive. The objection of claim 2 has been withdrawn.
Applicant’s arguments, see pg. 13 of Remarks, filed 10/16/2025, with respect to the rejection(s) of claim(s) 7 under 35 U.S.C. §112(a) and 35 U.S.C. §102(a)(1) have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. §103 in view of Ito (PGPub No. 20210066329) in further view of Akada (PGPub No. 20200185340).
Applicant's arguments filed 10/16/2025 have been fully considered but they are not persuasive. Specifically, Applicant traverses the previously made rejections under 35 U.S.C. §112(b) (see Sections 5-8 in the previous Office Action) and the rejection of claim 1 under 35 U.S.C. 102(a)(1).
Regarding Section 5 of the previous Office Action, specifically the use of the term “conductor” in claims 1-4, 6-9, and 11-20, Examiner argues that Applicant still fails to properly use the term in a clear and definite manner. Applicant lists non-limiting examples of the correspondences between the “first conductor” to the “tenth conductor” and the features described in the specification, but Examiner argues that this only further adds to any confusion, as the term “conductor” is shown to correspond to the terms “contact”, “conductive layer”, “crack stopper”, and/or combination(s) of said terms. Additionally, such a list of examples is mentioned nowhere in the specification or claims themselves, such that one of ordinary skill in the art would, for example, identify the “first conductor” as two contacts connected by a conductive layer but the “second conductor” as just a conductive layer. Thus, Applicant’s argument is considered unpersuasive and the corresponding rejection is upheld.
Regarding Section 6 of the previous Office Action, specifically the use of the terms “first region” and “second region” in claim 1, Examiner argues that Applicant merely provides a conclusory argument. Normally, such terms would in fact be clear and definite terms based on their plan and ordinary meaning. However, the fact that both the specification and Fig. 3 specifically point to four regions, that being a core region CR, a wall region WR, a contact region C3T, and an end region ER, without any indication as to which region or combination of regions corresponds to the “first region” and “second region” respectively, renders said terms indefinite. Thus, Applicant’s argument is considered unpersuasive and the corresponding rejection is upheld.
Regarding Section 7 of the previous Office Action, specifically the use of the term “layer stack” in claims 1 and 8-11, Examiner argues that Applicant merely provides a conclusory argument. While Applicant does point to a structure comprising insulating layer(s) and conductive layer(s) that could be construed as a “layer stack”, this does nothing to alleviate the confusion created by the actual wording currently used in the specification. At best, [0068-69] as cited by Applicant only hint to said structure being the “layer stack”, primarily due to said layers being “stacked in an alternating manner”; in contrast, the specification explicitly points to a layer stack SLP while also calling it a “stacked structure” in [0100]. Thus, without any amendment to the specification, Applicant’s argument is considered unpersuasive and the corresponding rejection is upheld.
Regarding Section 8 of the previous Office Action, specifically the use of the terms “second conductor”, “third conductor”, and “third insulating layer” in claims 18-20 respectively, Examiner argues that Applicant fails to recognize the chain of dependency used by said claims. While Applicant correctly states that claim 4 previously discloses a “first insulator”, it exists as part of an alternative embodiment to the claimed invention comprising claims 1, 4, and 5. As currently written, claims 18-20 each separately depend on claim 11, which in turn depends on claim 1. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers (emphasis added). See 35 U.S.C. §112(d). In other words, claims 18-20 can only be seen in view of the claims which they depend on and not simply any claim within the disclosed invention. Thus, without any further amendment(s) to the claims, Applicant’s argument is considered unpersuasive and the corresponding rejection is upheld.
Regarding the rejection of claim 1, Examiner argues that Applicant’s analysis of reference Ito (PGPub No. 20210066329) is based on evidence not supported by the claimed invention. Specifically, Applicant argues that the term “first direction” corresponds to the “Z direction” shown in Fig. 9 of the claimed invention, which by extension proves that Ito fails to disclose or suggest that “the third conductor is not opposed to the first conductor in the first direction”. Examiner argues that neither the claims nor the specification support this argument; the term “first direction” is used only a few times throughout the claimed invention, and never is used to directly or indirectly point to the “Z direction” as claimed by Applicant. It is for this reason that Examiner previously pointed to the x-direction as best shown in Fig. 9 of Ito, which when followed shows contact C1W (first conductor) and contact C3W (third conductor) running parallel to each other (not opposed to). Thus, Applicant’s argument is considered unpersuasive and the corresponding rejection is upheld.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899