Attorney Docket Number: AE3679-US
Filing Date: 09/02/2022
Claimed Priority Date: none
Inventors: Marin et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 12/10/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 12/10/2025 in reply to the previous Office action mailed on 09/23/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-4, 6, 8-12, and 14-19.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims. No new matter should be entered.
“A package substrate including a power source, the power source electrically coupled to the tenth conductive contact at the first surface of the substrate”, as recited in claim 15
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “1624” has been used to designate both a source/drain contact and a device layer in figure 6.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “1628” has been used to designate both an interconnect structure and a dielectric material in figure 6.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-9, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade (US 2022/0199539) in view of Sun (US 2022/0270976), Lu (US 2019/0115294), and Liff (US 2021/0111147).
Regarding claim 1, Karhade (see, e.g., fig. 14) shows most aspects of the instant invention, including a microelectronic assembly 150 comprising:
a conductive pad 180 (see, e.g., par.0029/ll.51) having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces;
a liner 116 on the second surface of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold (see, e.g., par.0029/ll.24-25);
a microelectronic component 110 having a conductive contact 182;
an interconnect 106 electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin (see, e.g., pars.0032/ll.7-8 and 0080/ll.1-3); and
a dielectric material 104, 147 (see, e.g., par.0049/ll.32) having a cavity 120, wherein the microelectronic component 110 is at least partially nested in the cavity with the conductive contact 182 facing towards a bottom surface of the cavity, and wherein the bottom surface of the cavity comprises a perimeter
Although Karhade shows most aspects of the instant invention, further specifies that the conductive pad may take any suitable form (see, e.g., par.0029/ll.43-51), and shows other embodiments (see, e.g., fig. 43) having a conductive via coupled to a conductive pad, Karhade as used fails to specify that a conductive via is coupled to first surface of the conductive pad and that the liner is on the lateral surfaces of the conductive pad.
Sun, in the same field of endeavor and in a similar device to Karhade, teaches a device having vias shown to be coupled to the first surface of a conductive pad (see, e.g., Sun: fig. 2). Sun teaches that such vias can form conductive pathways that penetrate through a substrate (see, e.g., par.0025/ll.6-8), can electrically couple various lines of conductive material below the conductive pad (see, e.g., par.0025/ll.18-20), and can electrically connect circuitry in a microelectronic component to circuitry within or connected to the substrate (see, e.g., par.0026/ll.14-21). Furthermore, Lu, in the same field of endeavor, teaches that having a conductive liner disposed on the lateral surfaces of a conductive pad can reduce a moment caused by a force directionally perpendicular to a substrate, which can help prevent the pad and liner from delaminating (see, e.g., Lu: par.0031/ll.7-14).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have vias coupled to the first surface of Karhade’s conductive pad, as taught by Sun and shown in Karhade’s other embodiments, so as to expand the electrical and circuitry connections of Karhade’s conductive pad and microelectronic component. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Karhade’s liner further disposed on the lateral sides of Karhade’s conductive pad, as taught by Lu, so as to prevent Karhade’s conductive pad and liner from delaminating.
Additionally, Karhade (see, e.g., fig. 14) shows a dielectric material 104, 147 (see, e.g., par.0049/ll.32) having a cavity 120, wherein the microelectronic component 110 is at least partially nested in the cavity with the conductive contact 182 facing towards a bottom surface of the cavity. Karhade further shows the cavity having space at a bottom surface, wherein the bottom surface of the cavity comprises a perimeter. Karhade, however, fails to explicitly specify that a metal ring is within the cavity and at a perimeter of the bottom surface of the cavity. Liff, in the same field of endeavor and in a similar device to Karhade, shows a microelectronic assembly 348 comprising a dielectric or insulating material 132 and/or 134 having a cavity (e.g., space in 151 between two innermost 134), wherein a microelectronic component 114-1 is at least partially nested in the cavity with a conductive contact 122 facing towards a bottom surface of the cavity, and wherein a metal ring 136 is within the cavity and at a perimeter of the bottom surface of the cavity (see, e.g., Liff: figs. 22 and 25A-25F and pars.0089/ll.7-8 and 0106/ll.5-12). Liff teaches that the inclusion of such a ring in such a structure, shown such that the metal ring is within the cavity and at a perimeter of the bottom surface of the cavity, complements the footprint shape of the microelectronic component and facilitates guiding the microelectronic component into position, ensuring the alignment of the microelectronic component during manufacture and allowing the microelectronic component to be properly positioned (see, e.g., Liff: pars.0089/ll.12-17 and 0102/ll.4-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a metal ring within Karhade’s cavity and at a perimeter of the bottom surface of Karhade’s cavity, as taught by Liff, so as to complement the footprint shape of Karhade’s microelectronic component and facilitate guiding Karhade’s microelectronic component into position, ensuring the proper positioning of Karhade’s microelectronic component and the alignment of Karhade’s microelectronic component during manufacture.
Regarding claim 16, Karhade (see, e.g., fig. 14) shows most aspects of the instant invention, including a microelectronic assembly 150 comprising:
a bridge component 110 including a conductive contact 182; and
a substrate 112/104
wherein the substrate includes:
a conductive trace 180, the conductive trace having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces;
a liner 116 on the second surface of the conductive trace, wherein a material of the liner includes nickel, palladium, or gold (see, e.g., par.0029/ll.24-25);
an interconnect 106 electrically coupling the conductive contact 182 of the bridge component 110 to the liner on the second surface of the conductive trace, wherein a material of the interconnect includes nickel or tin (see, e.g., pars.0032/ll.7-8 and 0080/ll.1-3); and
a dielectric material 104 having a cavity 120, wherein the bridge component 110 is at least partially nested in the cavity with the conductive contact 182 facing towards a bottom surface of the cavity, and wherein the bottom surface of the cavity comprises a perimeter
Although Karhade shows most aspects of the instant invention, further specifies that the conductive trace may take any suitable form (see, e.g., par.0029/ll.43-51), and shows other embodiments (see, e.g., fig. 43) having a conductive via coupled to a conductive trace, Karhade as used fails to specify that a conductive via is coupled to first surface of the conductive trace and that the liner is on the lateral surfaces of the conductive trace.
Sun, in the same field of endeavor and in a similar device to Karhade, teaches a device having vias shown to be coupled to the first surface of a conductive trace (see, e.g., Sun: fig. 2). Sun teaches that such vias can form conductive pathways that penetrate through a substrate (see, e.g., par.0025/ll.6-8), can electrically couple various lines of conductive material below the conductive trace (see, e.g., par.0025/ll.18-20), and can electrically connect circuitry in a microelectronic component to circuitry within or connected to the substrate (see, e.g., par.0026/ll.14-21). Furthermore, Lu, in the same field of endeavor, teaches that having a conductive liner disposed on the lateral surfaces of a conductive trace can reduce a moment caused by a force directionally perpendicular to a substrate, which can help prevent the trace and liner from delaminating (see, e.g., Lu: par.0031/ll.7-14).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have vias coupled to the first surface of Karhade’s conductive trace, as taught by Sun and shown in Karhade’s other embodiments, so as to expand the electrical and circuitry connections of Karhade’s conductive trace and microelectronic component. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Karhade’s liner further disposed on the lateral sides of Karhade’s conductive trace, as taught by Lu, so as to prevent Karhade’s conductive trace and liner from delaminating.
Additionally, Karhade (see, e.g., fig. 14) shows that Karhade’s substrate 112/104 includes a dielectric material 104, 147 (see, e.g., par.0049/ll.32) having a cavity 120, wherein the bridge component 110 is at least partially nested in the cavity with the conductive contact 182 facing towards a bottom surface of the cavity. Karhade further shows the cavity having space at a bottom surface, wherein the bottom surface of the cavity comprises a perimeter. Karhade, however, fails to explicitly specify that Karhade’s substrate includes a metal ring within the cavity and at a perimeter of the bottom surface of the cavity. Liff, in the same field of endeavor and in a similar device to Karhade, shows a microelectronic assembly 348 comprising a substrate 148/151/153 having a dielectric or insulating material 132 and/or 134 having a cavity (e.g., space in 151 between two innermost 134), wherein a bridge component 114-1 is at least partially nested in the cavity with a conductive contact 122 facing towards a bottom surface of the cavity, and wherein a metal ring 136 is within the cavity and at a perimeter of the bottom surface of the cavity (see, e.g., Liff: figs. 22 and 25A-25F and pars.0089/ll.7-8 and 0106/ll.5-12). Liff teaches that inclusion of such a ring in such a structure, shown such that the metal ring included in the substrate is within the cavity and at a perimeter of the bottom surface of the cavity, complements the footprint shape of the bridge component and facilitates guiding the bridge component into position, ensuring the alignment of the bridge component during manufacture and allowing the bridge component to be properly positioned (see, e.g., Liff: pars.0089/ll.12-17 and 0102/ll.4-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a metal ring included in Karhade’s substrate within Karhade’s cavity and at a perimeter of the bottom surface of Karhade’s cavity, as taught by Liff, so as to complement the footprint shape of Karhade’s bridge component and facilitate guiding Karhade’s bridge component into position, ensuring the proper positioning of Karhade’s bridge component and the alignment of Karhade’s bridge component during manufacture.
Regarding claims 2 and 17, Karhade (see, e.g., par.0031/ll.7-8) shows that a thickness of the liner 116 is between 50 nanometers and 2 microns.
Nevertheless, differences in thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed thickness, i.e., between 50 nanometers and 2 microns, it would have been obvious to one of ordinary skill in the art to use these values in the device of Karhade.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claims 3 and 18, Karhade (see, e.g., fig. 14) shows that the interconnect 106 is tapered, narrowing towards a bottom surface of the interconnect.
Regarding claims 4 and 19, Karhade (see, e.g., fig. 14) shows that the interconnect 106 is one of a plurality of interconnects, and wherein a pitch of the interconnects is between 25 microns and 250 microns (see, e.g., par.0049/ll.25-28).
Nevertheless, differences in distance/pitch will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the criticality of the claimed pitch, i.e., between 25 and 250 microns, it would have been obvious to one of ordinary skill in the art to use these values in the device of Karhade. See the comments stated above in paragraphs 21-24, with respect to claims 2 and 16, regarding criticality, which are considered to be repeated here.
Regarding claim 6, Karhade (see, e.g., fig. 14) shows that the cavity 120 is tapered, narrowing towards a bottom surface of the cavity.
Regarding claim 8, Karhade (see, e.g., fig. 14) shows that the dielectric material 104, 147 includes a first dielectric material 104 and a second dielectric material 147 (see, e.g., par.0049/ll.32), wherein the first dielectric material includes the cavity 120, and wherein the second dielectric material is on the first dielectric material and on and around the microelectronic component 110. Furthermore, Sun (see, e.g., fig. 2) also shows that a dielectric material 104, 145 includes a first dielectric material 104 and a second dielectric material 145, wherein the first dielectric material includes a cavity 120, and wherein the second dielectric material is on the first dielectric material and on and around a microelectronic component 110.
Regarding claim 9, Karhade (see, e.g., fig. 14) shows that the microelectronic component 110 is a first microelectronic component, wherein:
the conductive contact 182 is a first conductive contact at a first surface of the first microelectronic component 110; and
the first microelectronic component further includes second conductive contacts (two leftmost 118) and third conductive contacts (two rightmost 118) at an opposing second surface;
and wherein the microelectronic assembly 150 further comprises:
a second microelectronic component 130-1 electrically coupled to the second conductive contacts (two leftmost 118) of the first microelectronic component 110; and
a third microelectronic component 130-2 electrically coupled to the third conductive contacts (two rightmost 118) of the first microelectronic component
Claims 10-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Karhade in view of Lu and Liff.
Regarding claim 10, Karhade (see, e.g., fig. 14) shows most aspects of the instant invention, including a microelectronic assembly 150 comprising:
a first layer 112 of a substrate 112/104/147 including a conductive trace 180 with a liner 116 on a top surface of the conductive trace, wherein a material of the liner includes nickel, palladium, or gold (see, e.g., par.0029/ll.24-25); and
a second layer 147 of the substrate on the first layer, the second layer including a cavity 120 having a die 110 embedded in a dielectric material 147 filling the cavity (see, e.g., par.0049/ll.32)
wherein:
the die 110 includes a conductive contact 182 at a surface facing the first layer 112;
the conductive contact is electrically coupled, by an interconnect 106, to the liner 116 on the top surface of the conductive trace 180, and wherein a material of the interconnect includes nickel or tin (see, e.g., pars.0032/ll.7-8 and 0080/ll.1-3); and
the surface of the die 120 comprises a perimeter
Although Karhade shows most aspects of the instant invention, Karhade fails to specify that the liner is on the lateral surfaces of the conductive trace. Lu, in the same field of endeavor, teaches that having a conductive liner disposed on the lateral surfaces of a conductive pad can reduce a moment caused by a force directionally perpendicular to a substrate, which can help prevent the pad and liner from delaminating (see, e.g., Lu: par.0031/ll.7-14).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Karhade’s liner further disposed on the lateral sides of Karhade’s conductive pad, as taught by Lu, so as to prevent Karhade’s conductive pad and liner from delaminating.
Additionally, Karhade shows that Karhade’s second layer 147 of the substrate includes a cavity 120 having a die 110 embedded in a dielectric material 147 filling the cavity (see, e.g., figs. 14 and par.0049/ll.32). Karhade further shows the cavity having space at a surface, and that the surface of the die (wherein a conductive contact 182 is included) comprises a perimeter. Karhade, however, fails to explicitly specify that a metal ring is within the dielectric material filling the cavity and at a perimeter of the surface of the die. Liff, in the same field of endeavor and in a similar device to Karhade, shows a microelectronic assembly 348 having a second layer 151 of a substrate 148/151/153, wherein the second layer comprises a dielectric or insulating material 132 and/or 134 filling a cavity (e.g., space in 151 between two innermost 134), wherein the cavity has a die 114-1 embedded in the dielectric or insulating material filling the cavity with a conductive contact 122 on a surface of the die, and wherein a metal ring 136 is within the dielectric or insulating material filling the cavity and at a perimeter of the surface of the die (see, e.g., Liff: figs. 22 and 25A-25F and pars.0089/ll.7-8 and 0106/ll.5-12). Liff teaches that inclusion of such a ring in such a structure, shown such that the metal ring is within the dielectric or insulating material filling the cavity and at a perimeter of the surface of the die, complements the footprint shape of the die and facilitates guiding the die into position, ensuring the alignment of the die during manufacture and allowing the die to be properly positioned (see, e.g., Liff: pars.0089/ll.12-17 and 0102/ll.4-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a metal ring within the dielectric material taught by Karhade to be filling Karhade’s cavity and at a perimeter of the surface of Karhade’s die, as taught by Liff, so as to complement the footprint shape of Karhade’s die and facilitate guiding Karhade’s die into position, ensuring the proper positioning of Karhade’s die and the alignment of Karhade’s die during manufacture.
Regarding claim 11, Karhade (see, e.g., par.0031/ll.7-8) shows that a thickness of the liner 116 is between 50 nanometers and 2 microns.
Nevertheless, differences in thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the criticality of the claimed thickness, i.e., between 50 nanometers and 2 microns, it would have been obvious to one of ordinary skill in the art to use these values in the device of Karhade. See the comments stated above in paragraphs 21-24, with respect to claims 2 and 16, regarding criticality, which are considered to be repeated here.
Regarding claim 12, Karhade (see, e.g., fig. 14) shows that the interconnect 106 is one of a plurality of interconnects, and wherein a pitch of the interconnects is between 25 microns and 250 microns (see, e.g., par.0049/ll.25-28).
Nevertheless, differences in distance/pitch will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the criticality of the claimed pitch, i.e., between 25 and 250 microns, it would have been obvious to one of ordinary skill in the art to use these values in the device of Karhade. See the comments stated above in paragraphs 21-24, with respect to claims 2 and 16, regarding criticality, which are considered to be repeated here.
Regarding claim 14, Karhade (see, e.g., fig. 14) shows that the conductive contact 182 is a first conductive contact at a first surface of the die 110, wherein:
the die further includes second conductive contacts (two leftmost 118) and third conductive contacts (two rightmost 118) at an opposing second surface; and
the substrate 112/104/147 further includes fourth conductive contacts (two leftmost 114) and fifth conductive contacts (two rightmost 114) on a surface
and wherein the microelectronic assembly 150 further comprises:
a first microelectronic component 130-1 having sixth conductive contacts 134 and seventh conductive contacts 132 at a surface of the first microelectronic component:
wherein the sixth conductive contacts 134 are electrically coupled to the second conductive contacts (two leftmost 118) of the die 110; and
wherein the seventh conductive contacts 132 are electrically coupled to the fourth conductive contacts (two leftmost 114) of the substrate 112/104/147; and
a second microelectronic component 130-2 having eighth conductive contacts 134 and ninth conductive contacts 132:
wherein the eighth conductive contacts 134 are electrically coupled to the third conductive contacts (two rightmost 118) of the die 110; and
wherein the ninth conductive contacts 132 are electrically coupled to the fifth conductive contacts (two rightmost 114) of the substrate 112/104/147
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Karhade/Lu/Liff in view of Zhang (US 2020/0212020) and Baba (US 2003/0209808).
Regarding claim 15, Karhade/Lu/Liff shows most aspects of the instant invention (see paragraphs 32-36 and 41 above). Furthermore, Karhade (see, e.g., fig. 14) teaches that the surface of the substrate 112/104/147 is a second surface, that the substrate further includes a first surface (bottommost surface of 104), opposite the second surface, having a tenth conductive contact (bottommost 106/206) with electrical couplings, and that the microelectronic assembly 150 includes the tenth conductive contact at the first surface of the substrate. Karhade additionally teaches that Karhade’s microelectronic package 150 includes a conductive trace 180 and that Karhade’s microelectronic assembly may comprise other electronic components known in the art (teaching also that package substrates are known in the art (see, e.g., par.0001/ll.1-2)), electrically coupled by way of the tenth conductive contact (see, e.g., par.0036/ll.15-19). However, Karhade fails to specify that the tenth conductive contact is electrically coupled to the conductive trace and that Karhade’s package substrate includes a power source, wherein the power source is electrically coupled to the tenth conductive contact.
Zhang, in the same field of endeavor, teaches (see, e.g., Zhang: fig. 1) a microelectronic assembly 100 hosting a substrate (all layers including and between topmost 127 and bottommost 127) including a first surface having a tenth conductive contact (bottommost 150 beneath 152) electrically coupled to the conductive trace (topmost 150 above 152) (see, e.g., Zhang: pars.0018/ll.8-14, 024/ll.25-27, 0034/ll.20-21) of a die 114-1, wherein the microelectronic assembly further comprises a package substrate 102 housing power structures (see, e.g., Zhang: pars.0021/ll.18-19 and 0033/ll.1-4) electrically coupled to the die by way of being electrically coupled to the tenth conductive contact (see, e.g., Zhang: 0035/ll.13-15) at the first surface of the substrate. Zhang teaches that such a structure can improve the performance of a microelectronic assembly by more efficiently delivering power to the die (see, e.g., Zhang: par.0022/ll.7-8). Furthermore, Baba, in the same field of endeavor, teaches that having a power source directly included in a package substrate reduces noise and improves high-speed transmission (see, e.g., Baba: fig. 1B and par.0054).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Karhade’s tenth conductive contact electrically coupled to Karhade’s conductive trace, and to have Karhade’s microelectronic assembly further comprise a package substrate including a power structure, the power structure electrically coupled to the tenth conductive contact, as taught by Zhang, so as to improve the performance of Karhade’s device by more efficiently delivering power to Karhade’s die. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the power structures in such a package substrate be a power source, as taught by Baba, so as to improve noise reduction and high-speed transmission in Karhade’s device.
Response to Arguments
Applicant’s arguments with respect to the objections to the drawings put forth in the previous Office action mailed on 09/23/2025 have been considered and are found partially persuasive. Specifically, Applicant’s arguments with respect to the objections to the drawings under 37 CFR 1.84(p)(4) and 37 CFR 1.84(p)(5), in view of Applicant’s specification, are found persuasive. However, Applicant has failed to address the remaining objections to the drawings under 37 CFR 1.83(a) and 37 CFR 1.84(p)(4), which do not reference Applicant’s specification or written description. Accordingly, the remaining objections to the drawings put forth in the previous Office action are maintained.
Applicant’s arguments with respect to the 35 U.S.C. 112 rejection put forth in the previous Office action mailed on 09/23/2025 have been considered and are found persuasive. Accordingly, the 35 U.S.C. 112 rejection put forth in the previous Office action is withdrawn.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814