DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/5/2026 has been entered.
Claim Rejections - 35 USC § 112
Prior rejection of Claims 9-11 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claim 9.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 2019/0296046 A1, of record), and further in view of Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, of record).
Re Claim 12, Arai teaches a system, comprising:
one or more memory devices (memory device, para [0013]) comprising at least one electronic device (Fig. 19), the at least one electronic device comprising:
a source contact (13, Fig. 19, para [0122]) vertically adjacent to a source stack (10+12, Fig. 19, para [0121]);
a first semiconductor material (14, Fig. 19, para [0025]) over the source contact (13);
memory pillars (CL, Fig. 19, para [0018]) vertically extending through a stack (100, Fig. 19, para [0018]) of alternating dielectric materials (72, Fig. 19, para [0029]) and conductive materials (70, Fig. 19, para [0029]), the first semiconductor material (14), and the source contact (13), and at least partially into the source stack (10+12), the memory pillars (CL) operably coupled to the source contact (10+12, see Fig. 19);
a fill material (165+166, Fig. 19, paras [0127] - [0128]) extending vertically through the stack (100) and into the source contact (13, see Fig. 19), the fill material (165+166) comprising an additional material (166 is an insulating material, para [0127]);
Arai does not explicitly disclose that the fill material comprises an additional dielectric material. Arai discloses that the fill material (165+166, Fig. 19) comprises an insulating material 166 but does not explicitly disclose that the insulating material is a dielectric material.
Related semiconductor art, Youn’663 discloses a similar insulating spacer (584, Fig. 16-I, paras [0216] – [0217]) which is made of an insulating dielectric material like silicon oxide. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the insulating material of Arai from a dielectric material as disclosed by Youn’663 (Fig. 16-I). The use of a known dielectric material for its known purpose for forming an insulating spacer is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Arai also does not disclose a metal silicide material directly vertically adjacent to the source contact.
However, in a related semiconductor art, Youn’663 discloses (Fig. 16-I) that a metal silicide layer (704) can be formed between the source contact 504 (similar to 13 of Arai), and the conductive pillar 582 (similar to 165 of Arai in Fig. 19). Additional art, Yun discloses that the metal silicide layer is formed in order to reduce contact resistance (para [0046]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to interpose a metal silicide layer between the layers 13 and 165 of Arai (see annotated Fig. 19 of Arai below) as disclosed by Youn’663 (Fig. 16-I) because it helps in reduction of the contact resistance and improve electrical conductivity (Yun, para [0046]).
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Furthermore, Arai does not disclose a processor coupled to an input device and an output device, and one or more memory devices operably coupled to the processor.
Related art, Youn’663 discloses a memory module (1210, Fig. 19, para [0311]), which can be made up of the memory devices of Arai, and are coupled to a processor (1222, Fig. 19, para [0311]) and also to an input/output device (Host interface, 1223, Fig. 19, para [0311]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include the processor and input/output devices to the memory device of Arai, as disclosed by Youn’663, which will make it a fully-functioning and an independent user-friendly device.
Re Claim 13, Arai modified by Youn’663 and Yun teaches the system of claim 12, wherein the metal silicide material (“silicide layer”, see annotated Fig. 19 of Arai, above) does not extend over sidewalls of the first semiconductor material (the “silicide layer” does not extend over top or bottom sidewalls of the first semiconductor material 14, see annotated Fig. 19 of Arai, above).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 2019/0296046 A1, of record), Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, of record), and further in view of Lee et al. (US 2014/0308794 A1, of record).
Re Claim 14, Arai modified by Youn’663 and Yun teaches the system of claim 12, but does not disclose that the metal silicide material comprises a gradient of silicon in the metal silicide material.
However, in a related semiconductor art, Lee discloses a silicidation process where the metal silicide layer can have a gradient of silicon, depending on the annealing conditions. For example, the cobalt silicide layer can have CoSix phase, where x is between 0.1 and 1.5 (para [0068]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the silicon gradient of the metal silicide layer through different annealing steps and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed silicon gradient in the metal silicide layer through different annealing steps would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 1-3, 5-9 and 11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowable for following reasons. Most of the limitations of claim 1 are taught by Arai et al. (US 2019/0296046 A1, of record), and further in view of Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, of record), as stated in the office action dated 2/12/2026. The amended claim further contains the limitation wherein, “the metal silicide material directly contacting sidewalls of the source contact and sidewalls of the fill material.” Arai modified by Youn’663 and Yun teaches that the metal silicide layer would directly contact the sidewalls of the source contact (layer 13, see annotated Fig. 19 of Arai above) and also the bottom sidewall of the fill material (layer 165, see annotated Fig. 19 of Arai above). However, they fail to teach that the silicide layer will directly contact a plurality of sidewalls of the fill material, as required by the claim limitation. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, as was also stated in the objection of claim 4 in the office action dated 2/12/2026. Claims 2-3 and 5-8 depend from claim 1 and are allowable for at least the reasons above.
Claim 9 is allowable for following reasons. Arai et al. (US 2019/0296046 A1, of record), and further in view of Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, of record) teaches most of the limitations of claim 9.
For example, Arai teaches a memory device (Fig. 19), comprising:
a stack comprising tiers of alternating conductive structures (70, Fig. 19, para [0029]) and dielectric structures (72, Fig. 19, para [0029]) overlying a source stack (10+12, Fig. 19, para [0121]);
pillars (CL, Fig. 19, para [0018]) extending vertically through the stack (70+72) and into the source stack (10+12, Fig. 19), the pillars comprising a channel material (20, Fig. 19, para [0043]);
a source contact (13, Fig. 19, para [0122]) laterally adjacent to the pillars (CL, Fig. 19) and electrically connected to the channel material of the pillars (20, see Fig. 19);
a fill material (165, Fig. 19, para [0128]) vertically extending through the tiers (70+72) and into the source contact (13, see Fig. 19).
Arai does not disclose a metal silicide material directly contacting an upper surface of the source contact, the metal silicide material directly contacting sidewalls of the source contact and sidewalls of the fill material.
Youn’663 discloses (Fig. 16-I) that a metal silicide layer (704) can be formed between the source contact 504 (similar to 13 of Arai), and the conductive pillar 582 (similar to 165 of Arai in Fig. 19). Additional art, Yun discloses that the metal silicide layer is formed in order to reduce contact resistance (para [0046]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to interpose a metal silicide layer between the layers 13 and 165 of Arai (see annotated Fig. 19 of Arai above) as disclosed by Youn’663 (Fig. 16-I) because it helps in reduction of the contact resistance and improve electrical conductivity (Yun, para [0046]).
However, Arai modified by Youn’663 and Yun fails to teach the limitation wherein, “the metal silicide material directly contacting sidewalls of the source contact and sidewalls of the fill material”. The combined art above teaches that the metal silicide layer would directly contact the sidewalls of the source contact (layer 13, see annotated Fig. 19 of Arai above) and also the bottom sidewall of the fill material (layer 165, see annotated Fig. 19 of Arai above). However, they fail to teach that the silicide layer will directly contact a plurality of sidewalls of the fill material, as required by the claim limitation. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion. Claim 11 depends from claim 9 and is allowable for at least the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim 12 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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