DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 9 recites the limitation wherein the “metal silicide material directly contacting an upper surface of the source contact and sidewalls of the conductive structures of the tiers.” The metal silicide layer (148, Fig. 1H) does not directly contact the sidewalls of the conductive structures of the tiers (conductive layers 152 of the tier stack 116, Fig. 1H). Additionally, there is no support for the limitation in paragraphs [0048] – [0052] of the original specification, as the applicant claimed in the remarks filed 11/3/2025.
Claims 10-11 depend from claim 9 and are also rejected at least for the reasons above.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 2019/0296046 A1, of record), and further in view of Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, newly cited).
Re Claim 1, Arai teaches an electronic device, comprising:
a source contact (13, Fig. 19, para [0122]) adjacent to a source stack (10+12, Fig. 19, para [0121]), the source contact comprising one or more conductive materials (13, Fig. 19, para [0025]);
tiers of alternating conductive materials (70, Fig. 19, para [0029]) and dielectric materials (72, Fig. 19, para [0029]) adjacent to the source contact (13); pillars (CL, Fig. 19, para [0018]) extending vertically through the tiers (70+72) and the source contact (13) and at least partially into the source stack (10+12, Fig. 19);
a fill material (165, Fig. 19, para [0128]) extending vertically through the tiers (70+72) and into the source contact (13, see Fig. 19);
Arai does not disclose a metal silicide material between the fill material (165) and an upper surface of the source contact (13).
However, in a related semiconductor art, Youn’663 discloses (Fig. 16-I) that a metal silicide layer (704) can be formed between the source contact 504 (similar to 13 of Arai), and the conductive pillar 582 (similar to 165 of Arai in Fig. 19). Additional art, Yun discloses that the metal silicide layer is formed in order to reduce contact resistance (para [0046]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to interpose a metal silicide layer between the layers 13 and 165 of Arai (see annotated Fig. 19 of Arai below) as disclosed by Youn’663 (Fig. 16-I) because it helps in reduction of the contact resistance and improve electrical conductivity (Yun, para [0046]).
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Re Claim 3, Arai modified by Youn’663 and Yun teaches the electronic device of claim 1, wherein the metal silicide material comprises one or more of tungsten silicide, molybdenum silicide, cobalt silicide, and titanium silicide (cobalt silicide, tungsten silicide, or nickel silicide, para [0046], Yun).
Re Claim 12, Arai teaches a system, comprising:
one or more memory devices (memory device, para [0013]) comprising at least one electronic device (Fig. 19), the at least one electronic device comprising:
a source contact (13, Fig. 19, para [0122]) vertically adjacent to a source stack (10+12, Fig. 19, para [0121]);
a first semiconductor material (14, Fig. 19, para [0025]) over the source contact (13);
memory pillars (CL, Fig. 19, para [0018]) vertically extending through a stack (100, Fig. 19, para [0018]) of alternating dielectric materials (72, Fig. 19, para [0029]) and conductive materials (70, Fig. 19, para [0029]), the first semiconductor material (14), and the source contact (13), and at least partially into the source stack (10+12), the memory pillars (CL) operably coupled to the source contact (10+12, see Fig. 19);
a fill material (165, Fig. 19, para [0128]) extending vertically through the stack (100) and into the source contact (13, see Fig. 19);
Arai does not disclose a metal silicide material directly vertically adjacent to the source contact.
However, in a related semiconductor art, Youn’663 discloses (Fig. 16-I) that a metal silicide layer (704) can be formed between the source contact 504 (similar to 13 of Arai), and the conductive pillar 582 (similar to 165 of Arai in Fig. 19). Additional art, Yun discloses that the metal silicide layer is formed in order to reduce contact resistance (para [0046]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to interpose a metal silicide layer between the layers 13 and 165 of Arai (see annotated Fig. 19 of Arai above) as disclosed by Youn’663 (Fig. 16-I) because it helps in reduction of the contact resistance and improve electrical conductivity (Yun, para [0046]).
Furthermore, Arai also does not disclose a processor coupled to an input device and an output device, and one or more memory devices operably coupled to the processor.
Related art, Youn’663 discloses a memory module (1210, Fig. 19, para [0311]), which can be made up of the memory devices of Arai, and are coupled to a processor (1222, Fig. 19, para [0311]) and also to an input/output device (Host interface, 1223, Fig. 19, para [0311]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include the processor and input/output devices to the memory device of Arai, as disclosed by Youn’663, which will make it a fully-functioning and an independent user-friendly device.
Re Claim 13, Arai modified by Youn’663 and Yun teaches the system of claim 12, wherein the metal silicide material (“silicide layer”, see annotated Fig. 19 of Arai, above) does not extend over sidewalls of the first semiconductor material (the “silicide layer” does not extend over top or bottom sidewalls of the first semiconductor material 14, see annotated Fig. 19 of Arai, above).
Claims 2, 7-8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 2019/0296046 A1, of record), Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, newly cited), and further in view of Lee et al. (US 2014/0308794 A1, of record).
Re Claim 2, Arai modified by Youn’663 and Yun teaches the electronic device of claim 1, but does not disclose a metal material adjacent to the metal silicide material, the metal material comprising the same metal as the metal material of the metal silicide material.
However, in a related semiconductor art, Lee discloses that during the silicidation process, the metal layer (17, para [0068], Figs. 2E-F) reacts with the polysilicon layer (16, para [0068], Figs. 2E-F), to form the metal silicide layer (20, para [0068], Figs. 2E-F). During this process, there may be unreacted silicidable metal layer (17A, para [0069], Fig. 2F) which is left adjacent to the metal silicide layer (20, Fig. 2F). In view of Lee, it would be obvious to one of ordinary skill in the art, at the time of invention, through routine experimentation, that there might be unreacted metal silicidable layer adjacent to the metal silicide material as claimed in the limitation. Thus, the claimed limitation would have been obvious and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Re Claim 7, Arai modified by Youn’663 and Yun teaches the electronic device of claim 1, but does not disclose that the metal silicide material comprises a stoichiometric metal silicide.
However, in a related semiconductor art, Lee discloses a silicidation process where the cobalt silicide layer has a stochiometric CoSi2 phase (para [0073]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the stoichiometry of the metal silicide layer through different annealing steps and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed stoichiometry through different annealing steps would have been obvious to one of ordinary skill in the art.
Re Claim 8, Arai modified by Youn’663 and Yun teaches the electronic device of claim 1, but does not disclose that the metal silicide material comprises a non-stoichiometric metal silicide.
However, in a related semiconductor art, Lee discloses a silicidation process where the cobalt silicide layer has a non-stochiometric cobalt silicide phase, like CoSix, where x is between 0.1 and 1.5 (para [0068]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the atomic concentration of each of the elements of the metal silicide material through different annealing steps and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the atomic concentration of each of the elements of the metal silicide material through different annealing steps would have been obvious to one of ordinary skill in the art.
Re Claim 14, Arai modified by Youn’663 and Yun teaches the system of claim 12, but does not disclose that the metal silicide material comprises a gradient of silicon in the metal silicide material.
However, in a related semiconductor art, Lee discloses a silicidation process where the metal silicide layer can have a gradient of silicon, depending on the annealing conditions. For example, the cobalt silicide layer can have CoSix phase, where x is between 0.1 and 1.5 (para [0068]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the silicon gradient of the metal silicide layer through different annealing steps and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed silicon gradient in the metal silicide layer through different annealing steps would have been obvious to one of ordinary skill in the art.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 2019/0296046 A1, of record), Youn et al. (US 2015/0228663 A1, hereinafter “Youn’663”, of record) and Yun et al. (US 2020/0273501 A1, newly cited), and further in view of Akutsu et al. (US 2016/0079265 A1, of record).
Re Claim 6, Arai modified by Youn’663 and Yun teaches the electronic device of claim 1, but does not disclose that the metal silicide material has a thickness within a range of from about 1 nm to about 5 nm.
However, in a related semiconductor art, Akutsu discloses that a silicide film layer can have a thickness between 20 – 30 nm (para [0051]). It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thickness of the metal silicide layer and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the thickness of the metal silicide layer would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 4 is allowable for at least the reasons of, “wherein the metal silicide material directly contacts sidewalls of the source contact and sidewalls of the fill material”. Arai modified by Youn’663 and Yun teaches that the metal silicide layer would directly contact the sidewalls of the source contact (layer 13, see annotated Fig. 19 of Arai above) and also the bottom sidewall of the fill material (layer 165, see annotated Fig. 19 of Arai above). However, they fail to teach that the silicide layer will directly contact a plurality of sidewalls of the fill material, as required by the claim limitation. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, in view of the independent claim 1. Claim 5 depends from claim 4 and is allowable for at least the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
With reference of claim 12, applicant remarked that the “fill material 165 of Arai (correlated to the "fill material" of amended claim 12) does not extend vertically into the source contact 13.” Examiner respectfully disagrees with the applicant. In Fig. 19 of Arai, the conductive fill material 165 clearly goes into the source contact layer 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898