DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim(s) 1-9 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1-9 has been withdrawn.
RE: the rejection of claim(s) 1-7, 9 under 35 USC 102 and the rejection of claim 8 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered. However, further consideration of the Park reference resulted in the new grounds of rejection presented herein.
Applicant argues the contact plug 170 does not overlap the substrate 201, the ground via 250, and the plate layer 101 in the X direction and Y direction.
However, the claims include the terminology “conductive pillar” which is broad terminology not limited to only a contact plug. Accordingly, as detailed hereafter, the combination of the contact plug 170 and additional elements under the contact plug 170 in FIG. 2A in Park are considered to correspond to the claimed at least one conductive pillar, and in combination, these elements overlap the substrate 201, the ground via 250, and the plate layer 101 in the horizontal direction.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US20240038659A1 to Park et al. (hereinafter “Park”).
RE: Claim 1, Park discloses A semiconductor device (100 in FIG. 2A), comprising:
a ground layer (201, 250, 101, portions of 280, 270 directly under and connected to 201, 250, 101 as shown in Annotated FIG. 2 below; The ground via 250 is connected to the substrate 201 through a ground interconnection structure, [0036]; The ground via 250 forms a ground structure, together with the ground interconnection structure. The ground structure performs a function of grounding the plate layer 101 and a second horizontal conductive layer 104, [0036]; Accordingly, 201, 250, 101 and portions of 280, 270 directly under and connected to 201, 250, 101 are grounded and are therefore considered a ground layer) comprising a lower semiconductor material layer (201), a refilled semiconductor material layer (250) disposed on the lower semiconductor material layer, and an upper conductive layer (101, [0037]) disposed on the refilled semiconductor material layer;
a stacked structure (GS2) disposed on the ground layer, and the stacked structure comprising a plurality of insulating layers (120; insulating layers 120 are between gate electrodes 130, [0053]) and a plurality of conductive layers (130, [0048]) alternately stacked along a first direction (vertical direction in FIG. 2A); and
at least one conductive pillar (combination of the second 170 from the left as shown in Annotated FIG. 2A below, the portions of 270, 280 directly under the second 170, and the portion of 205 directly under the second 170) penetrating the stacked structure along the first direction and extending into the ground layer (FIG. 2A shows the second 170 penetrating GS2 along the vertical direction and extending into at least 101), wherein the at least one conductive pillar comprises a bottom body portion (bottom portion of 170 in GS1 and portions of 270, 280, 205 directly under the second 170 as shown in Annotated FIG. 2A below), a middle body portion (middle portion of 170 in GS2) and a plug (upper portion of 170 in GS3), wherein the middle body portion is connected between the bottom body portion and the plug (Annotated FIG. 2A below shows the middle portion of 170 in GS2 is connected between the upper portion of 170 in GS3 and bottom portion of 170 in GS1 and below);
wherein, in a second direction (horizontal direction in FIG. 2A) different from the first direction (vertical direction), a portion of the bottom body portion (bottom portion of second 170 delineated with dashed lines in Annotated FIG. 2A below) overlapping the upper conductive layer has a first dimension (the bottom portion of the second 170 has a first dimension / width in the horizontal direction as shown in Annotated FIG. 2A below), and a portion of the middle body portion overlapping a bottommost insulating layer of the stacked structure has a second dimension (Annotated FIG. 2A shows a bottom portion of the middle body portion of 170 has second dimension / width in the horizontal direction), and the first dimension is greater than the second dimension (Annotated FIG. 2A shows the first dimension is greater than the second dimension),
wherein the bottom body portion overlaps the lower semiconductor material layer, the refilled semiconductor material layer and the upper conductive layer in the second direction (Annotated FIG. 2A shows the second 170 from the left in FIG. 2A, the portions of 280, 270 directly under the second 170, and the portion of 205 directly under the second 170 overlap 201, 250, 101 in the horizontal direction).
PNG
media_image1.png
734
1136
media_image1.png
Greyscale
Annotated FIG. 2A of Park
RE: Claim 2, Park discloses The semiconductor device according to claim 1, wherein, in the second direction, a portion of the middle body portion overlapping a portion disposed above the bottommost insulating layer of the stacked structure has a third dimension (Annotated FIG. 2A of Park above shows a middle portion of the middle body portion overlapping a lower portion of the middle body portion disposed above the bottommost insulating layer 120 has a third dimension / width in the horizontal direction), the first dimension is greater than the third dimension, and the third dimension is greater than the second dimension (Annotated FIG. 2A shows 170 in GS2 has a tapered width that increases in the upward direction, and that the width at the top of 170 in GS2 is substantially equal to the first dimension / width; accordingly the first dimension / width is greater than the third dimension / width, and the third dimension / width is greater than the second dimension / width).
RE: Claim 3, Park discloses The semiconductor device according to claim 1, further comprising an isolation material layer (combination of 160, 121, 294, [0047]) disposed between the conductive pillar and the stacked structure and between the conductive pillar and the ground layer,
wherein in the second direction, a maximum dimension of a portion (121) of the isolation material layer overlapping the upper conductive layer is greater than a maximum dimension of a portion (160) of the isolation material layer overlapping the stacked structure (FIG. 2A shows the maximum horizontal dimension of 121 in the far right in FIG. 2A is greater than maximum dimension of each portion of 160).
RE: Claim 4, Park discloses The semiconductor device according to claim 1, wherein the middle body portion and the bottom body portion comprise a body barrier layer (In Park FIG. 3: 172 in GS2 and below) and a lower conductive layer (174), and the plug comprises an upper barrier layer (172 in GS3) and an upper conductor (178), and a material of the lower conductive layer is different from a material of the upper conductor (The third conductive layer 178 includes a material, different from those of the barrier layer 172, the first conductive layer 174, and the second conductive layer 176, [0090]).
RE: Claim 5, Park discloses The semiconductor device according to claim 1, wherein an outer sidewall of the conductive pillar has a kink profile at a portion adjacent to the bottommost insulating layer of the stacked structure (In Park FIG. 2A shows 170 has a kink profile at a portion of 170 adjacent to bottommost insulating layer 120 in GS2).
RE: Claim 6, Park discloses The semiconductor device according to claim 1, further comprising a circuit board (In Park FIG. 13: 2100 is a printed circuit board, [0186]), and the ground layer is disposed on the circuit board (In FIG. 13, 2200 is on 2100; Park discloses Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to example embodiments shown in FIGS. 1, 2, 3, 4, 5, 6, 7, 8 and 9, [0186]; Accordingly, the device in FIG. 2A is disclosed as being on 2100, and therefore the ground layer 101, 250, 201 would be on 2100).
RE: Claim 7, Park discloses The semiconductor device according to claim 1, further comprising a plurality of channel structures (In Park FIG. 2A: CH, [0054]), wherein the channel structures penetrate through the stacked structure along the first direction and extend into the ground layer (FIG. 2A shows channel structures CH penetrating through GS2 along vertical direction and extending into 101).
RE: Claim 9, Park discloses The semiconductor device according to claim 1, wherein in the second direction, a portion of the bottom body portion overlapping a top protrusion of the refilled semiconductor material layer has the first dimension (Annotated FIG. 2A shows the bottom portion of second 170 overlapping top protrusion of 250 has the first dimension / width; top portion of 250 is considered a protrusion from 101 and is therefore considered a top protrusion of 250).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of US 20230187351A1 to Kong et al. (hereinafter “Kong”).
RE: Claim 8, Park does not explicitly disclose The semiconductor device according to claim 1, wherein in the first direction, a height is formed between a bottom surface of the bottommost insulating layer of the stacked structure and a bottom surface of the upper conductive layer, and the height is greater than 0 nm, and is less than or equal to 60 nm.
However, in the same field of endeavor, Kong discloses the thickness of the conductive layer 122 may be approximately 50 nm, the thickness of the dielectric layer 124 (the thickness TK1 of the portion of the dielectric layer 124 covered by the conductive layer 122) may be approximately 30 nm, [0021].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of each electrode layer 130, which is conductive, [0052], to approximately 50nm and/or to modify the thickness of each insulating layer 120 approximately 30nm to make a small size low power memory device with fast operation speed as taught by Kong, [0003]. As a result, a height of a layer 130 and/or a height of a layer 120 would be greater than 0nm and less than 60nm, and this height would be formed between the bottom surface of bottommost 120 in GS2 and the bottom surface of 101.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899