DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 recites the limitation " the plurality of third nanostructure channels ". There is insufficient antecedent basis for this limitation in the claim. Claim 9 used to depend from claim 6- claim 9 has been incorporated into claim 1 and the dependency of claim 10 and 11 are altered and therefore the lack of antecedent basis issue has arisen.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wu et al (2019/0131274).
1. A semiconductor device comprising:
a first gate all around field effect transistor (GAA FET) (Fig. 12 A (102B) and [0039]) within a first region of a first type (Fig.12A (202)), the first GAA FET comprising a plurality of first nanostructure channels of a first channel material (Fig.12D (CL2/3) and [0037-0039]); wherein the first GAA FET (Fig. 12 A (102B) and [0039]) further comprises a first portion of nanolayer channel (See Annotated Fig.12B-12C below- the layer is unlabeled) between each of the plurality of first nanostructure channels (Fig.12D (CL2/3) and [0037-0039]) and a first source and drain (See Annotated Drawing below for clarity); and
a second GAA FET (Fig.12A (102A) and [0037-0039]) within a second region of the first type (Fig.12A (202)), the second GAA FET (Fig.12A (102A) and [0037-0039]) comprising a plurality of second nanostructure channels (Fig.12 D (CL1) and [0037-0039]) of a second channel material different than the first channel material [0037-0039].
7. The semiconductor device of claim 1, wherein the plurality of second nanostructure channels (Fig.12 D (CL1) and [0037-0039]) each have a longer channel length relative to the plurality of first nanostructure channels (Fig.12D (CL2/3) and [0037-0039]).
10. The semiconductor device of claim 9, wherein the second GAA FET further comprises a second portion of nanolayer channel (See Annotated Fig.12B-12C below- the layer is unlabeled) between each of the plurality of second nanostructure channels (Fig.12 D (CL1) and [0037-0039]) and a second source and drain (See Annotated Fig.12B-12C below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Witters et al (2017/0025314), and further in view of Wu et al (2019/0131274).
In regards to claim 1, Witters teaches the following claimed limitations as cited below:
1. A semiconductor device comprising:
a first gate all around field effect transistor (GAA FET) (Fig.4 (r-SiGe PMOS) and [0065/0078]) within a first region (Fig.4 (II) [0062 and 0088-0102]) of a first type (Fig.4 (sub) and [0067-0068/0102- the transistors may be all formed on a common substrate]), the first GAA FET (Fig.4 (r-SiGe PMOS) and [0062 and 0088-0102] see also [0065/0078]) comprising a plurality of first nanostructure channels (Fig.4 (SiGe) and [0088-0102]) of a first channel material [Fig.4 (SiGe) and [0062 and 0088-0102]); and
a second GAA FET (Fig.4 (sGe PMOS) and [0065/0078]) within a second region (Fig.4 (III) [0062 and 0088-0102]) of the first type (Fig.4 (sub) and [0067-0068/0102- the transistors may be all formed on a common substrate]), the second GAA FET (Fig.4 (sGe PMOS) and [0062 and 0088-0102] see also [0065/0078]) comprising a plurality of second nanostructure channels (Fig.4 (Ge) and [0088-0102]) of a second channel material (Fig.4 (Ge) and [0088-0102]) different than the first channel material [Fig.4 (SiGe) and [0062 and 0088-0102]).
However, fails to explicitly teach Applicant’s amended claim limitation:
wherein the first GAA FET further comprises a first portion of nanolayer channel between each of the plurality of first nanostructure channels and a first source and drain.
Wu however teaches wherein the first GAA FET (Fig. 12 A (102B) and [0039]) further comprises a first portion of nanolayer channel (See Annotated Fig.12B-12C above- the layer is unlabeled) between each of the plurality of first nanostructure channels (Fig.12D (CL2/3) and [0037-0039]) and a first source and drain (See Annotated Drawing above for clarity).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a first portion of nanolayer channels between the nanostructure channel and source and drain regions as taught by Wu because it is a natural result the selective etch process which occurs to create the nanochannels and allow for the gate all around structure to be formed and is more clearly demonstrated depending upon the plan view of the GAAFET.
2. The semiconductor device of claim 1, further comprising:
a third GAA FET (Fig.4 (S-Si NMOS) and [0065/0078]) within a third region (Fig.4 (I) [0062 and 0088-0102]) of the first type (Fig.4 (sub) and [0067-0068/0102- the transistors may be all formed on a common substrate]), the third GAA FET (Fig.4 (S-Si NMOS) and [0065/0078]) comprising a plurality of third nanostructure channels (Fig.4 (Si) and [0088-0102]) of a third channel material (Fig.4 (Si) and [0088-0102]) different than the first channel material [Fig.4 (SiGe) and [0062 and 0088-0102]) and different than the second channel material (Fig.4 (Ge) and [0088-0102]).
3. The semiconductor device of claim 2, wherein the first region (Fig.4 (II) and [0062 and 0088-0102]) is a p-type region Fig.4 (SiGe PMOS) and [0062 and 0088-0102]) and wherein the second region (Fig.4 (III) and [0062 and 0088-0102]) is a p-type region (Fig.4 (sGe PMOS)).
5. The semiconductor device of claim 3, wherein the first channel material is Silicon Germanium with a first Ge percentage (SiGex) (Fig.4 (SiGe) and [0069-0071]) and wherein the second channel material is Silicon Germanium with a second Ge percentage (SiGey) (Fig.4 (Ge) and [0069-0071).
6. The semiconductor device of claim 4, wherein the first channel material is Silicon Germanium with a first Ge percentage (SiGex) (Fig.4 (SiGe) and [0069-0071]), wherein the second channel material is Silicon Germanium with a second Ge percentage (SiGey) (SiGey) (Fig.4 (Ge) and [0069-0071), and wherein the third channel material is Silicon (Si) (Fig.4 (Si) and [0069-0071]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Witters et al (2017/0025314) in further view of Wu et al (2019/0131274)..
Witters and Wu teach the limitations of claims 1-3 as cited above, and Witters teaches the third region (Fig.4 (I) [0062 and 0088-0102]) is n-type; however Witters fails to explicitly teach the limitations of claim 4 as cited below:
4. The semiconductor device of claim 3, wherein the third region is a p-type region.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Witters teachings to include a third region of a p-type; because one of ordinary skill in the art understands that chips include thousands of transistors and the transistor types are either n or p type and modifying the teachings of Witters to include a third p type transistor would be considered obvious, conventional and well understood by one of ordinary skill in the art.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (2019/0131274) in further view of Witters et al (2017/0025314).
Wu teaches the limitations of claims 1-2 above, however fails to teach the limitations of claim 8 as recited below:
8. The semiconductor device of claim 2, wherein the plurality of third nanostructure channels each have a longer channel length relative to the plurality of first nanostructure channels.
However Wu teaches nanostructure channels having varying lengths (Fig.12D (CL1/CL2/CL3) and [0037-0039]).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Wu’s teachings to include varying channel widths for a third nanostructure and the relative to the first and second, because manipulating the size of the channel can help optimize carrier mobility as taught by Wu [0039].
10. The semiconductor device of claim 9, wherein the second GAA FET further comprises a second portion of nanolayer channel between each of the plurality of second nanostructure channels and a second source and drain.
Response to Arguments
Applicant's arguments filed 12/15/25 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach the amended claim language- this is not persuasive- see the Annotated drawing of the Wu reference below:
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Moreover, a portion of a nanolayer channel may be also interpreted as a portion of the nanostructure channel itself divided up any myriad of ways- the claim is the name of the game- and the claim language is not specific- it’s broad.
The previous indicated allowable subject matter required the combination of claims 1,2, 3, 4, 6 and 9. The current amendment added claim 9 into 1 and changed the dependency of claims 10-11- thus necessitating the rejections made above and there is no longer pending allowable subject matter- because the combination of claims (due to the dependency) no longer exists within the claim set.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liaw (US 2021/0159232); Balakrishnan (US 2017/0104060); and Kachian et al (US 2014/0091279) teach similar structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
2/7/26
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