DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed May 15, 2026 has been entered. Claims 1-18 and 21-22 remain pending in the application. Applicant’s amendments to the Drawings and Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed February 18, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-15, 18 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et. al. (US 20190148342 A1), hereinafter Hu.
Regarding claim 1, Hu teaches a device (Fig 14 package 82, [0047]) comprising: a logic layer (Fig 14 unlabeled layer in substrate 114) arranged as a plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2 which has device die 4, [0031]), the logic layer (Fig 14 unlabeled layer in substrate 114) having a front side (Fig 14 top side of logic layer) and a back side (Fig 14 top side of logic layer); a plurality of interconnect structures (Fig 14 vias 68/116, metal lines 66/70) over the front side (Fig 14 top side of logic layer) of the logic layer (Fig 14 unlabeled layer in substrate 114), at least one interconnect structure (Fig 14 TSV 116 connected to bond pad labeled 146 extending through to unlabeled TSVs in die 4) coupling a first die (Fig 14 die 112, [0031]) of the plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2, [0031]) to a second die (Fig 14 device die 4, [0031]) of the plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2 which has device die 4, [0031]); a backside layer (Fig 14 layer with dielectric layers 142 and 42 bonded together) over the back side (Fig 14 bottom side of logic layer) of the logic layer (Fig 14 unlabeled layer in substrate 114); and a passive device (Fig 14 passive device 48B, [0027]; the passive device may be a capacitor, an inductor, a transformer, a resistor, or the like, [0027]) in the backside layer (Fig 14 layer with dielectric layers 142 and 42 bonded together), the passive device (Fig 14 passive device 48B, [0027]) having a seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device), the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device) extending through (Fig 15) the passive device (Fig 14 passive device 48B, [0027]) substantially parallel (Fig 2, [0033]) to the logic layer (Fig 14 unlabeled layer in substrate 114), and the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device) within the backside layer (Fig 14 layer with dielectric layers 142 and 42 bonded together).
Regarding claim 2, Hu as modified in claim 1 teaches the passive device (Fig 12 passive device 48B, [0027]) is in a backside layer (Fig 12 interconnect structure 30, [0020]) comprising a plurality of passive devices (Fig 12 passive device 48D/E/F) and a plurality of vias (Fig 12 vias 44, [0024]).
Regarding claim 3, Hu as modified in claim 2 teaches one of the plurality of vias (Hu: Fig 14 TSVs 16, [0055]) is coupled to the logic layer (Fig 12 unlabeled layer in substrate 114) to deliver power (the structure of Hu is substantially identical to that of the claim, thus the function is presumed to be inherent, MPEP 2112.01(I)) to the logic layer (Fig 12 unlabeled layer in substrate 114).
Regarding claim 4, Hu as modified in claim 1 teaches a support structure (Fig 14 unlabeled structure corresponds to Fig 2 interconnect structure 130, [0029]) between the logic layer (Fig 14 unlabeled layer in substrate 114) and the passive device (Fig 14 passive device 48B, [0027]).
Regarding claim 9, Hu as modified in claim 1 teaches the passive device (Fig 14 passive device 48B, [0027]) comprises a first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) between the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]) and the logic layer (Fig 14 unlabeled layer in substrate 114) and a second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]) over the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]), the first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) having a different material structure (since the metal pads were formed as different times the material structure would be different) from the second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]).
Regarding claim 10, Hu as modified in claim 1 teaches the passive device (Fig 14 passive device 48B, [0027]) comprises a conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]), and the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device; in this case the boundary between the lower electrode and the insulating material) comprises a different chemical composition (Since there are different materials formed in the transition from electrode to insulating material, there will be the presence of process gases, no matter how small of an amount present in the seam) from a region (Fig 14 capacitor insulator of capacitor 48) of the passive device (Fig 14 passive device 48B, [0027]) above the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device).
Regarding claim 11, Hu as modified in claim 1 teaches the passive device (Fig 14 passive device 48B, [0027]) has a base (top of Fig 14 passive device 48B, [0027]) parallel to the logic layer (Fig 14 unlabeled layer in substrate 114) and a height in a direction perpendicular to the logic layer (Fig 14 unlabeled layer in substrate 114)
Hu fails to teach the seam is located at a height above the base in a range between 40% and 60% of the height.
However, Hu teaches the capacitor is formed of metal pads and dielectric layers ([0033]). One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the thicknesses of the dielectric layers would be dependent on the desired properties of the layers. The height of the seam is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the thickness of the dielectric layers as Hu and one of ordinary skill in the art before the effective filing date of the claimed invention has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at thicknesses of the dielectric material and etch stop layer such that a height of the seam above the base is in a range between 40% and 60% of the height, in order to achieve the desired balance properties of the dielectric layer and capacitance of the capacitor, as taught by Hu and one of ordinary skill in the art before the effective filing date of the claimed invention. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed height is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed height).
Regarding claim 12, Hu as modified in claim 1 teaches a via (Fig 14 via 16, [0055]) coupled to a back side (Fig 14 bottom side of passive device 48B) of the passive device (Fig 14 passive device 48B, [0027]).
Regarding claim 13, Hu as modified in claim 12 teaches the passive device (Fig 14 passive device 48B, [0027]) has a height in a direction perpendicular to the logic layer (Fig 14 unlabeled layer in substrate 114), and the via (Fig 14 not shown but coupled to via 116, [0048]) has a width in a direction parallel to the logic layer (Fig 14 unlabeled layer in substrate 114).
Hu as modified in claim 12 fails to teach the width of the via greater than the height of the passive device.
However, Hu teaches the passive device may be a capacitor, an inductor, a resistor among other things ([0027]). One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the different passive devices would have different dimensions, in particular a resistor would have the smallest height of the passive devices. The height of the passive device as compared to the width of the via is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the height of the passive device and the width of the via as Hu and one of ordinary skill in the art before the effective filing date of the claimed invention has identified the height and width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the width of the via being greater than the height of the passive device, in order to achieve the desired balance properties of the passive device and properties of the via, as taught by Hu and one of ordinary skill in the art before the effective filing date of the claimed invention. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed height/width relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed height/width relationship).
Regarding claim 14, Hu as modified in claim 1 teaches a cross-section (Fig 14) of the passive device (Fig 14 passive device 48B, [0027]) has a back side (Fig 14 bottom side of passive device 48B) parallel to the logic layer (Fig 14 unlabeled layer in substrate 114) and a front side (Fig 14 top side of passive device 48B) parallel (Fig 14) to the logic layer (Fig 14 unlabeled layer in substrate 114), the back side (Fig 14 bottom side of passive device 48B) of the passive device (Fig 14 passive device 48B, [0027]) farther from (Fig 14) the logic layer (Fig 14 unlabeled layer in substrate 114) than the front side (Fig 14 top side of passive device 48B) of the passive device (Fig 14 passive device 48B, [0027]), wherein a length of the back side (Fig 14 bottom side of passive device 48B) of the passive device (Fig 14 passive device 48B, [0027]) is longer (due to differences in manufacturing the length of the backside may be longer than the length of the front side) than a length of the front side (Fig 14 bottom side of logic layer) of the passive device (Fig 14 passive device 48B, [0027]).
Regarding claim 15, Hu teaches a wafer device (Fig 14 wafer 2, [0015]) comprising: a logic layer (Fig 14 unlabeled layer in substrate 114) comprising a plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2, [0031]), one of the plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2, [0031]) comprising a plurality of transistors (Fig 14 unlabeled transistor in substrate 114; the art lists the device die 112 with substrate 114 as a logic die, which may be a CPU die, a MCU die, etc.; it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that there would be more than the one transistor shown in Fig 14); and a power delivery structure (Fig 14 interconnect structure 30, unlabeled interconnect structure 130 from Fig 2, vias 16 through substrate 20) on a backside (Fig 14 bottom side) of the logic layer (Fig 14 unlabeled layer in substrate 114), the power delivery structure (Fig 14 interconnect structure 30, unlabeled interconnect structure 130 from Fig 2, vias 16 through substrate 20) comprising: a plurality of backside layers (Figs 1, 2, 14 dielectric layers 32, 38, 42, 138, 142, and other layers in interconnect structures 130); a via coupled to the logic layer (Fig 14 unlabeled layer in substrate 114), the via extending through the plurality of backside layers (Figs 1, 2, 14 dielectric layers 32, 38, 42, 138, 142, and other layers in interconnect structures 130); and a passive electronic device (Fig 14 bottom plate of capacitor 48B of passive device 48B, [0027]; Examiner is interpreting the bottom plate of capacitor 48B as the passive electronic device, as drawn to [0077] of the instant application disclosing that passive device/structure 510 may represent one portion of a passive device, e.g. a capacitor plate) having a seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device), the passive electronic device (Fig 14 bottom plate of capacitor 48B of passive device 48B, [0027]) within one (Fig 14 layer with dielectric layers 142 and 42 bonded together) of the plurality of backside layers (Figs 1, 2, 14 dielectric layers 32, 38, 42, 138, 142, and other layers in interconnect structures 130), the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device) extending through the passive electronic device (Fig 14 bottom plate of capacitor 48B of passive device 48B, [0027]) substantially parallel (Fig 14) to the logic layer (Fig 14 unlabeled layer in substrate 114).
Regarding claim 18, Hu as modified in claim 15 teaches the passive electronic device (Fig 14 bottom plate of capacitor 48B of passive device 48B, [0027]) comprises a first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) between the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]) and the logic layer (Fig 14 unlabeled layer in substrate 114) and a second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]) over the seam (Fig 14 bottom plate of capacitor 48B, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]), the first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) having a different material structure (since the metal pads were formed as different times the material structure would be different) from the second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]).
Regarding claim 21, Hu teaches an interconnect structure (Fig 14 TSV 116 connected to bond pad labeled 146 extending through to unlabeled TSVs in die 4) within the backside layer (Fig 14 layer with dielectric layers 142 and 42 bonded together), wherein a height of the passive device (Fig 14 passive device 48B, [0027]) is no greater than (the interconnect structure extends through multiple dielectric layers so the height is greater than the height of the passive device) a height of the interconnect structure (Fig 14 TSV 116 connected to bond pad labeled 146 extending through to unlabeled TSVs in die 4).
Regarding claim 22, Hu teaches the backside layer (Fig 14 layer with dielectric layers 142 and 42 bonded together) extends across at least two (Fig 14 die 112 and device die 4, [0031]) of the plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2 which has device die 4, [0031]).
Response to Arguments
Applicant’s arguments, see 35 USC §112 section on page 10, filed May 15, 2026, with respect to arguments presented have been fully considered and are persuasive. The 35 USC §112 rejection of claims 13-14 has been withdrawn.
Applicant’s arguments, see 35 USC §103 section on page 10, filed May 15, 2026, with respect to the rejection(s) of claim(s) 1-4, 9-15, and 18 under 35 USC §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of Hu.
Hu teaches many different backside layers. As it relates to claim 1, the backside layer of Hu having the passive device is taught to be two surfaces hybrid bonded. Examiner interprets the resultant structure to be one backside layer. The seam being located within the layer.
In relation to claim 15, [0077] of the instant application discloses that the passive device/structure shown in Figs 5 and 6 may be a portion of a passive device, such as a capacitor plate. Hu teaches a structure substantially identical to the passive device disclosed, thus the limitation of “the passive electronic device [is] within one of the plurality of backside layers” is taught by Hu.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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