DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I and Species D in the reply filed on December 26, 2025 is acknowledged.
Claims 5-8, 16-17, and 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 26, 2025.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “backside layer comprising a plurality of passive devices” from claim 2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because the figures do not have indicators or markings to indicate height or width as needed for claims 11 and 13-14. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 14 is objected to because of the following informalities:
Claim 14 uses the limitation “the back side” in lines 2 and 3. There is no indication that this instance of “the back side” is different from “the back side of the logic layer” in claim 1. Applicant is asked to add a reference similar to claim 1 such that the limitation of “the back side” in claim 14 reads “the back side of the passive device” to prevent confusion with the back side of the logic layer rom claim 1
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, the limitation of “the via has a width in a direction parallel to the logic layer” in line 2 can present confusion. The via and logic layer are 3-dimensional objects and have multiple surfaces, which may be at different angles to each other and the drawings can only convey a slice (specific view) of the device. The claim does not further specify which direction is being used with to compare the width, i.e. into the page, parallel to the page, or a third angle. For purposes of examination, Examiner will interpret the direction of the width to be that shown in the figure.
Regarding claim 14, similar to claim 13, the direction to measure the and compare lengths can present confusion. The direction for comparing the lengths can also be taken into the page instead of the direction as shown in the figure. For purposes of examination, Examiner will interpret the direction for comparison to be that shown in the figure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et. al. (US 20190148342 A1), hereinafter Hu.
Regarding claim 1, Hu teaches a device (Fig 14 package 82, [0047]) comprising: a logic layer (Fig 14 unlabeled layer in substrate 114) arranged as a plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2, [0031]), the logic layer (Fig 14 unlabeled layer in substrate 114) having a front side (Fig 14 top side of logic layer) and a back side (Fig 14 top side of logic layer); a plurality of interconnect structures (Fig 14 vias 68/116, metal lines 66/70) formed over the front side (Fig 14 top side of logic layer) of the logic layer (Fig 14 unlabeled layer in substrate 114); and a passive device (Fig 14 passive device 48B, [0027]; the passive device may be a capacitor, an inductor, a transformer, a resistor, or the like, [0027]) formed over the back side (Fig 14 bottom side of logic layer) of the logic layer (Fig 14 unlabeled layer in substrate 114), the passive device (Fig 14 passive device 48B, [0027]) having a seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device), the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device) extending through (Fig 15) the passive device (Fig 14 passive device 48B, [0027]) substantially parallel (Fig 2, [0033]) to the logic layer (Fig 14 unlabeled layer in substrate 114).
Regarding claim 2, Hu as modified in claim 1 teaches the passive device (Fig 12 passive device 48B, [0027]) is in a backside layer (Fig 12 interconnect structure 30, [0020]) comprising a plurality of passive devices (Fig 12 passive device 48D/E/F) and a plurality of vias (Fig 12 vias 44, [0024]).
Regarding claim 3, Hu as modified in claim 2 teaches one of the plurality of vias (Hu: Fig 14 TSVs 16, [0055]) is coupled to the logic layer (Fig 12 unlabeled layer in substrate 114) to deliver power (the structure of Hu is substantially identical to that of the claim, thus the function is presumed to be inherent, MPEP 2112.01(I)) to the logic layer (Fig 12 unlabeled layer in substrate 114).
Regarding claim 4, Hu as modified in claim 1 teaches a support structure (Fig 14 unlabeled structure corresponds to Fig 2 interconnect structure 130, [0029]) between the logic layer (Fig 14 unlabeled layer in substrate 114) and the passive device (Fig 14 passive device 48B, [0027]).
Regarding claim 9, Hu as modified in claim 1 teaches the passive device (Fig 14 passive device 48B, [0027]) comprises a first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) between the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]) and the logic layer (Fig 14 unlabeled layer in substrate 114) and a second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]) over the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]), the first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) having a different material structure (since the metal pads were formed as different times the material structure would be different) from the second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]).
Regarding claim 10, Hu as modified in claim 1 teaches the passive device (Fig 14 passive device 48B, [0027]) comprises a conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]), and the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device; in this case the boundary between the lower electrode and the insulating material) comprises a different chemical composition (Since there are different materials formed in the transition from electrode to insulating material, there will be the presence of process gases, no matter how small of an amount present in the seam) from a region (Fig 14 capacitor insulator of capacitor 48) of the passive device (Fig 14 passive device 48B, [0027]) above the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device).
Regarding claim 11, Hu as modified in claim 1 teaches the passive device (Fig 14 passive device 48B, [0027]) has a base (top of Fig 14 passive device 48B, [0027]) parallel to the logic layer (Fig 14 unlabeled layer in substrate 114) and a height in a direction perpendicular to the logic layer (Fig 14 unlabeled layer in substrate 114)
Hu fails to teach the seam is located at a height above the base in a range between 40% and 60% of the height.
However, Hu teaches the capacitor is formed of metal pads and dielectric layers ([0033]). One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the thicknesses of the dielectric layers would be dependent on the desired properties of the layers. The height of the seam is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the thickness of the dielectric layers as Hu and one of ordinary skill in the art before the effective filing date of the claimed invention has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at thicknesses of the dielectric material and etch stop layer such that a height of the seam above the base is in a range between 40% and 60% of the height, in order to achieve the desired balance properties of the dielectric layer and capacitance of the capicitor, as taught by Hu and one of ordinary skill in the art before the effective filing date of the claimed invention. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed height is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed height).
Regarding claim 12, Hu as modified in claim 1 teaches a via (Fig 14 via 16, [0055]) coupled to a back side (Fig 14 bottom side of passive device 48B) of the passive device (Fig 14 passive device 48B, [0027]).
Regarding claim 13, Hu as modified in claim 12 teaches the passive device (Fig 14 passive device 48B, [0027]) has a height in a direction perpendicular to the logic layer (Fig 14 unlabeled layer in substrate 114), and the via (Fig 14 not shown but coupled to via 116, [0048]) has a width in a direction parallel to the logic layer (Fig 14 unlabeled layer in substrate 114).
Hu as modified in claim 12 fails to teach the width of the via greater than the height of the passive device.
However, Hu teaches the passive device may be a capacitor, an inductor, a resistor among other things ([0027]). One having ordinary skill in the art before the effective filing date of the claimed invention would recognize that the different passive devices would have different dimensions, in particular a resistor would have the smallest height of the passive devices. The height of the passive device as compared to the width of the via is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the height of the passive device and the width of the via as Hu and one of ordinary skill in the art before the effective filing date of the claimed invention has identified the height and width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the width of the via being greater than the height of the passive device, in order to achieve the desired balance properties of the passive device and properties of the via, as taught by Hu and one of ordinary skill in the art before the effective filing date of the claimed invention. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed height/width relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed height/width relationship).
Regarding claim 14, Hu as modified in claim 1 teaches a cross-section (Fig 14) of the passive device (Fig 14 passive device 48B, [0027]) has a back side (Fig 14 bottom side of passive device 48B) parallel to the logic layer (Fig 14 unlabeled layer in substrate 114) and a front side (Fig 14 top side of passive device 48B) parallel (Fig 14) to the logic layer (Fig 14 unlabeled layer in substrate 114), the back side (Fig 14 bottom side of passive device 48B) farther from (Fig 14) the logic layer (Fig 14 unlabeled layer in substrate 114) than the front side (Fig 14 top side of passive device 48B), wherein a length of the back side (Fig 14 bottom side of passive device 48B) is longer (due to differences in manufacturing the length of the backside may be longer than the length of the front side) than a length of the front side (Fig 14 bottom side of logic layer).
Regarding claim 15, Hu teaches a wafer device (Fig 14 wafer 2, [0015]) comprising: a logic layer (Fig 14 unlabeled layer in substrate 114) comprising a plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2, [0031]), one of the plurality of dies (Fig 14 a plurality of device die 112 may be bonded to wafer 2, [0031]) comprising a plurality of transistors (Fig 14 unlabeled transistor in substrate 114; the art lists the device die 112 with substrate 114 as a logic die, which may be a CPU die, a MCU die, etc.; it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that there would be more than the one transistor shown in Fig 14); and a power delivery structure (Fig 14 interconnect structure 30, unlabeled interconnect structure 130 from Fig 2, vias 16 through substrate 20) on a backside (Fig 14 bottom side) of the logic layer (Fig 14 unlabeled layer in substrate 114), the power delivery structure (Fig 14 interconnect structure 30, unlabeled interconnect structure 130 from Fig 2, vias 16 through substrate 20) comprising a via coupled to the logic layer (Fig 14 unlabeled layer in substrate 114), the power delivery structure (Fig 14 interconnect structure 30, unlabeled interconnect structure 130 from Fig 2, vias 16 through substrate 20) further comprising a passive electronic device (Fig 14 passive device 48B, [0027]; the passive device may be a capacitor, an inductor, a transformer, a resistor, or the like, [0027]) having a seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device), the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device) extending through the passive electronic device substantially parallel (Fig 14) to the logic layer (Fig 14 unlabeled layer in substrate 114).
Regarding claim 18, Hu as modified in claim 15 teaches the passive electronic device (Fig 14 passive device 48B, [0027]; the passive device may be a capacitor, an inductor, a transformer, a resistor, or the like, [0027]) comprises a first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) between the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]) and the logic layer (Fig 14 unlabeled layer in substrate 114) and a second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]) over the seam (Fig 15 capacitor 48, [0027]; the seam is a discontinuity between two portions in the device; in this case the discontinuity between the metal pads of device dies 112 and 4, [033]), the first portion of conductive material (Fig 14 top layer of bottom electrode of passive device 48B, [0033]) having a different material structure (since the metal pads were formed as different times the material structure would be different) from the second portion of conductive material (Fig 14 bottom layer of bottom electrode of passive device 48B, [0033]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et. al. (US 20200152855 A1) teaches an inductor with a core within an air gap
Paital et. al. (US 20200343049 A1) teaches a seam between an electrode of a capacitor due that appears similar to diffusion bonding. The seam was formed due to the manufacturing process.
Ichimori (US 20060054949 A1) teaches seams formed in a capacitor multilayer electrode. The multilayer electrode being made of different metals.
Pyo (US 20050014317 A1) teaches it was known in the art voids or seams may occur during the filling process for forming inductors and provides a means to reduce the defects.
Di et. al. (CN 111739703 A) teaches seams between different materials used in the formation of a resistive element.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813