DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/30/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shim (US 20200013797 A1) in view of Angyal et al. (US 20050242414 A1).
Regarding claim 1, Shim discloses a semiconductor device (Figs. 14B-14C), comprising:
a substrate (100)
a cell array structure (ST) on the substrate, the cell array structure comprising a plurality of electrodes (EL) that are stacked and spaced apart from each other;
a vertical channel structure (VS) that penetrates the cell array structure and is electrically connected (via LSP) to the substrate ([0038]);
a conductive pad (BCP) in an upper portion of the vertical channel structure;
an interlayer insulating layer (ILD or ILD/130) on the cell array structure;
a bit line (BL) on the cell array structure and electrically connected (via BPLG) to the conductive pad; and
a first stress release layer (SPP, [0047]) between the cell array structure and the bit line on a top surface of the interlayer insulating layer (Figs. 14B-14C), wherein the first stress release layer (SPP) covers (indirectly) a bottom surface of the bit line (BL. Fig 14A; SPP overlaps with BL and indirectly covers BL. Fig. 14B; SPP is below BL and despite 140 being interposed, SPP indirectly covers BL. Note: the claim should recite --the first stress release layer covers and directly physically contacts a bottom surface of the bit line—per Fig. 9A of applicant and the relationship between FSL3 and BL; the examiner’s suggestion would overcome Shim).
Shim fails to disclose (a) wherein the first stress release layer comprises organosilicon polymer, and (b) a carbon concentration of the first stress release layer is higher than a carbon concentration of the interlayer insulating layer.
Angyal discloses (a) wherein the first stress release layer (104) comprises organosilicon polymer ([0036-0037], Fig. 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date to employ the material of Angyal in Shim so as to provide high polishing selectivity, a moisture and oxygen barrier, provide adhesion to underlying layer and/or so as to reduce a propensity to cracking in stacks (Angyal, [0087]).
Limitation (b) a carbon concentration of the first stress release layer is higher than a carbon concentration of the interlayer insulating layer is met by the combination because layer 104 (the claimed “first stress release layer”) of Angyal comprises carbon ([0036-0037] – “SiCOH material, such as Black Diamond.TM., an organosilicon glass (OSG)”) while layer ILD or ILD/130 (the claimed “interlayer insulating layer”) of Shim lack carbon ([0032] – “dielectric patterns ILD may be silicon oxide layers” and [0065] – “The third interlayer dielectric layer 130 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride”).
Regarding claim 3, Shim/Angyal discloses wherein the first stress release layer (104) comprises carbon (C), hydrogen (H), silicon (Si), and oxygen (O) ([0036-0037] – “SiCOH material, such as Black Diamond.TM., an organosilicon glass (OSG)”)
Shim/Angyal fails to disclose the carbon concentration of the first stress release layer is about 20 at% to 40 at%, a silicon concentration of the first stress release layer is about 3 at% to 16 at%, and an oxygen concentration of the first stress release layer is about 3 at% to 16 at%.
However, Shim/Angyal discloses “The deposition is accomplished by altering the process conditions (e.g., gas flow, power, pressure, bias) which were being used to deposit the primary dielectric layer 102 to yield a film 104 under compressive stress while maintaining a low dielectric constant” ([0033]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at values within the claimed ranges in Shim/Angyal so as to allow for tailoring of the stress release layer composition to provide high polishing selectivity, a moisture and oxygen barrier, provide adhesion to underlying layer and/or so as to reduce a propensity to cracking in stacks (Angyal, [0033] and [0087]), and/or, as a matter of routine experimentation (MPEP 2144.05) since [0033] of Angyal establishes that altering process conditions is desirable.
Regarding claim 5, Shim/Angyal fails to disclose the semiconductor device of claim 1, wherein a density of the first stress release layer is lower than a density of the interlayer insulating layer.
However:
Layer 104 (the claimed “first stress release layer”) of Angyal comprises organosilicon polymer ([0036-0037] – “SiCOH material, such as Black Diamond.TM., an organosilicon glass (OSG)”) which matches that of claim 1,
Layer ILD or ILD/130 (the claimed “interlayer insulating layer”) of Shim includes silicon oxides ([0032] – “dielectric patterns ILD may be silicon oxide layers” and [0065] – “The third interlayer dielectric layer 130 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride”) which matches the materials of applicant’s interlayer insulating layers ([0093] of published application US 20230230937 A1), and
Angyal discloses “The deposition is accomplished by altering the process conditions (e.g., gas flow, power, pressure, bias) which were being used to deposit the primary dielectric layer 102 to yield a film 104 under compressive stress while maintaining a low dielectric constant” ([0033]).
In view of the materials commonality plus the disclosure of the prior art of altering process condition to form the stress release layer, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at density values meeting the claim in Shim/Angyal so as to allow for tailoring of the stress release layer composition to provide high polishing selectivity, a moisture and oxygen barrier, provide adhesion to underlying layer and/or so as to reduce a propensity to cracking in stacks (Angyal, [0033] and [0087]), and/or, as a matter of routine experimentation (MPEP 2144.05) since [0033] of Angyal establishes that altering process conditions is desirable.
Regarding claim 6, Shim/Angyal fails to disclose the semiconductor device of claim 1, wherein a silicon concentration of the first stress release layer is lower than a silicon concentration of the interlayer insulating layer.
However:
Layer 104 (the claimed “first stress release layer”) of Angyal comprises organosilicon polymer ([0036-0037] – “SiCOH material, such as Black Diamond.TM., an organosilicon glass (OSG)”) which matches that of claim 1,
Layer ILD or ILD/130 (the claimed “interlayer insulating layer”) of Shim includes silicon oxides ([0032] – “dielectric patterns ILD may be silicon oxide layers” and [0065] – “The third interlayer dielectric layer 130 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride”) which matches the materials of applicant’s interlayer insulating layers ([0093] of published application US 20230230937 A1), and
Angyal discloses “The deposition is accomplished by altering the process conditions (e.g., gas flow, power, pressure, bias) which were being used to deposit the primary dielectric layer 102 to yield a film 104 under compressive stress while maintaining a low dielectric constant” ([0033]).
In view of the materials commonality plus the disclosure of the prior art of altering process condition to form the stress release layer, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at silicon concentrations meeting the claim in Shim/Angyal so as to allow for tailoring of the stress release layer composition to provide high polishing selectivity, a moisture and oxygen barrier, provide adhesion to underlying layer and/or so as to reduce a propensity to cracking in stacks (Angyal, [0033] and [0087]), and/or, as a matter of routine experimentation (MPEP 2144.05) since [0033] of Angyal establishes that altering process conditions is desirable.
Regarding claim 9, Shim/Angyal fails to disclose, with respect to the embodiment of Figs. 14B-14C, the semiconductor device of claim 1, further comprising: a lower level layer, which is below the substrate and comprises a peripheral circuit.
In a separate embodiment (Fig. 17B), Shim discloses a lower level layer (PS), which is below the substrate (100) and comprises a peripheral circuit (PS, Fig. 17B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the lower level as claimed in the embodiment of Figs. 14B-14C of Shim/Angyal so as include “row and column decoders, a page buffer, and/or control circuits” (Shim, [0071]).
Regarding claim 10, Shim/Angyal discloses the semiconductor device of claim 1, wherein a (bottommost) surface of the substrate (100) opposite the first stress release layer (SPP) is free of stress release layers thereon (none shown at the bottom of 100, Figs. 14B-14C).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shim (US 20200013797 A1) in view of Angyal et al. (US 20050242414 A1) as applied to claim 1 above, and further in view of Yang et al. (US 9165941 B2).
Regarding claim 2, Shim/Angyal discloses the semiconductor device of claim 1, further comprising a bit line contact (BPLG) electrically connecting the bit line (BL) to the conductive pad (BCP, Fig. 14B) but fails to disclose wherein a top surface of the first stress release layer is at a same level as a top surface of the conductive pad.
Yang discloses (Fig. 2I) wherein a top surface of the first stress release layer (130) is at a same level as a top surface of a drain (153)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the location of the first stress release layer of Shim/Angyal to meet the claim by having BCP and SPP share a common upper surface in view of Yang so as to increase the likelihood of achieving prevention or mitigation of warping during fabrication (Yang, “…further comprises a stress buffer layer 130, as illustrated in FIG. 2I, which prevents or mitigates the warping of the substrate 100 during a fabrication process”).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shim (US 20200013797 A1) in view of Angyal et al. (US 20050242414 A1) as applied to claim 1 above, and further in view of Shimabukuru et al. (US 20180374865 A1).
Regarding claim 7, Shim/Angyal fails to disclose the semiconductor device of claim 1, wherein the cell array structure comprises a first stack and a second stack on the first stack, the semiconductor device further comprises a second stress release layer between the first stack and the second stack, and the second stress release layer comprises a same organosilicon polymer as the first stress release layer.
Shimabukuru discloses (Fig. 11) wherein the cell array structure comprises a first stack (below 182) and a second stack (above 182) on the first stack, the semiconductor device further comprises a second stress release layer (182) between (indirectly) the first stack and the second stack (Fig. 11).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the second stack and stress release layer of Shimabukuro in Shim/Angyal so as to increase packaging density and expand the functionality of the semiconductor device.
Regarding “the second stress release layer comprises a same organosilicon polymer as the first stress release layer”, it would have been obvious to one of ordinary skill in the art, before the effective filing date to employ the same stress release layer material in Shim/Angyal/Shimabukuru so as to simplify the manufacturing of the semiconductor device and/or so as to to provide high polishing selectivity, a moisture and oxygen barrier, provide adhesion to underlying layer and/or so as to reduce a propensity to cracking in stacks (Angyal, [0087]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shim (US 20200013797 A1) in view of Angyal et al. (US 20050242414 A1) as applied to claim 1 above, and further in view of Kim et al. (US 20160093547 A1).
Regarding claim 4, Shim/Angyal fail to disclose the semiconductor device of claim 1, wherein the organosilicon polymer comprises a unit of following chemical formula 1, a unit of following chemical formula 2, or a combination of the units of the following chemical formulas 1 and 2:
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where R1, R2, R3, and R4 are each independently a hydrogen, an alkyl group having 1 to 5 carbon atoms, an alkenyl group having 2 to 6 carbon atoms, an alkynyl group having 2 to 6 carbon atoms, an alkoxy group having 1 to 5 carbon atoms, an aryl group having 6 to 10 carbon atoms, a thiol group, a thiolalkyl group having 1 to 5 carbon atoms, a fluoroalkyl group having 1 to 5 carbon atoms, or an aminoalkyl group having 1 to 5 carbon atoms, and
each of n and m is an integer between 100 and 10,000.
Kim discloses wherein the organosilicon polymer ([0042] – “polyorganosiloxane resin”) comprises a unit of following chemical formula 1, a unit of following chemical formula 2, or a combination of the units of the following chemical formulas 1 and 2:
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(
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)
where R1, R2, R3, and R4 ([0043]) are each independently a hydrogen, an alkyl group having 1 to 5 carbon atoms (C1 to C10), an alkenyl group having 2 to 6 carbon atoms (C2 to C20), an alkynyl group having 2 to 6 carbon atoms (C2 to C20), an alkoxy group having 1 to 5 carbon atoms (C1 to C10), an aryl group having 6 to 10 carbon atoms (C6-C20), a thiol group, a thiolalkyl group having 1 to 5 carbon atoms, a fluoroalkyl group having 1 to 5 carbon atoms, or an aminoalkyl group having 1 to 5 carbon atoms, and
each of n and m is an integer between 100 and 10,000 (“n may be 0 to about 100 on average, e.g., n may be an integer of 0 to about 100”; 100 being explicitly disclosed).
The examiner takes the position that the ranges of the prior art anticipate the claim ranges with sufficient specificity (MPEP 2131.03).
In the event the ranges of the prior art do not anticipate the claim ranges with sufficient specificity (MPEP 2131.03), which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to select values that anticipate the claim based on Kim so as to tailor the composition of the polyorganosiloxane to “help prevent cracking at an interface between an epoxy molding composition and the silicon-based die adhesive, thereby improving reliability” (Kim, [0047]).
Finally, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the material disclose or suggested by Kim in Shim/Angyal so as to “help prevent cracking at an interface between an epoxy molding composition and the silicon-based die adhesive, thereby improving reliability” (Kim, [0047]).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose or suggest a source contact plug vertically extending from a first upper interconnection line to the substrate; and a penetration via vertically extending from a second upper interconnection line to a region below the substrate, wherein a top surface of the first stress release layer is at a same level as a top surface of at least one of the separation structure, the source contact plug, or the penetration via.
Response to Arguments
Applicant's arguments filed 6.12.2026 have been fully considered but they are not persuasive.
The applicant alleges:
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This is not found persuasive because Shim discloses wherein the first stress release layer (SPP) covers (indirectly) a bottom surface of the bit line (BL).
In Fig. 14A, SPP overlaps with BL and indirectly covers BL as claimed.
In Fig. 14B, SPP is below BL and despite 140 being interposed, SPP indirectly covers BL as claimed.
The claim should recite --the first stress release layer covers and directly physically contacts a bottom surface of the bit line—per Fig. 9A of applicant and the relationship between FSL3 and BL; the examiner’s suggestion would overcome Shim but also change the scope of the claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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