DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: FULL WAFER DEVICE WITH FRONT SIDE PASSIVE ELECTRONIC COMPONENTS WITH A SEAM EXTENDING THROUGH A PASSIVE ELECTRONIC COMPONENT
Election/Restrictions
Applicant’s election without traverse of claims 1-8, 11-17 in the reply filed on 12/26/2025 is acknowledged. This follows from applicant’s election, without traverse, of Group I (claims 1-18) and further election of “Species A of Fig. 7”, on which claims 1-8, 11-17 and 19-20 read – see reply filed on 12/26/2025.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 5-14 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5-14 of of copending Application No. 17930801. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following:
Claim 1 of current application reads on claim 1 of application 17930801, noting that “support structure” for a logic layer (recited additionally in claim 1 of current application) is well known in the art to support layers like a logic layer; the recitation “computing logic over the front side of the support structure” (of claim 1 of current application) reads on the recited “logic layer” of claim 1 of application 17930801; the recitation “a back end layer over the computing logic, the back end layer comprising a passive electronic structure” (of claim 1 of current application) reads on the recited “a passive device formed over the back side of the logic layer”. Also, as support layers or substrates on which logic and other layers are formed, typically arrange all layers in parallel, and hence the recitation “substantially parallel to the support structure” (of claim 1 of current application) reads on the recited “substantially parallel to the logic layer”. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify claim 1 of application 17930801to include the well known “support structure” recited in claim 1, and associated changes listed above. The ordinary artisan would have been motivated to modify as above for at least the purpose of using a substrate (i.e. a support structure) on which to build all the other layers for ease of manufacturing and later mounting in electronic modules.
Claims 5-14, respectively, of current application are substantially the same as claims 5-14 of application 17930801, but claims 9-10 have withdrawn, and as such, claims 5-8 and 11-14 are rejected under above double patenting.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites “the passive electronic structure has a height in a direction perpendicular to the support structure, and the via has a width in a direction parallel to the support structure”. However, the support structure as well as the via are 3-dimensional objects and have multiple surfaces, which may be at different angles (including right angles) to each other. Without specifying which surface is used to determine “parallel” or “perpendicular”. For the purposes of this office action, this limitation will not be considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8, 12-13 and 15-17 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin (US 20200152855 A1), hereinafter Lin-855.
Regarding claims 1 and 6, Lin-855 (refer to Figure 29; also see other Figures for details as outlined below) teaches a device comprising:
a support structure (1602, para 80) having a front side and a back side;
computing logic over the front side of the support structure, the computing logic arranged as a plurality of dies (1604, described as “device layers 1604” which “may include features of one or more transistors 1640” in para 81); and
a back end layer over the computing logic, the back end layer comprising a passive electronic structure (such as an inductor, para 87 describes "An inductor/core assembly 100 included in the metallization stack 1619 may be referred to as a “back-end” assembly"; Figure 1A shows inductor 102 – see para 31) having a seam, wherein the seam is an air gap (112, describes as “air gap 112” in para 31 – see Figure 1A; also para 167 discloses "an inductor and an air gap in an interior of the inductor" in "Example 146"), the seam extending through the passive electronic structure substantially parallel to the support structure (compare orientation of 100 in Figure 29 with respect to support structure 1602, and compare it with orientation of air gap 112 in detail of 100 shown in Figure 1A).
Note: that the recitation of “the seam” being “parallel to the support structure” of claim 1 is very broad. The shape of the seam is not recited and the claim does not require any specific side or face of the seam to be parallel to any specific face of the support structure.
Regarding claim 2, Lin-855 teaches the device of claim 1, further comprising a second back end layer over the back end layer, the second back end layer comprising an interconnect structure (a plurality of back end layers are taught for interconnection – see para 87 that describes "one or more interconnect layers disposed on the device layer 1604" that are "illustrated in FIG. 29 as interconnect layers 1606-1610")
Regarding claims 3-4 , Lin-855 teaches the device of claim 1, further comprising a power via (as recited in claim” and “a signal via” (as recited in claim 4) extending through the back end layer to one of the plurality of dies (see para 89 that describes "vias 1628b may be arranged to route electrical signals"; AND para 87 that describes "Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 29 as interconnect layers 1606-1610)".
Regarding claim 8, Lin-855 teaches the device of claim 1, wherein the passive electronic structure comprises a conductive material, and the seam is an air gap (112 – see Figure 1A) within the conductive material (110, comprising "electrode material 110-1" and "electrode material 110-1" of the “magnetic core 104” of the inductor - see Figure 1A and para 36).
Regarding claims 12-13, Lin-855 teaches the device of claim 1, further comprising a via coupled to the passive electronic structure and formed over the passive electronic structure (para 89 of Lin-855 describes "vias 1628b may be arranged to route electrical signals"), as recited in claim 12, wherein (as recited in claim 13) the passive electronic structure has a height in a direction perpendicular to the support structure, and the via (1628b of Figure 29) has a width in a direction parallel to the support structure, the width of the via greater than the height of the passive electronic structure (which is part of 100 of Figure 29); also see 35 USC 112, 2nd paragraph rejection above.
Regarding claim 15, Lin-855 teaches a wafer (see Figures 28-29 and para 17) comprising:
a logic layer comprising a plurality of dies, one of the plurality of dies comprising a plurality of transistors (1604, described as “device layers 1604” which “may include features of one or more transistors 1640” in para 81); and
an interconnect layer over the logic layer, the interconnect layer comprising an interconnect structure electrically coupled to one of the plurality of transistors (a plurality of back end layers are taught for interconnection – see para 87 that describes "one or more interconnect layers disposed on the device layer 1604" that are "illustrated in FIG. 29 as interconnect layers 1606-1610"), the interconnect layer further comprising a passive electronic device (such as an inductor, para 87 describes "An inductor/core assembly 100 included in the metallization stack 1619 may be referred to as a “back-end” assembly"; Figure 1A shows inductor 102 – see para 31) having a seam (wherein the seam is an air gap 112, describes as “air gap 112” in para 31 – see Figure 1A; also para 167 discloses "an inductor and an air gap in an interior of the inductor" in "Example 146"), the seam extending through the passive electronic device substantially parallel to the logic layer (compare orientation of 100 in Figure 29 with respect to logic layer 1602, and compare it with orientation of seam; i.e. air gap 112 in detail of 100 shown in Figure 1A).
Regarding claim 16, Lin-855 teaches the wafer of claim 15, wherein the passive electronic device is a resistor or an inductor (such as an inductor, para 87 describes "An inductor/core assembly 100 included in the metallization stack 1619 may be referred to as a “back-end” assembly"; Figure 1A shows inductor 102 – see para 31).
Regarding claim 17, Lin-855 teaches the wafer of claim 15, wherein the passive electronic device comprises a conductive material, and the seam is an air gap within the conductive material (112 – see Figure 1A) within the conductive material (110, comprising "electrode material 110-1" and "electrode material 110-1" of the “magnetic core 104” of the inductor - see Figure 1A and para 36).
Claims 1, 3, 4, 7 and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin (US 20100309605), hereinafter Lin-605.
Regarding claims 1 and 7, Lin-605 teaches a device comprising:
a support structure (non-active part of 40, described as "semiconductor substrate 40 and is formed as part of an integrated circuit" in para 25; best seen in Figure 4) having a front side and a back side;
computing logic over the front side (i.e. upper side in Figure 4) of the support structure, the computing logic arranged as a plurality of dies (comprising "PMOS transistor" and "NMOS transistor" described in para 25); and
a back end layer (comprising “through vias 43b” – see para 26, best seen in Figure 4 and detail of Figure 9, where similar “thorough vias 155b” are shown and described in para 34; also see similar vias 16 and 18 of prior art shown in Figure 1 and this layer is described as “back-end-of-line” stack – see para 5) over layer the computing logic,
the back end layer comprising a passive electronic structure (5 of Figures 9-10, described as “3T-MOM capacitor” in para 20, also see para 32, especially 1st sentence); having a seam (seam formed due to “discontinuity 160” – see para 33, best seen in Figure 10; also see similar discontinuity between B and C in Figure 8) the seam extending through the passive electronic structure (i.e. the “3T-MOM capacitor” described above) substantially parallel to the support structure (the seam is substantially rectangular and at least one side of the seam is parallel to 142c in Figure 8 and 152c in Figure 10, which are parallel to at least one side of the support structure), wherein (as recited in claim 7) wherein the passive electronic structure is a capacitor (5 of Figures 9-10, described as “3T-MOM capacitor” in para 20, also see para 32, especially 1st sentence).
Note: that the recitation of “the seam” being “parallel to the support structure” of claim 1 is very broad. The shape of the seam is not recited and the claim does not require any specific side or face of the seam to be parallel to any specific face of the support structure.
Regarding claim 3, Lin-605 teaches the device of claim 1, further comprising a via that is capable of being a power via (comprising “through vias 43b” – see para 26; corresponding to “terminal A” which are connected to “ground or an output terminal” – see para 25, best seen in Figure 4 and detail of Figure 9, where similar “thorough vias 155b” are shown and described in para 34) extending through the back end layer (see similar vias 16 and 18 of prior art shown in Figure 1 and this layer is described as “back-end-of-line” stack – see para 5) to one of the plurality of dies (such as for connecting to source or drain). Note that power includes low power and high power.
Regarding claim 4, Lin-605 teaches the device of claim 3, further comprising a signal via (via corresponding to terminal C in Figure 4 which connects to “a drain of a NMOS transistor” of the dies, see para 25) extending through the back end layer (see Figure 4) to one of the plurality of dies.
Regarding claim 12, Lin-605 teaches the device of claim 1, further comprising a via coupled to the passive electronic structure and formed over the passive electronic structure (para 26 describes “through vias 43b” and these correspond to “terminal A” which are connected to “ground or an output terminal” – see para 25, best seen in Figure 4 and detail of Figure 9, where similar “thorough vias 155b” are shown and described in para 34).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin-855 in view of Mori (JP 2010034483 A), hereinafter Mori. A copy of English abstract and original document of Mori is included with this office action.
.
Regarding claim 5, Lin-855 teaches the device of claim 1, but does not teach wherein the passive electronic structure is “a resistor”. Mori (JP 2010034483 A) teaches that an resistor may also have a seam, such as an air gap to promote circulation (see English abstract). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Lin so that the passive electronic structure comprising the seam is “a resistor”. The ordinary artisan would have been motivated to modify Lin for at least the purpose of improving the circulation of heat, which can prevent overheating of the resistor.
Allowable Subject Matter
Claims 11 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 is objected to and would be allowable (if double patenting rejection is also overcome) because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “the passive electronic structure has a base parallel to the support structure and a height in a direction perpendicular to the support structure, and the seam is located at a height above the base in a range between 40% and 60% of the height”.
Claim 14 is objected to and would be allowable (if double patenting rejection is also overcome) because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “wherein a cross-section of the passive electronic structure has a back side parallel to the support structure and a front side parallel to the support structure, the front side farther from the support structure than the back side, wherein a length of the back side is shorter than a length of the front side”.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892