DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-20 in the reply filed on 01/07/26 is acknowledged. The Examiner will withdraw the restriction and will examine claims 1-20.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation in claim 11, “a bonding layer coupling the transistor layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9,11, 15-17 is/are rejected under 35 U.S.C. 102(a2) as being anticipated by Hush et al., (Hush) US 2023/0051863.
Regarding claim 1, Hush shows in FIG. 1-C-3C, a device comprising: a computing logic layer (124)[0038] comprising a plurality of transistors (shown in FIG. 1C); a local interconnect layer (115)(comprise metal connected to the transistor in 124) coupled to a first side of the computing logic layer (124); a plurality of global interconnect layers (120)[0038] coupled to a second side of the computing logic layer (124)(metal connecting to the transistors in 124), the second side opposite the first side; and a transistor layer (transistor shown in the memory logic area)(see FIG. 1C) formed between a first of the plurality of global interconnect layers (120) and a second of the plurality of global interconnect layers (layer below the second set of transistors)(part of 124)[0038,0039], the transistor layer comprising a second plurality of transistors [id.].
Regarding claims 2-4, Hush shows in FIG. 1-C-3C, a wherein the computing logic layer is arranged as a plurality of dies (dies in 114,115); wherein interconnect structures in the local interconnect layer (115) correspond to respective dies of the computing logic layer; wherein a first of the plurality of dies (dies in 114,115) has the same structure as a second of the plurality of dies (same structure shown in FIG. 1C).
Regarding claim 5, Hush shows in FIG. 1-C-3C, a device wherein a global interconnect structure (120) of at least one of the plurality of global interconnect layers is coupled between two of the plurality of dies (dies in layer 124 and layer 122).
Regarding claim 6, Hush shows in FIG. 1-C-3C, a device wherein at least one transistor of the transistor layer forms a switch [0064], the switch coupled between a first die (in 124) and a second die (in 122) of the plurality of dies.
Regarding claims 7,8, Hush shows in FIG. 1-C-3C, a device further comprising a power via [0020](vias are shown as “TSV” protruding and connecting to the transistors in layer 124,122) extending through the transistor layer to the computing logic layer (124); a signal via [0020,0038] extending through the transistor layer to the computing logic layer (124).
Regarding claim 9, Hush shows in FIG. 1-C-3C, a device wherein the transistor layer comprises thin-film transistors (TFTs) (shown in layer 124,122) (TFT’s are typical transistor in semiconductor chip, wafers).
Regarding claim 11, Hush shows in FIG. 1-C-3C, a device further comprising a bonding layer coupling the transistor layer (part of 124) to one of the plurality of global interconnect layers (120).
Regarding claim 15, Hush shows in FIG. 1-C-3C, a backside interconnect assembly comprising: a plurality of backside interconnect layers (in layer 115) coupled to a back side of a logic layer (124); and an active layer (in 124) formed between a first of the plurality of backside interconnect layers and a second of the plurality of backside interconnect layers (in layer 114), the active layer comprising a plurality of transistors.
Regarding claim 16, Hush shows in FIG. 1-C-3C, a backside interconnect assembly, wherein the logic layer (124) comprises a plurality of dies, and the plurality of backside interconnect layers couple a first die of the logic layer (124) to a second die (in 124) of the logic layer.
Regarding claim 17, Hush shows in FIG. 1-C-3C, a backside interconnect assembly (part of 115), wherein a logic device in the active layer (transistors in layer 124) alternatively couples a first die of the logic layer to a second die of the logic layer or to a third die (124 shows a pluralities of transistors that are parts of dies) of the logic layer (124).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hush as applied to claims 1-9,11, 15-17, and further in view of Or-Bach et al., (Or-Bach) US 2023/0329013.
Regarding claim 10, Hush differs from the claimed invention because he does not explicitly disclose a device wherein the transistor layer comprises a substantially monocrystalline material having a grain size of at least 100 nm.
Or-Bach discloses [0089] a device wherein the transistor layer comprises a substantially monocrystalline material having a grain size of at least 100 nm.
Or-Bach is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Hush. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Or-Bach in the device of Hush because it will increase the yield of the device [0008].
Claim(s) 12-14, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hush as applied to claims 1-9,11, 15-17, and further in view of Kim et al., (Kim) US 2019/0221557.
Regarding claim 12-14, Hush shows in FIG. 1-C-3C, a device wherein a cross-section of a global interconnect structure (120) in one of the plurality of global interconnect layers has a back side parallel to the computing logic layer and a front side parallel to the computing logic layer.
Hush differs from the claimed invention because he does not explicitly disclose a device wherein the front side closer to the computing logic layer than the back side, wherein a length of the back side is longer than a length of the front side; wherein a first dielectric material in the first of the plurality of global interconnect layers is different from a second dielectric material in the second of the plurality of global interconnect layers; wherein the first dielectric material has a first dielectric constant, and the second dielectric material has a second dielectric constant different from the first dielectric constant.
Kim shows in FIG. 25,29, a device wherein the front side closer to the computing logic layer than the back side, wherein a length of the back side (back side of 1792) is longer than a length of the front side; wherein a first dielectric material in the first of the plurality of global interconnect layers is different from a second dielectric material in the second of the plurality of global interconnect layers [0105]; wherein the first dielectric material has a first dielectric constant, and the second dielectric material has a second dielectric constant different from the first dielectric constant [0105].
Kim is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Hush. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Kim in the device of Hush because it will provide a high density device [0003].
Regarding claim 18, Hush shows in FIG. 1-C-3C, a device comprising: a logic layer comprising a plurality of transistors (in 124); a first interconnect layer (above 124 in layer 115) coupled to a first side of the logic layer (124), the first interconnect layer comprising a first dielectric (in 124); a second interconnect layer (120) coupled to a second side of the logic layer, the second side opposite the first side, the second interconnect layer comprising a second dielectric (in 102); and a transistor layer coupled to the second interconnect layer (in 124).
Hush differs from the claimed invention because he does not explicitly disclose a device wherein a second dielectric different from the first dielectric.
Kim shows in FIG. 25,29, a device wherein a second dielectric different from the first dielectric [0105].
Kim is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Hush. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Kim in the device of Hush because it will provide a high-density device [0003].
Regarding claims 19,20, Hush in view of Kim discloses a device, further comprising a third interconnect layer (120 has multiple interconnect layers and also in 114) coupled to the transistor layer (in 124), the transistor layer between the second interconnect layer and the third interconnect layer (in 114); wherein the logic layer comprises a plurality of dies (124 comprises dies).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Examiner
Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813