DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to RCE filed on January 5, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7, 9-10, 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over by Noh et al. (US 2020/0203427, hereinafter Noh) in view of Tsuji et al. (US 2016/0071873, hereinafter Tsuji).
Regarding claim 1, Noh discloses for a semiconductor device comprising that
a semiconductor layer containing silicon (Si) (bottom channel layer 70, see attached and annotated Fig. 35 below), because the bottom channel layer 70 by Noh includes “an intrinsic semiconductor layer such as an undoped polysilicon or a P-doped polysilicon layer doped with P-type ions” ([0087]);
a first insulating layer (a composite insulating layer of the interlayer dielectric layer 30 and the uppermost interlayer dielectric layer 32, Fig. 35) provided in a first direction of the semiconductor layer (vertical direction in Fig. 35), because the interlayer dielectric layer 30 and the uppermost interlayer dielectric layer 32 by Noh are disposed above the bottom channel layer 70 (Fig. 35), i.e., along the vertical direction in the claimed invention;
a second insulating layer (third gate dielectric layer 63 or first gate dielectric layer 61, Fig. 35) surrounded by the semiconductor layer (bottom 70, Fig. 35) in a first cross section perpendicular to the first direction (lower cross section, see Fig. 35 below), because a lateral portion of the third gate dielectric layer 63 or the first gate dielectric layer 61 by Noh is surrounded by the bottom channel layer 70 (Fig. 35) at a lower cross section shown in Fig. 35 below, which corresponds to the first cross section perpendicular to the first direction in the claimed invention, and containing silicon (Si) and oxygen (O), because “the third gate dielectric layer 63 may include a silicon oxide” ([0084]) or “the first gate dielectric material layer 61a may include a silicon oxide (SiO2)” ([0142]);
a third insulating layer (first gate dielectric layer 61 or third gate dielectric layer 63, Fig. 35) surrounded by the second insulating layer (63 or 61, Fig. 35) in the first cross section (lower cross section, attached Fig. 35 below) and containing a metal element and oxygen (O), because “the first gate dielectric layer 61 may include a metal oxide” ([0084]) or “the third gate dielectric material layer 63a may include a metal oxide such as an aluminum oxide (Al2O3)” ([0142]); and
a conductive layer (gate electrode 50, Fig. 35) surrounded by the first insulating layer (composite layer of 30/32, Fig. 35) in a second cross section perpendicular to the first direction (upper cross section, see Fig. 35 below), the conductive layer (50, Fig. 35) provided in the first direction of the third insulating layer (vertical direction of 61 or 63, Fig. 35), because the first gate dielectric layer 61 by Noh has “U” shape and the gate electrode 50 is disposed above a lower-flat portion of the first gate dielectric layer 61 or the third gate dielectric layer 63 in a vertical direction, which corresponds to the first direction in the claimed invention, and the semiconductor layer (bottom 70, Fig. 35 below), because as shown in the attached Fig. 35 below, the gate electrode 50 by Noh, which corresponds to the conductive layer in the claimed invention, is provided along the vertical direction of the bottom channel layer 70 and it is provided over the bottom channel layer 70 (Fig. 35 below), and Examiner notes that Applicants do not specifically claim what a vertical orientation or alignment (i.e., geometrical configuration) of the conductive layer and the semiconductor has,
the conductive layer (50, Fig. 35) spaced from the semiconductor layer (bottom 70, Fig. 35). Examiner notes that Applicants do not specifically claim an entirety of the conductive layer is provided in the first direction of the third insulating layer.
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Noh does not explicitly disclose that the conductive layer including a first portion, a second portion, and a third portion in a cross section including the third insulating layer and parallel to the first direction, the first portion being in contact with the second insulating layer, the second portion being in contact with the second insulating layer, the third portion being in contact with the third insulating layer, and the third portion is provided between the first portion and the second portion.
However, Tsuji discloses for a NAND-type non-volatile memory device that Fig. 1 of Tsuji shows a cross-sectional view of the memory device 1 (Fig. 1) including the conductive body 60, which corresponds to the conductive layer in the claimed invention, the insulation film 23 (labeled in Fig. 5) and the core 140 (labeled in Fig. 8) disposed below the conductive body 60, corresponding to the second insulating layer and the third insulating layer in the claimed invention, respectively, because Tsuji further discloses “the core 140 is, for example, a silicon oxide film” (emphasis added, [0047]), therefore, the core 140 is an insulating layer; the Merriam-Webster dictionary defines a word “portion” and “an often limited part of a whole”, therefore, the conductive body 60 by Tsuji includes multiple portions and different portions can be selected for the first, second and third portions of the conductive body 60, as shown in the attached and annotated Fig. 1 of Tsuji below; in this case, the first and second portions of the conductive body 60 are in contact with the insulation film 23 (the claimed second insulating layer), while the third portion of the conductive body 60 is in contact with the core 140 (the claimed third insulating layer) and is disposed between the first and second portions in the claimed cross-sectional view (Fig. 1).
Since both Noh and Tsuji teach a 3D vertical memory device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive structure of Noh to include the arrangement of conductive portions in contact with multiple insulating layers, as disclosed by Tsuji, as an alternative configuration of the conductive structure in the vertical semiconductor memory device, in order to improve the electrical insulation and overall performance of the memory device.
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Regarding claim 3, Noh further discloses for the semiconductor device according to claim 1 that the first insulating layer (composite layer 30/32, Fig. 35) is in contact with the semiconductor layer (70, Fig. 35).
Regarding claim 4, Noh further discloses for the semiconductor device according to claim 1 that the third insulating layer (61, Fig. 35) is spaced from the semiconductor layer (70, Fig. 35).
Regarding claim 5, Noh further discloses for the semiconductor device according to claim 1 that a dielectric constant of the third insulating layer (61, Fig. 35) is higher than a dielectric constant of the second insulating layer (63, Fig. 35), because “the first gate dielectric material layer 61a may include a metal oxide such as an aluminum oxide (Al2O3)… and the third gate dielectric material layer 63a may include a silicon oxide (SiO2)” ([0142]); the dielectric constant of aluminum oxide generally ranges from 8 to 10 at room temperature and the dielectric constant of silicon oxide is approximately 3.9 (Examiner’s Googling results), therefore, a dielectric constant of the first gate dielectric layer 61 is higher than a dielectric constant of the third gate dielectric layer 63, which correspond to the third insulating layer and the first insulating layer in the claimed invention.
Regarding claim 7, Noh further discloses for the semiconductor device according to claim 1 that the metal element is at least one metal element selected from a group consisting of aluminum (Al),hafnium (Hf), zirconium (Zr), lanthanum (La), yttrium (Y), titanium (Ti), nickel (Ni), zinc (Zn), indium (In),tin(Sn), gallium (Ga), and tungsten (W), because “the first gate dielectric layer 61 may include a metal oxide” ([0084]) and “the first gate dielectric material layer 61a may include a metal oxide such as an aluminum oxide (Al2O3)…” (emphasis added, [0142]).
Regarding claim 9, Noh further discloses for a semiconductor memory device comprising that
a first semiconductor layer containing silicon (Si) (lowest channel layer 70, Fig. 35), because the channel layer 70 by Noh includes “an intrinsic semiconductor layer such as an undoped polysilicon or a P-doped polysilicon layer doped with P-type ions” ([0087]);
a first insulating layer (a composite insulating layer of the interlayer dielectric layer 30 and the uppermost interlayer dielectric layer 32, Fig. 35) provided in a first direction of the first semiconductor layer (vertical direction, Fig. 35), because the interlayer dielectric layer 30 and the uppermost interlayer dielectric layer 32 by Noh are disposed above the channel layer 70 (Fig. 35), i.e., along the vertical direction in the claimed invention;
a second insulating layer (third gate dielectric layer 63 or first gate dielectric layer 61, Fig. 35) surrounded by the first semiconductor layer (lowest 70, Fig. 35) in a first cross section perpendicular to the first direction (lower cross section, see attached Fig. 35 above), because a lateral portion of the third gate dielectric layer 63 or the first gate dielectric layer 61 by Noh is surrounded by the channel layer 70 (Fig. 35) at a lower cross section shown in Fig. 35 below, which corresponds to the first cross section perpendicular to the first direction in the claimed invention, and containing silicon (Si) and oxygen (O), because “the third gate dielectric layer 63 may include a silicon oxide” ([0084]) or “the first gate dielectric material layer 61a may include a silicon oxide (SiO2)” ([0142]);
a third insulating layer (first gate dielectric layer 61 or third gate dielectric layer 63, Fig. 35) surrounded by the second insulating layer in the first cross section (lower cross section, see attached Fig. 35 above) and containing a metal element and oxygen (O), because “the first gate dielectric layer 61 may include a metal oxide” ([0084]) “the third gate dielectric material layer 63a may include a metal oxide such as an aluminum oxide (Al2O3)” ([0142]);
a conductive layer (gate electrode 50, Fig. 35) extending in the first direction (vertical direction, Fig. 35), the conductive layer (50, Fig. 35) surrounded by the first insulating layer (composite layer of 30/32, Fig. 35) in a second cross section perpendicular to the first direction (upper cross section, see attached Fig. 35 above), the conductive layer provided in the first direction of the third insulating layer (vertical direction of 61 or 63, Fig. 35), because the first gate dielectric layer 61 by Noh has “U” shape and the gate electrode 50 is disposed above a lower-flat portion of the first dielectric layer 61 or the third gate dielectric layer 63 in a vertical direction, which corresponds to the first direction in the claimed invention, and the first semiconductor layer (lowest 70, Fig. 35), because as shown in the attached Fig. 35 above, the gate electrode 50 by Noh, which corresponds to the conductive layer in the claimed invention, is provided along the vertical direction of the lowest channel layer 70 and it is provided over the lowest channel layer 70 (Fig. 35 above), and Examiner notes that Applicants do not specifically claim what a vertical orientation or alignment (i.e., geometrical configuration) of the conductive layer and the semiconductor has,
and the conductive layer (50, Fig. 35) spaced from the first semiconductor layer (lowest 70, Fig. 35);
a first gate electrode layer (gate contact plug GC and gate line GL, Fig. 35) provided in the first direction of the first semiconductor layer (vertical direction, i.e., above the lowest channel layer 70, Fig. 35), because the gate contact plug GC and the gate line GL by Noh include “at least one among an N-doped polysilicon, a metal silicide such as a titanium silicide (TiSi) or a tungsten silicide (WSi), a metal such as tungsten (W), a metal compound such as a titanium nitride (TiN) or a tantalum nitride (TaN) and a metal alloy” ([0149]), therefore, both the gate contact plug and the gate line can be made of the same material listed in [0149] of Noh, and therefore, GC and GL can be a single body or element,
and in a second direction (lateral direction, Fig. 35) perpendicular to the first direction of the conductive layer (50, Fig. 35), because the gate line GL is provided laterally or in lateral direction above the gate electrode 50 (Fig. 35), and electrically connected to the conductive layer (50, Fig. 35);
a second semiconductor layer (second lowest channel layer 70, Fig. 35) extending in the first direction (vertical direction, Fig. 35); and
a charge storage layer (charge trap gate dielectric layer 62, Fig. 35) provided between the first gate electrode layer (GC/GL, Fig. 35) and the second semiconductor layer (second lowest 70, Fig. 35), because the gate contact plug GC and the second lowest channel layer 70 is positioned diagonally between each other (Fig. 35).
Noh does not explicitly disclose that the conductive layer including a first portion, a second portion, and a third portion in a cross section including the third insulating layer and parallel to the first direction, the first portion being in contact with the second insulating layer, the second portion being in contact with the second insulating layer, the third portion being in contact with the third insulating layer, and the third portion is provided between the first portion and the second portion.
However, Tsuji discloses for a NAND-type non-volatile memory device that Fig. 1 of Tsuji shows a cross-sectional view of the memory device 1 (Fig. 1) including the conductive body 60, which corresponds to the conductive layer in the claimed invention, the insulation film 23 (labeled in Fig. 5) and the core 140 (labeled in Fig. 8) disposed below the conductive body 60, corresponding to the second insulating layer and the third insulating layer in the claimed invention, respectively, because Tsuji further discloses “the core 140 is, for example, a silicon oxide film” (emphasis added, [0047]), therefore, the core 140 is an insulating layer; the Merriam-Webster dictionary defines a word “portion” and “an often limited part of a whole”, therefore, the conductive body 60 by Tsuji includes multiple portions and different portions can be selected for the first, second and third portions of the conductive body 60, as shown in the attached and annotated Fig. 1 of Tsuji above; in this case, the first and second portion of the conductive body 60 is in contact with the insulation film 23 (the claimed second insulating layer), while the third portion of the conductive body 60 is in contact with the core 140 (the claimed third insulating layer) and is disposed between the first and second portions in the claimed cross-sectional view (Fig. 1).
Since both Noh and Tsuji teach a 3D vertical memory device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive structure of Noh to include the arrangement of conductive portions in contact with multiple insulating layers, as disclosed by Tsuji, as an alternative configuration of the conductive structure in the vertical semiconductor memory device, in order to improve the electrical insulation and overall performance of the memory device.
Regarding claim 10, Noh further discloses for the semiconductor memory device according to claim 9 that the conductive layer (50, Fig. 35) is in contact with the first gate electrode layer (GC/GL, Fig. 35).
Regarding claim 15, Noh further discloses for the semiconductor memory device according to claim 9 that the first insulating layer (composite layer 30/32, Fig. 35) is in contact with the first semiconductor layer (lowest 70, Fig. 35).
Regarding claim 16, Noh further discloses for the semiconductor memory device according to claim 9 that the third insulating layer (61, Fig. 35) is spaced from the first semiconductor layer (lowest 70, Fig. 35).
Regarding claim 17, Noh further discloses for the semiconductor memory device according to claim 9 that a dielectric constant of the third insulating layer is higher than a dielectric constant of the second insulating layer, because “the first gate dielectric material layer 61a may include a metal oxide such as an aluminum oxide (Al2O3)… and the third gate dielectric material layer 63a may include a silicon oxide (SiO2)” ([0142]); the dielectric constant of aluminum oxide generally ranges from 8 to 10 at room temperature and the dielectric constant of silicon oxide is approximately 3.9 (Examiner’s Googling results), therefore, a dielectric constant of the first gate dielectric layer 61 is higher than a dielectric constant of the third gate dielectric layer 63, which correspond to the third insulating layer and the first insulating layer in the claimed invention.
Regarding claim 18, Noh further discloses for the semiconductor memory device according to claim 9 that the conductive layer (50, Fig. 35) is in contact with the second insulating layer (61, Fig. 35).
Regarding claim 20, Noh further discloses for the semiconductor memory device according to claim 9 that the metal element is at least one metal element selected from a group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), yttrium (Y), titanium (Ti), nickel (Ni), zinc (Zn), indium (In),tin(Sn), gallium (Ga), and tungsten (W), because “the first gate dielectric layer 61 may include a metal oxide” ([0084]) and “the first gate dielectric material layer 61a may include a metal oxide such as an aluminum oxide (Al2O3)…” (emphasis added, [0142]).
Allowable Subject Matter
Claims 24-26 are allowed, because the prior arts cited in this Office Action do not teach the claim limitation, “a second gate electrode layer provided in the first direction of the first semiconductor layer, the second gate electrode provided in the first direction of the first gate electrode layer, and the second gate electrode electrically separated from the conductive layer”, recited on lines 18-20 of claim 24, and claims 25-26 depend on claim 24.
Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815
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