DETAILED ACTION
This office action is in response to the arguments filed on October 27, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
Applicant’s arguments filed on October 27, 2025, in response to the office action mailed on 7/25/2025 is acknowledged. The present office action is made with all the suggested amendments being fully considered. Accordingly, pending in this office action are claims 1-3, 5-10 and 17-22. Claims 4 and 11-16 are canceled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/13/2022 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2012/0306080) in view of Schneegans (US 2016/0379947).
With respect to Claim 1, Yu shows (Fig. 2) most aspects of the current invention including a semiconductor device comprising:
a semiconductor die (200) including a via (118) (par 16)
a metal layer (241) in direct contact with the via (118)
a pillar including a top portion (234) and a bottom portion (232), the top portion including copper and the bottom portion in contact with the metal layer
Yu does not disclose wherein the metal layer in direct contact with the via is a layer of titanium tungsten (TiW), the bottom portion including zinc and copper and the bottom portion in contact with the layer of TiW.
On the other hand, and in the same field of endeavor, Schneegans teaches (Fig. 2E) a semiconductor device comprising a pillar including a top portion (350) and a bottom portion (325), the top portion including copper and the bottom portion including zinc and copper, the bottom portion in contact with the layer of TiW, (par 47-48 and 72; layer 325 contains, as main constituent or as minor constituent with a mass fraction of at least 80 wt % a second metal which is not the first metal, and may contain further constituents, e.g., the first metal and/or at least one further metal selected from aluminum (Al), gold (Au), silver (Ag), tin (Sn), zinc (Zn), lead (Pb) and nickel (Ni)) and further wherein the bottom portion of the pillar is in contact with the layer of TiW (321) (par 46). Schneegans teaches providing an adhesion layer that may reduce thermo-mechanical stress between the pillar and layer of TiW.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the metal layer in direct contact with the via is a layer of titanium tungsten (TiW), the bottom portion including zinc and copper and the bottom portion in contact with the layer of TiW in the device of Yu, as suggested by Schneegans because providing an adhesion layer that may reduce thermo-mechanical stress between the pillar and layer of TiW.
With respect to Claim 2, Yu shows (Fig. 2) wherein the metal layer (241) contacts portions of the semiconductor die. Also, see comments stated above in Par. 7-9 with regards to Claim 1, which are considered repeated here.
With respect to Claim 3, Yu shows (Fig. 2) wherein the via includes copper.
With respect to Claim 6, Schneegans teaches (Fig. 2E) wherein the top portion of the pillar does not include zinc (par 42)
With respect to Claim 17, Yu shows (Fig. 2) wherein the top portion includes pure copper. Further, Schneegans teaches (Fig. 2E) wherein the top portion includes pure copper.
With respect to Claim 18, regarding the language in Claim 18 referring to the process step of wherein zinc is inter-diffused with copper in the bottom portion, it has been held by the courts that the patentability of a product does not depend on its method of production. “If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
In the instant case, Schneegans shows the copper pillar including a top portion (350) and a bottom portion (325), the top portion including copper and the bottom portion including zinc and copper. Therefore, since the final structure for the pillar, as taught in the prior art, is substantially identical to the analogous structure being claimed, a prima facie case of obviousness has been established.
With respect to Claim 19, Yu shows (Fig. 2-3) further including a substrate (110) coupled to the pillar.
With respect to Claim 20, Yu shows (Fig. 2-3) wherein the substrate and the pillar are coupled via a solder material (138).
Claims 5, 7-10 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Schneegans and in further view of Ho (US 2018/0130759).
With respect to Claim 5, Yu in view of Schneegans show most aspects of the current invention. However, the combination of references does not show further including mold compound in contact with the semiconductor die, the layer of TiW, and the pillar.
On the other hand, and in the same field of endeavor, Ho teaches (see in particular Fig 1-2) a semiconductor device comprising a semiconductor die (3), a conductive pillar (32) and a conductive connector (34) and further including mold compound (4) in contact with the semiconductor die, conductive pillar and conductive connector (par 28-29). Ho teaches doing so to allow the mold compound to extend to a space between the semiconductor die and the semiconductor substrate structure so as to protect the conductive posts, pillars and connectors (par 29).
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have a mold compound in contact with the semiconductor die, the layer of TiW, and the pillar in the device of Yu in view of Schneegans, as taught by Ho, to allow the mold compound to extend to a space between the semiconductor die and the semiconductor substrate structure so as to protect the conductive posts, pillars and connectors.
With respect to Claim 7, Yu shows (Fig. 2-3) most aspects of the current invention including a packaged semiconductor device comprising:
a semiconductor die (200) including a via (118) (par 16)
a metal layer (241) in direct contact with the via (118)
a pillar including a top portion (234) and a bottom portion (232), the top portion including copper and the bottom portion in contact with the metal layer
a substrate (110) coupled to the pillar
Yu does not disclose wherein the metal layer in direct contact with the via is a layer of titanium tungsten (TiW), the bottom portion including zinc and copper and the bottom portion in contact with the layer of TiW, a mold compound covering portions of the semiconductor die, the pillar, the layer of TiW, and the substrate.
On the other hand, and in the same field of endeavor, Schneegans teaches (Fig. 2E) a semiconductor device comprising a pillar including a top portion (350) and a bottom portion (325), the top portion including copper and the bottom portion including zinc and copper, the bottom portion in contact with the layer of TiW, (par 47-48 and 72; layer 325 contains, as main constituent or as minor constituent with a mass fraction of at least 80 wt % a second metal which is not the first metal, and may contain further constituents, e.g., the first metal and/or at least one further metal selected from aluminum (Al), gold (Au), silver (Ag), tin (Sn), zinc (Zn), lead (Pb) and nickel (Ni)) and further wherein the bottom portion of the pillar is in contact with the layer of TiW (321) (par 46). Schneegans teaches providing an adhesion layer that may reduce thermo-mechanical stress between the pillar and layer of TiW.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the metal layer in direct contact with the via is a layer of titanium tungsten (TiW), the bottom portion including zinc and copper and the bottom portion in contact with the layer of TiW in the device of Yu, as suggested by Schneegans because providing an adhesion layer that may reduce thermo-mechanical stress between the pillar and layer of TiW.
However, the combination of references do not show mold compound covering portions of the semiconductor die, the pillar, the layer of TiW, and the substrate.
On the other hand, and in the same field of endeavor, Ho teaches (see in particular Fig 1-2) a semiconductor device comprising a semiconductor die (3), a conductive pillar (32), a conductive connector (34) and a substrate (2) coupled to the conductive pillar and further including mold compound (4) in contact with the semiconductor die, conductive pillar and conductive connector (par 28-29). Ho teaches doing so to allow the mold compound to extend to a space between the semiconductor die and the semiconductor substrate structure so as to protect the conductive posts, pillars and connectors (par 29).
Therefore, it would have been obvious at the time the invention to one having ordinary skill in the art, or before the effective filing date of the invention to have a substrate coupled to the copper pillar and a mold compound in contact with the semiconductor die, the layer of TiW, and the copper pillar in the device of Yu and Schneegans, as taught by Ho, to allow the mold compound to extend to a space between the semiconductor die and the semiconductor substrate structure so as to protect the conductive posts, pillars and connectors.
With respect to Claim 8, Yu shows (Fig. 2) wherein the metal layer (241) contacts portions of the semiconductor die. Also, see comments stated above in Par. 21-23 with regards to Claim 7, which are considered repeated here.
With respect to Claim 9, Yu shows (Fig. 2) wherein the via includes copper.
With respect to Claim 10, regarding the language in Claim 10 referring to the process step of wherein zinc is inter-diffused with copper in the bottom portion, it has been held by the courts that the patentability of a product does not depend on its method of production. “If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
In the instant case, Schneegans shows the copper pillar including a top portion (350) and a bottom portion (325), the top portion including copper and the bottom portion including zinc and copper. Therefore, since the final structure for the pillar, as taught in the prior art, is substantially identical to the analogous structure being claimed, a prima facie case of obviousness has been established.
With respect to Claim 21, Schneegans teaches (Fig. 2E) wherein the top portion of the pillar does not include zinc (par 42)
With respect to Claim 22, Yu shows (Fig. 2) wherein the top portion includes pure copper. Further, Schneegans teaches (Fig. 2E) wherein the top portion includes pure copper.
Response to Arguments
Applicant’s arguments, filed 10/27/2025, with respect to the rejection(s) of claims 1-3, 5-10 and 17-22 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the references provided above.
Conclusion
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/Q.A.B/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814