DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 17, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 26, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. Claim 1 recites the limitation “wherein an upper surface of the insulating division layer is higher than an upper surface of the dielectric layer” in the last paragraph of the claim language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-9, 24, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Koo (U.S. 2013/0127012), and further in view of Park et al (U.S. 2008/0160712).
Regarding claim 1. Koo discloses a semiconductor device (FIG. 7) comprising:
a first contact plug (FIG. 7, item 155) on a substrate (FIG. 7, item 100);
a capacitor ([Abstract]) including:
a first electrode (FIG. 7, item 185) contacting an upper surface of the first contact plug (FIG. 7, item 155), the first electrode (FIG. 7, item 185) extending in a vertical direction substantially perpendicular (FIG. 7 shows item 185 extending in a vertical direction substantially perpendicular to item 100) to an upper surface of the substrate (FIG. 7, item 100);
a second electrode (FIG. 7, item 162) spaced apart from the first electrode (FIG. 7, item 185), the second electrode (FIG. 7, item 162) extending in the vertical direction and including lower and upper surfaces ([0053]-[0054]) substantially coplanar ([0053]-[0054]) with lower and upper surfaces ([0053]-[0054]), respectively, of the first electrode (FIG. 7, item 185);
a dielectric layer (FIG. 7, item 172) on sidewalls of the first (FIG. 7, item 185) and second electrodes (FIG. 7, item 162);
an insulating division layer (FIG. 7, item 174) between portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second electrodes (FIG. 7, item 162); and
a second contact plug (FIG. 7, item 164) contacting the upper surface of the second electrode (FIG. 7, item 162), and
wherein an upper surface (FIG. 7, upper surface of item 174) of the insulating division layer (FIG. 7, item 174) is higher (FIG. 7, shows an upper surface of item 174 is higher than an upper surface of item 172) than an upper surface (FIG. 7, upper surface of item 172) of the dielectric layer (FIG. 7, item 172).
Koo fails to explicitly disclose wherein the first electrode is separated from the second electrode by a first portion of the dielectric layer on a first sidewall of the first electrode, a second portion of the dielectric layer on a second sidewall of the second electrode, and a portion of the insulating division layer between the first portion and the second portion of the dielectric layer.
However, Park et al teaches wherein the first electrode (FIG. 6D, item 27) is separated from the second electrode (FIG. 6D, item 28) by a first portion (FIG. 6D, item 101) of the dielectric layer (FIG. 6D, item 100) on a first sidewall (FIG. 6D, item 27) of the first electrode (FIG. 6D, item 27), a second portion (FIG. 6D, item 103) of the dielectric layer (FIG. 6D, item 100) on a second sidewall (FIG. 6D, item 28) of the second electrode (FIG. 6D, item 28), and a portion (FIG. 6D, item 102) of the insulating division layer (FIG. 6D, item 102) between ([0020]) the first portion (FIG. 6D, item 101) and the second portion (FIG. 6D, item 103) of the dielectric layer (FIG. 6D, item 100)
Since Koo and Park et al teach Capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo with the teachings of wherein the first electrode is separated from the second electrode by a first portion of the dielectric layer on a first sidewall of the first electrode, a second portion of the dielectric layer on a second sidewall of the second electrode, and a portion of the insulating division layer between the first portion and the second portion of the dielectric layer as disclosed by Park et al. The use of a first dielectric layer; a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a dielectric constant lower than that of the first dielectric layer; and a third dielectric layer formed over the second dielectric layer, the third dielectric layer having a dielectric constant higher that of than the second dielectric layer in Park et al provides for reducing leakage current and secure a high dielectric constant (Park et al, [0009]).
Regarding claim 5. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses wherein an upper surface of the dielectric layer (FIG. 7, item 172) is substantially coplanar ([0053]-[0054]) with the upper surfaces ([0053]-[0054]) of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes.
Regarding claim 6. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 5 above.
Koo further discloses wherein the insulating division layer (FIG. 7, item 174) and the dielectric layer (FIG. 7, item 172) comprise different respective materials ([0060], i.e. the second dielectric layer 174 may be formed of a different material from the first dielectric layer patterns 172), and wherein the portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes are spaced apart (FIG. 7, items 72 are spaced apart by item 174) from each other by the insulating division layer (FIG. 7, item 174).
Regarding claim 7. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 6 above.
Koo further discloses wherein a lower surface (FIG. 7, lower surface of item 174) of the insulating division layer (FIG. 7, item 174) is substantially coplanar (FIG. 7, the lower surface of item 174 is substantially coplanar with the lower surfaces of items 185 and 162) with the lower surfaces (FIG. 7, lower surfaces of items 185 and 162) of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes.
Regarding claim 8. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 5 above.
Koo further discloses wherein the insulating division layer (FIG. 7, item 174) is on the upper surface of the first electrode (FIG. 7, item 185), and wherein the second contact plug (FIG. 7, item 164) extends through the insulating division layer (FIG. 7, item 174).
Regarding claim 9. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses further comprising an insulating interlayer (FIG. 7, item 150) that is on the substrate (FIG. 7, item 100) and a sidewall of the first contact plug (FIG. 7, item 155), wherein the portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes are each thinner (FIG. 7 shows item 172 is thinner than item 155), in a horizontal direction perpendicular to the vertical direction, than each of the first contact plug (FIG. 7, item 155), the first electrode (FIG. 7, item 185), and the second electrode (FIG. 7, item 162).
Regarding claim 24. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses wherein the insulating division layer (FIG. 7, item 174) is on upper surfaces ([0062]-[-0063]) of the first electrodes (FIG. 7, item 185), and wherein the second contact plugs (FIG. 7, item 164) extend through ([0062]-[-0063]) the insulating division layer (FIG. 7, item 174).
Regarding claim 31. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Park et al further discloses wherein the first sidewall (FIG. 6D, item 27) of the first electrode (FIG. 6D, item 27) is adjacent (FIG. 6D, item 100) to the second sidewall (FIG. 6D, item 28) of the second electrode (FIG. 6D, item 28).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Koo (U.S. 2013/0127012) and Park et al (U.S. 2008/0160712) as applied to claim 1 above, and further in view of Kim et al (U.S. 2018/0096935).
Regarding claim 10. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses the capacitor ([Abstract]).
Koo and Park et al fails to explicitly disclose further comprising an insulating interlayer on the capacitor, wherein the second contact plug extends through the insulating interlayer.
However, Kim et al teaches further comprising an insulating interlayer (FIG. 5, item 305), wherein the second contact plug (FIG. 5, item 392) extends through the insulating interlayer (FIG. 5, item 305; [0052], i.e. insulation reinforcing layer 305 may be formed on the first insulating interlayer 300 through which the first contact plugs 332 are formed).
Since Koo, Park et al and Kim et al teach contact plug, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo and Park et al with the teachings of further comprising an insulating interlayer, wherein the second contact plug extends through the insulating interlayer as disclosed by Kim et al. The use of insulation reinforcing layer may be formed on the first insulating interlayer through which the first contact plugs are formed in Kim et al provides for the electrical insulation between the first and third contact plugs may be enhanced (Kim et al, [0052]).
Claims 18, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Koo (U.S. 2013/0127012), and Cho et al (U.S. 2015/0357399).
Regarding claim 18. Koo discloses a semiconductor device (FIG. 7) comprising:
first contact plugs (FIG. 7, item 155) on a substrate (FIG. 7, item 100), the first contact plugs (FIG. 7, item 155) being spaced apart from each (FIG. 7 shows items 155 are spaced apart from each other) other in a horizontal direction ([0062]-[-0063]) substantially parallel to an upper surface of the substrate (FIG. 7, item 100);
first electrodes (FIG. 7, item 185) contacting the first contact plugs (FIG. 7, item 155), respectively, each of the first electrodes (FIG. 7, item 185) having a shape ([0054], i.e. a cylinder shape with a closed bottom. In addition, horizontal sectional views of the lower electrodes 185 (i.e., sectional views taken in planes that are parallel to the top surface of the substrate 100) may each have various shapes such as a circular shape, an oval shape, and a polygonal shape) extending in a vertical direction ([0062]-[-0063]) substantially perpendicular (FIG. 7, item 185 extends in a vertical direction substantially perpendicular to upper surface of item 100) to the upper surface of the substrate (FIG. 7, item 100);
second electrodes (FIG. 7, item 162) spaced apart from the first electrodes (FIG. 7, item 185) in the horizontal direction ([0062]-[-0063]), each of the second electrodes (FIG. 7, item 162) extending in the vertical direction ([0062]-[-0063]);
a dielectric layer (FIG. 7, item 172) on sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes;
an insulating division layer (FIG. 7, item 174) between portions (FIG. 7, item 172) of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes; and
second contact plugs (FIG. 7, item 164) contacting upper surfaces of the second electrodes (FIG. 7, item 162), respectively, wherein the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes repeatedly alternate ([0062]-[-0063]) with each other in the horizontal direction (FIG. 7, shows item 162 and 185 alternate with each in a horizontal direction).
Koo fails to explicitly disclose with the first electrode has a pillar shape, first electrodes being separated from the second electrodes in the horizontal direction by first portions of the dielectric layer that are on first sidewalls of the first electrodes, second portions of the dielectric layer that are on second sidewalls of the second electrodes, and portions of the insulating division layer that are between the first portions and the second portions of the dielectric layer.
However, Cho et al teaches with the first electrode (FIG. 1, item 123; [0038]) has a pillar shape ([0042], i.e. lower electrode 123 may have a pillar shape), the first electrodes (FIG. 1, item 123) being separated (FIG. 1, item 126) from the second electrodes (FIG. 1, item 129) in the horizontal direction by first portions (FIG. 1, item 126a) of the dielectric layer (FIG. 1, item 126a) that are on first sidewalls (FIG. 1, item 123) of the first electrodes (FIG. 1, item 123), second portions (FIG. 1, item 126c) of the dielectric layer (FIG. 1, item 126c) that are on second sidewalls (FIG. 1, item 129) of the second electrodes (FIG. 1, item 129), and portions (FIG. 1, item 126b) of the insulating division layer (FIG. 1, item 126b) that are between ([0051]) the first portions (FIG. 1, item 126a) and the second portions (FIG. 1, item 126c) of the dielectric layer (FIG. 1, item 126).
Since Koo and Cho et al teach Capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo with the teachings of the first electrode has a pillar shape, with the first electrodes being separated from the second electrodes in the horizontal direction by first portions of the dielectric layer that are on first sidewalls of the first electrodes, second portions of the dielectric layer that are on second sidewalls of the second electrodes, and portions of the insulating division layer that are between the first portions and the second portions of the dielectric layer as disclosed by Cho et al. The use of a capacitor may include a lower electrode electrically connected to a plug that extends through an insulating interlayer to a substrate. The capacitor may further include a dielectric layer structure and an upper electrode sequentially stacked on the lower electrode 123 and the insulating interlayer in Cho et al provides for the capacitor including the dielectric layers may have a reduced leakage current and have a high capacitance (Cho et al, [0022]).
Regarding claim 22. Koo and Cho et al discloses all the limitations of the semiconductor device according to claim 18 above.
Koo further discloses wherein an upper surface ([0053]-[0054]) of the dielectric layer (FIG. 7, item 172) is substantially coplanar ([0053]-[0054]) with upper surfaces ([0053]-[0054]) of the first electrodes (FIG. 7, item 185) and with the upper surfaces ([0053]-[0054]) of the second (FIG. 7, item 162) electrodes.
Regarding claim 23. Koo and Cho et al discloses all the limitations of the semiconductor device according to claim 22 above.
Koo further discloses wherein the portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second electrodes (FIG. 7, item 162) are spaced apart ([0062]-[-0063]) from each other (FIG. 7, items 72 are spaced apart by item 174) by the insulating division layer (FIG. 7, item 177).
Response to Arguments
Applicant's arguments filed March 17, 2026 have been fully considered but they are not persuasive.
On page 9, applicant appears to argue against the methods of Koo and Park does not disclose applicant’s amended claim 1.
Examiner respectfully points out that applicant’s claims are directed to the device, and not the method of manufacturing the device. Examiner respectfully points out that Koo and Park et al discloses applicant’s amended claim 1 of the device. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 10, applicant appears to further argue, that Koo FIG. 3-5 manufacturing method fails to disclose applicant’s claimed device.
Examiner respectfully points out that Koo FIG. 7 was used to reject applicant’s device.
On page 10, applicant appears to be arguing that Park et al method fails to disclose applicant’s claimed device because Park et al upper electrode runs above the lower electrode.
Examiner respectfully points out that Koo discloses the first and second electrodes with a insulators in between. Park et al was used to disclose a three layered insulator. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant’s arguments with respect to claim(s) 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner respectfully points out, Koo and Cho et al discloses applicant’s amended claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (U.S. 6,936,880) discloses Capacitor Of Semiconductor Memory Device And Method Of Manufacturing The Same.
Lin (U.S. 9,887,258) discloses method for fabricating capacitor
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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