DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-9, 24, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Koo (U.S. 2013/0127012), and further in view of Park et al (U.S. 2008/0160712).
Regarding claim 1. Koo discloses a semiconductor device (FIG. 6) comprising:
a first contact plug (FIG. 7, item 155) on a substrate (FIG. 7, item 100);
a capacitor ([Abstract]) including:
a first electrode (FIG. 7, item 185) contacting an upper surface of the first contact plug (FIG. 7, item 155), the first electrode (FIG. 7, item 185) extending in a vertical direction substantially perpendicular (FIG. 7 shows item 185 extending in a vertical direction substantially perpendicular to item 100) to an upper surface of the substrate (FIG. 7, item 100);
a second electrode (FIG. 7, item 162) spaced apart from the first electrode (FIG. 7, item 185), the second electrode (FIG. 7, item 162) extending in the vertical direction and including lower and upper surfaces ([0053]-[0054]) substantially coplanar ([0053]-[0054]) with lower and upper surfaces ([0053]-[0054]), respectively, of the first electrode (FIG. 7, item 185);
a dielectric layer (FIG. 7, item 172) on sidewalls of the first (FIG. 7, item 185) and second electrodes (FIG. 7, item 162);
an insulating division layer (FIG. 7, item 174) between portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second electrodes (FIG. 7, item 162); and
a second contact plug (FIG. 7, item 164) contacting the upper surface of the second electrode (FIG. 7, item 162), and
a first portion (FIG. 7, portion of item 174 that is between items 162 and 185) of the insulating layer (FIG. 7, item 174),
wherein an uppermost surface (FIG. 7, upper surface of item 174) of a second portion (FIG. 7, portion of item 174 that is above item 172) the insulating division layer (FIG. 7, item 174) is higher (FIG. 7, shows an upper surface of item 174 is higher than an uppermost surface of item 172) than an uppermost surface (FIG. 7, upper surface of item 172) of the dielectric layer (FIG. 7, item 172).
wherein the first electrode (FIG. 7, item 185) is separated (FIG. 7, item 172) from the second electrode (FIG. 7, item 164) by the dielectric layer (FIG. 7, item 172),
wherein the first portion (FIG. 7, portion of item 174 that is between items 162 and 185) of the insulating division layer (FIG. 7, item 174) is continuous ([0059]-[0062]) with the second portion (FIG. 7, portion of item 174 that is above item 172) of the insulation division layer (FIG. 7, item 174)
Koo fails to explicitly disclose wherein the first electrode is separated from the second electrode by a first portion of the dielectric layer on a first sidewall of the first electrode, a second portion of the dielectric layer on a second sidewall of the second electrode, and a first portion of the insulating division layer between the first portion of the dielectric layer on the first sidewall of the first electrode and the second portion of the dielectric layer on the second sidewall of the second electrode.
However, Park et al teaches wherein the first electrode (FIG. 6D, item 27) is separated from the second electrode (FIG. 6D, item 28) by a first portion (FIG. 6D, item 101) of the dielectric layer (FIG. 6D, item 100) on a first sidewall (FIG. 6D, item 27) of the first electrode (FIG. 6D, item 27), a second portion (FIG. 6D, item 103) of the dielectric layer (FIG. 6D, item 100) on a second sidewall (FIG. 6D, item 28) of the second electrode (FIG. 6D, item 28), and a first portion (FIG. 6D, item 102) of the insulating division layer (FIG. 6D, item 102) between ([0020]) the first portion (FIG. 6D, item 101) of the dielectric layer (FIG. 6D, item 100) on the first sidewall (FIG. 6D, item 27) of the first electrode (FIG. 6D, item 27) and the second portion (FIG. 6D, item 103) of the dielectric layer (FIG. 6D, item 100) on the second sidewall (FIG. 6D, item 28) of the second electrode (FIG. 6D, item 28).
Since Koo and Park et al teach capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo with the teachings of wherein the first electrode is separated from the second electrode by a first portion of the dielectric layer on a first sidewall of the first electrode, a second portion of the dielectric layer on a second sidewall of the second electrode, and a first portion of the insulating division layer between the first portion of the dielectric layer on the first sidewall of the first electrode and the second portion of the dielectric layer on the second sidewall of the second electrode as disclosed by Park et al. The use of a first dielectric layer; a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a dielectric constant lower than that of the first dielectric layer; and a third dielectric layer formed over the second dielectric layer, the third dielectric layer having a dielectric constant higher that of than the second dielectric layer in Park et al provides for reducing leakage current and secure a high dielectric constant (Park et al, [0009]).
Regarding claim 5. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses wherein an upper surface of the dielectric layer (FIG. 7, item 172) is substantially coplanar ([0053]-[0054]) with the upper surfaces ([0053]-[0054]) of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes.
Regarding claim 6. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 5 above.
Koo further discloses wherein the insulating division layer (FIG. 7, item 174) and the dielectric layer (FIG. 7, item 172) comprise different respective materials ([0060], i.e. the second dielectric layer 174 may be formed of a different material from the first dielectric layer patterns 172), and wherein the portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes are spaced apart (FIG. 7, items 72 are spaced apart by item 174) from each other by the insulating division layer (FIG. 7, item 174).
Regarding claim 7. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 6 above.
Koo further discloses wherein a lower surface (FIG. 7, lower surface of item 174) of the insulating division layer (FIG. 7, item 174) is substantially coplanar (FIG. 7, the lower surface of item 174 is substantially coplanar with the lower surfaces of items 185 and 162) with the lower surfaces (FIG. 7, lower surfaces of items 185 and 162) of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes.
Regarding claim 8. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 5 above.
Koo further discloses wherein the insulating division layer (FIG. 7, item 174) is on the upper surface of the first electrode (FIG. 7, item 185), and wherein the second contact plug (FIG. 7, item 164) extends through the insulating division layer (FIG. 7, item 174).
Regarding claim 9. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses further comprising an insulating interlayer (FIG. 7, item 150) that is on the substrate (FIG. 7, item 100) and a sidewall of the first contact plug (FIG. 7, item 155), wherein the portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes are each thinner (FIG. 7 shows item 172 is thinner than item 155), in a horizontal direction perpendicular to the vertical direction, than each of the first contact plug (FIG. 7, item 155), the first electrode (FIG. 7, item 185), and the second electrode (FIG. 7, item 162).
Regarding claim 24. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses wherein the insulating division layer (FIG. 7, item 174) is on upper surfaces ([0062]-[-0063]) of the first electrodes (FIG. 7, item 185), and wherein the second contact plugs (FIG. 7, item 164) extend through ([0062]-[-0063]) the insulating division layer (FIG. 7, item 174).
Regarding claim 31. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Park et al further discloses wherein the first sidewall (FIG. 6D, item 27) of the first electrode (FIG. 6D, item 27) is adjacent (FIG. 6D, item 100) to the second sidewall (FIG. 6D, item 28) of the second electrode (FIG. 6D, item 28).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Koo (U.S. 2013/0127012) and Park et al (U.S. 2008/0160712) as applied to claim 1 above, and further in view of Kim et al (U.S. 2018/0096935).
Regarding claim 10. Koo and Park et al discloses all the limitations of the semiconductor device according to claim 1 above.
Koo further discloses the capacitor ([Abstract]).
Koo and Park et al fails to explicitly disclose further comprising an insulating interlayer on the capacitor, wherein the second contact plug extends through the insulating interlayer.
However, Kim et al teaches further comprising an insulating interlayer (FIG. 5, item 305), wherein the second contact plug (FIG. 5, item 392) extends through the insulating interlayer (FIG. 5, item 305; [0052], i.e. insulation reinforcing layer 305 may be formed on the first insulating interlayer 300 through which the first contact plugs 332 are formed).
Since Koo, Park et al and Kim et al teach contact plug, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo and Park et al with the teachings of further comprising an insulating interlayer, wherein the second contact plug extends through the insulating interlayer as disclosed by Kim et al. The use of insulation reinforcing layer may be formed on the first insulating interlayer through which the first contact plugs are formed in Kim et al provides for the electrical insulation between the first and third contact plugs may be enhanced (Kim et al, [0052]).
Claims 18, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Koo (U.S. 2013/0127012), Yamazaki et al (U.S. 2011/0033111), and Cho et al (U.S. 2015/0357399).
Regarding claim 18. Koo discloses a semiconductor device (FIG. 7) comprising:
first contact plugs (FIG. 7, item 155) on a substrate (FIG. 7, item 100), the first contact plugs (FIG. 7, item 155) being spaced apart from each (FIG. 7 shows items 155 are spaced apart from each other) other in a horizontal direction ([0062]-[-0063]) substantially parallel to an upper surface of the substrate (FIG. 7, item 100);
first electrodes (FIG. 7, item 185) contacting the first contact plugs (FIG. 7, item 155), respectively, each of the first electrodes (FIG. 7, item 185) having a shape ([0054], i.e. a cylinder shape with a closed bottom. In addition, horizontal sectional views of the lower electrodes 185 (i.e., sectional views taken in planes that are parallel to the top surface of the substrate 100) may each have various shapes such as a circular shape, an oval shape, and a polygonal shape) extending in a vertical direction ([0062]-[-0063]) substantially perpendicular (FIG. 7, item 185 extends in a vertical direction substantially perpendicular to upper surface of item 100) to the upper surface of the substrate (FIG. 7, item 100);
second electrodes (FIG. 7, item 162) spaced apart from the first electrodes (FIG. 7, item 185) in the horizontal direction ([0062]-[-0063]), each of the second electrodes (FIG. 7, item 162) extending in the vertical direction ([0062]-[-0063]);
a dielectric layer (FIG. 7, item 172) on sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes;
an insulating division layer (FIG. 7, item 174) between portions (FIG. 7, item 172) of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes; and
second contact plugs (FIG. 7, item 164) contacting upper surfaces of the second electrodes (FIG. 7, item 162), respectively, wherein the first (FIG. 7, item 185) and second (FIG. 7, item 162) electrodes repeatedly alternate ([0062]-[0063]) with each other in the horizontal direction (FIG. 7, shows item 162 and 185 alternate with each in a horizontal direction),
wherein the insulating division layer (FIG. 7, item 174) includes portions (FIG. 7, portions of item 174 above item 172) that are above ([0059]-[0063]) the upper surfaces (FIG. 7, item 162) of the second electrodes (FIG. 7, item 162) respectively.
Koo fails to explicitly disclose
and an insulating interlayer having portions that are above and aligned in the vertical direction with the upper surfaces of the second electrodes, respectively, the portions of the insulating interlayer separating the second contact plugs from each other in the horizontal direction
wherein the first electrode has a pillar shape, first electrodes being separated from the second electrodes in the horizontal direction by first portions of the dielectric layer that are on first sidewalls of the first electrodes, second portions of the dielectric layer that are on second sidewalls of the second electrodes, and portions of the insulating division layer that are between the first portions and the second portions of the dielectric layer.
However, Yamazaki et al teaches an insulating interlayer (FIG. 1B, item 148) having portions (FIG. 1B, item 148 on left and item 148 on the right) that are above ([0101]) and aligned ([0101]) in the vertical direction (FIG. 1B, up and down) with the upper surfaces (FIG. 1B, items 146b and 146a upper surfaces) of the second electrodes (FIG. 1B, items 146b and 146a), respectively, the portions (FIG. 1B, item 148 on left and item 148 on the right) of the insulating interlayer (FIG. 1B, item 148) separating ([0120]) the second contact plugs (FIG. 1B, items 110a and 110b) from each other in the horizontal direction (FIG. 1B, from left to right)
Since Koo and Yamazaki et al teach capacitor structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo with the teachings of an insulating interlayer having portions that are above and aligned in the vertical direction with the upper surfaces of the second electrodes, respectively, the portions of the insulating interlayer separating the second contact plugs from each other in the horizontal direction as disclosed by Yamazaki et al. The use of insulator 148 is provided to cover the insulator 140 and the conductor 146a and the conductor 110a is provided in an opening formed in the insulator 148 in Yamazaki et al provides for the electrostatic capacitance of the Capacitor 53aa (capacitor 53ab) can be reduced, and the speed of data writing can be increased (Yamazaki et al, [0136]).
Koo and Yamazaki et al fails to explicitly disclose with the first electrode has a pillar shape, first electrodes being separated from the second electrodes in the horizontal direction by first portions of the dielectric layer that are on first sidewalls of the first electrodes, second portions of the dielectric layer that are on second sidewalls of the second electrodes, and portions of the insulating division layer that are between the first portions and the second portions of the dielectric layer.
However, Cho et al teaches with the first electrode (FIG. 1, item 123; [0038]) has a pillar shape ([0042], i.e. lower electrode 123 may have a pillar shape), the first electrodes (FIG. 1, item 123) being separated (FIG. 1, item 126) from the second electrodes (FIG. 1, item 129) in the horizontal direction by first portions (FIG. 1, item 126a) of the dielectric layer (FIG. 1, item 126a) that are on first sidewalls (FIG. 1, item 123) of the first electrodes (FIG. 1, item 123), second portions (FIG. 1, item 126c) of the dielectric layer (FIG. 1, item 126c) that are on second sidewalls (FIG. 1, item 129) of the second electrodes (FIG. 1, item 129), and portions (FIG. 1, item 126b) of the insulating division layer (FIG. 1, item 126b) that are between ([0051]) the first portions (FIG. 1, item 126a) and the second portions (FIG. 1, item 126c) of the dielectric layer (FIG. 1, item 126).
Since Koo, Yamazaki et al and Cho et al teach Capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Koo and Yamazaki et al with the teachings of the first electrode has a pillar shape, with the first electrodes being separated from the second electrodes in the horizontal direction by first portions of the dielectric layer that are on first sidewalls of the first electrodes, second portions of the dielectric layer that are on second sidewalls of the second electrodes, and portions of the insulating division layer that are between the first portions and the second portions of the dielectric layer as disclosed by Cho et al. The use of a capacitor may include a lower electrode electrically connected to a plug that extends through an insulating interlayer to a substrate. The capacitor may further include a dielectric layer structure and an upper electrode sequentially stacked on the lower electrode 123 and the insulating interlayer in Cho et al provides for the capacitor including the dielectric layers may have a reduced leakage current and have a high capacitance (Cho et al, [0022]).
Regarding claim 22. Koo, Yamazaki et al and Cho et al discloses all the limitations of the semiconductor device according to claim 18 above.
Koo further discloses wherein an upper surface ([0053]-[0054]) of the dielectric layer (FIG. 7, item 172) is substantially coplanar ([0053]-[0054]) with upper surfaces ([0053]-[0054]) of the first electrodes (FIG. 7, item 185) and with the upper surfaces ([0053]-[0054]) of the second (FIG. 7, item 162) electrodes.
Regarding claim 23. Koo, Yamazaki et al and Cho et al discloses all the limitations of the semiconductor device according to claim 22 above.
Koo further discloses wherein the portions of the dielectric layer (FIG. 7, item 172) on the sidewalls of the first (FIG. 7, item 185) and second electrodes (FIG. 7, item 162) are spaced apart ([0062]-[0063]) from each other (FIG. 7, items 72 are spaced apart by item 174) by the insulating division layer (FIG. 7, item 177).
Response to Arguments
Applicant's arguments filed July 14, 2026 have been fully considered but they are not persuasive.
Regarding Interview Summary, on page 9, applicant appears to argue that during the interview on May 28, 2026 that the proposed amended claim language overcomes newly cited part of Koo.
Examiner respectfully disagrees with applicant’s assessment. As stated in the interview summary dated June 2, 2026, Examiner state that applicant’s proposed amended independent claim 1 appears to read upon the current art of record.
Regarding Objection to the Specifications, Applicant arguments are persuasive and the objection is withdrawn.
Regarding Rejection under 103, on page 13, applicant appears to argue that Koo fails to disclose in amended independent claim 1, a first portion of the insulating division layer between the first portion of the dielectric layer on the first sidewall of the first electrode and the second portion of the dielectric layer on the second sidewall of the second electrode, and wherein an uppermost surface of a second portion of the insulating division layer is higher than an uppermost surface of the dielectric layer, wherein the first portion of the insulating division layer is continuous with the second portion of the insulating division layer
Examiner disagrees with applicant’s assessment. Koo teaches a first portion of the insulating layer, wherein an uppermost surface of a second portion the insulating division layer is higher than an uppermost surface of the dielectric layer, wherein the first electrode is separated from the second electrode by the dielectric layer, wherein the first portion of the insulating division layer is continuous with the second portion of the insulation division layer.
The limitations that Koo does not disclose are taught by Park et al. Park et al teaches wherein the first electrode is separated from the second electrode by a first portion of the dielectric layer on a first sidewall of the first electrode, a second portion of the dielectric layer on a second sidewall of the second electrode, and a first portion of the insulating division layer between the first portion of the dielectric layer on the first sidewall of the first electrode and the second portion of the dielectric layer on the second sidewall of the second electrode.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 15 of applicant’s remarks, applicant appears to argue that Koo and Cho does not disclose applicant’s amended limitation in claim 18 of an insulating interlayer having portions that are above and aligned in the vertical direction with the upper surfaces of the second electrodes, respectively, the portions of the insulating interlayer separating the second contact plugs from each other in the horizontal direction.
Examiner respectfully agrees with applicant’s assessment. While Koo was not used in applicant’s amended claim limitation argued, Yamazaki et al discloses applicant’s amended claim limitation.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant appears to further argue that Koo and Cho fails to disclose wherein the insulating division layer includes portions that are above the upper surfaces of the second electrodes respectively.
Examiner respectfully disagrees with applicant’s assessment. As cited in the rejection above, Koo discloses wherein the insulating division layer includes portions that are above the upper surfaces of the second electrodes respectively.
On page 16 of applicant’s remarks, applicant appears to argue that the combination of Koo, Park et al, Cho, and Kim does not disclose applicant’s amended would not have satisfied each and every element recited in amended independent claim 18.
Examiner respectfully points out that Park et al and Kim et al were not used in the rejection of independent claim 18. Examiner respectfully points out that Koo, Yamazaki et al, and Cho et al satisfied each and every element recited in amended independent claim 18.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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