DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Remarks, filed 2/5/2026, with respect to the rejection(s) of claim(s) 1 and 11 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hsu, Chung-Wei et al. (Pub No. US 20220320342 A1) (hereinafter, Hsu) in view of Huang, Mao-Lin et al. (Pub No. US 20210359142 A1) (hereinafter, Huang).
6. Applicant’s arguments, see Remarks, filed 2/5/2026, with respect to the rejection of claim 5 under 35 U.S.C. § 112 (b) have been fully considered and are persuasive. The rejection of claim 5 has been withdrawn.
7. Applicant’s arguments, see Remarks, filed 2/5/2026, with respect to the objection of claim 14 have been fully considered and are persuasive. The objection of claim 14 has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1-7 and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Chung-Wei et al. (Pub No. US 20220320342 A1) (hereinafter, Hsu), and further in view of Huang, Mao-Lin et al. (Pub No. US 20210359142 A1) (hereinafter, Huang).
Hsu, Figs 26A/26B: pFET transistor on semiconductor substrate
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Re Claim 1, (Currently Amended) Hsu teaches a semiconductor device comprising:
a semiconductor substrate (Substrate, 101; Fig 26A; ¶[0015]); and
a pFET transistor (Embodiments may be p-type FET or n-type FET; Fig 27A; ¶[0036]) formed on the semiconductor substrate;
wherein the pFET transistor includes a plurality of channel regions (First semiconductor layers; 106; Fig 26A; ¶[0016]), and an uppermost channel region (Uppermost semiconductor layer; 106; Fig 26A; ¶[0016]) of the pFET transistor includes an uppermost active semiconductor layer (Uppermost semiconductor layer; 106; Fig 26A; ¶[0016]) and a capping layer (Capping layer; 157; Fig 26A; ¶[0046]) formed on the uppermost active semiconductor layer.
However, Hsu does not teach wherein the capping layer comprises SiGe having 5-15% Ge content.
In the same field of endeavor, Huang teaches wherein the capping layer (Cladding layer; 240; Fig 24; ¶[0038]) comprises SiGe (Cladding layer 240 comprises SiGe; ¶[0037]) having 5-15% Ge content (Germanium concentration between 1% to 10%; ¶[0038]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a capping layer comprising SiGe having 5-15% Ge content, as taught by Huang, with the semiconductor device as taught by Hsu. One would have been motivated to do this with a reasonable expectation of success because SiGe channels, such as the SiGe cladding layer with a low germanium concentration, allows for tuning a desirable threshold voltages in PFETs (Huang; ¶¶[0004, 0014]).
Hsu, Fig 18: Embodiment of transistor with capping layer
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Re Claim 3, (Original) Hsu teaches the semiconductor device according to claim 1, wherein the capping layer (Capping layer; 161; Fig 18; ¶[0050]) has a thickness of about 2-3 nm (May have thickness of 20 angstroms or 2 nm; ¶[0050]).
Hsu, Fig 19: Embodiment of transistor with interfacial layer around capping layer
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Re Claim 4, (Original) Hsu teaches the semiconductor device according to claim 1, further comprising an interfacial layer (Interfacial layer; 163; Fig 19; ¶[0050]) that is formed around the capping layer (Capping layer; 161; Fig 18; ¶[0050]) and uppermost active semiconductor layer (Semiconductor layer; 106; Fig 19; ¶[0050]).
Re Claim 5, (Currently Amended) Hsu teaches the semiconductor device according to claim 4, further comprising a high-k layer (High-k (HK) dielectric layer; 160; Fig 27A; ¶[0056]) formed on the interfacial layer (Interfacial layer; 163; Fig 19; ¶[0050]; Note: Per ¶[0056] in some embodiments the HK dielectric layer may wrap around interfacial layer 163, though not shown)).
Re Claim 6, (Original) Hsu teaches the semiconductor device according to claim 1, wherein the pFET transistor (Embodiments may be p-type FET or n-type FET; Fig 27A; ¶[0036]) is a nanosheet structure including at least two stacked active semiconductor layers (Three semiconductor layers; 106; Figs 27A/27B; ¶[0043]) surrounded by a WFM layer (Gate electrode layer; 172; Figs 27A/27B; ¶[0043]).
Hsu, Fig 20: Sacrificial oxide layer formed on capping layer
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Re Claim 7, (Original) Hsu teaches the semiconductor device according to claim 1, further comprising a sacrificial oxide layer (Hard mask; 152; Fig 20; ¶[0051]; Note: May contain SiO or AlO) formed on the capping layer (Capping layer; 161; Fig 18; ¶[0050]).
Re Claim 11, (Currently Amended) Hsu teaches a method of forming a semiconductor device, the method comprising:
forming a pFET transistor (Embodiments may be p-type FET or n-type FET; Fig 27A; ¶[0036]) on a semiconductor substrate (Substrate, 101; Fig 26A; ¶[0015]);
wherein the pFET transistor includes a plurality of channel regions (First semiconductor layers; 106; Fig 26A; ¶[0016]), and an uppermost channel region (Uppermost semiconductor layer; 106; Fig 26A; ¶[0016]) of the pFET transistor includes an uppermost active semiconductor layer (Uppermost semiconductor layer; 106; Fig 26A; ¶[0016]) and a capping layer (Capping layer; 157; Fig 26A; ¶[0046]) formed on the uppermost active semiconductor layer.
However, Hsu does not teach wherein the capping layer comprises SiGe having 5-15% Ge content.
In the same field of endeavor, Huang teaches wherein the capping layer (Cladding layer; 240; Fig 24; ¶[0038]) comprises SiGe (Cladding layer 240 comprises SiGe; ¶[0037]) having 5-15% Ge content (Germanium concentration between 1% to 10%; ¶[0038]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a capping layer comprising SiGe having 5-15% Ge content, as taught by Huang, with the semiconductor device as taught by Hsu. One would have been motivated to do this with a reasonable expectation of success because SiGe channels, such as the SiGe cladding layer with a low germanium concentration, allows for tuning a desirable threshold voltages in PFETs (Huang; ¶¶[0004, 0014]).
Re Claim 13, (Original) Hsu teaches the method according to claim 11, wherein the capping layer (Capping layer; 161; Fig 18; ¶[0050]) has a thickness of about 2-3 nm (May have thickness of 20 angstroms or 2 nm; ¶[0050]).
Re Claim 14, (Currently Amended) Hsu teaches the method according to claim 11, further comprising forming an interfacial layer (Interfacial layer; 163; Fig 19; ¶[0050]) around the capping layer (Capping layer; 161; Fig 18; ¶[0050]) and uppermost active semiconductor layer (Semiconductor layer; 106; Fig 19; ¶[0050]).
Re Claim 15, (Currently Amended) Hsu teaches the method according to claim 14, further comprising forming a high-k layer (High-k (HK) dielectric layer; 160; Fig 27A; ¶[0056]) on the interfacial layer (Interfacial layer; 163; Fig 19; ¶[0050]; Note: Per ¶[0056] in some embodiments the HK dielectric layer may wrap around interfacial layer 163, though not shown)).
Re Claim 16, (Original) Hsu teaches the method according to claim 11, wherein the pFET transistor (Embodiments may be p-type FET or n-type FET; Fig 27A; ¶[0036]) is a nanosheet structure including at least two stacked active semiconductor layers (Three semiconductor layers; 106; Figs 27A/27B; ¶[0043]) surrounded by a WFM layer (Gate electrode layer; 172; Figs 27A/27B; ¶[0043]).
Re Claim 17, (Original) Hsu teaches the method according to claim 11, further comprising forming a sacrificial oxide layer (Hard mask; 152; Fig 20; ¶[0051]; Note: May contain SiO or AlO) on the capping layer (Capping layer; 161; Fig 18; ¶[0050]).
10. Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Chung-Wei et al. (Pub No. US 20220320342 A1) (hereinafter, Hsu) in view of Huang, Mao-Lin et al. (Pub No. US 20210359142 A1) (hereinafter, Huang) as applied to claims 1 and 11 above, and further in view of Yang, Chih-Chuan et al. (Pub No. US 20230063098 A1) (hereinafter, Yang).
Yang, Fig 2B: Forming spacer layer over sacrificial oxide layer
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Re Claim 8, (Original) Hsu in view of Huang does not teach the semiconductor device according to claim 7, further comprising a spacer layer formed on the sacrificial oxide layer.
In the same field of endeavor, Yang teaches the semiconductor device according to claim 7, further comprising a spacer layer (Spacer; 124; Fig 2B; ¶[0013]) formed on the sacrificial oxide layer (Sacrificial gate dielectric; 126; Fig 2B; ¶[0018]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a spacer layer formed on the sacrificial oxide layer, as taught by Yang, with the semiconductor device as taught by Hsu in view of Huang. One would have been motivated to do this with a reasonable expectation of success because the sacrificial oxide layer is needed in order to preserve the shape of the surrounding structures, e.g. gate and channels, during the channel release process (Yang, ¶¶[0026-0027]).
Re Claim 18, (Original) Hsu in view of Huang does not teach the method according to claim 17, further comprising forming a spacer layer on the sacrificial oxide layer.
In the same field of endeavor, Yang teaches the method according to claim 17, further comprising forming a spacer layer (Spacer; 124; Fig 2B; ¶[0013]) formed on the sacrificial oxide layer (Sacrificial gate dielectric; 126; Fig 2B; ¶[0018]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a spacer layer formed on the sacrificial oxide layer, as taught by Yang, with the semiconductor device as taught by Hsu in view of Huang. One would have been motivated to do this with a reasonable expectation of success because the sacrificial oxide layer is needed in order to preserve the shape of the surrounding structures, e.g. gate and channels, during the channel release process (Yang, ¶¶[0026-0027]).
11. Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, Chung-Wei et al. (Pub No. US 20220320342 A1) (hereinafter, Hsu) in view of Huang, Mao-Lin et al. (Pub No. US 20210359142 A1) (hereinafter, Huang) as applied to claims 1 and 11 above, and further in view of Chen, Guan-Lin et al. (Pub No. US 20210336024 A1) (hereinafter, Chen).
Chen, Fig 17A: Semiconductor substrate with nFET disposed under pFET
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Re Claim 9, (Original) Hsu in view of Huang does not teach the semiconductor device of claim 1, wherein the semiconductor substrate includes an nFET transistor.
In the same field of endeavor, Chen teaches the semiconductor device of claim 1, wherein the semiconductor substrate (Substrate; 202; Fig 17A; ¶[0020]) includes an nFET transistor (Substrate may contain nFET transistor; Per ¶[0020] substrate includes FET).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the semiconductor substrate which includes an nFET transistor, as taught by Chen, with the semiconductor device as taught by Hsu in view of Huang. One would have been motivated to do this with a reasonable expectation of success in order to create a high-side switch using the pFET while the nFET is used for a low-side switch which connects the output to the ground when the input is high.
Re Claim 10, (Original) Hsu in view of Huang does not teach the semiconductor device of claim 9, further comprising a bonding oxide layer formed on the nFET transistor, wherein the pFET transistor is formed on the bonding oxide layer.
In the same field of endeavor, Chen teaches the semiconductor device of claim 9, further comprising a bonding oxide layer (Isolation structure; 208; Fig 5C; ¶[0030]) formed on the nFET transistor (Substrate may contain nFET transistor; Per ¶[0020] substrate includes FET), wherein the pFET transistor (HKMG; 280B; Fig 17C; ¶[0046]) is formed on the bonding oxide layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a bonding oxide layer formed on the nFET transistor, wherein the pFET transistor is formed on the bonding oxide layer, as taught by Chen, with the semiconductor device as taught by Hsu in view of Huang. One would have been motivated to do this with a reasonable expectation of success such that a complementary circuit may be formed, i.e. a CMOS inverter which are efficient for high-currents due to the nFET having a lower on-resistance than the pFET.
Re Claim 19, (Original) Hsu in view of Huang does not teach the method of claim 11, wherein the semiconductor substrate includes an nFET transistor.
In the same field of endeavor, Chen teaches the method of claim 11, wherein the semiconductor substrate (Substrate; 202; Fig 17A; ¶[0020]) includes an nFET transistor (Substrate may contain nFET transistor; Per ¶[0020] substrate includes FET).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the semiconductor substrate which includes an nFET transistor, as taught by Chen, with the semiconductor device as taught by Hsu in view of Huang. One would have been motivated to do this with a reasonable expectation of success in order to create a high-side switch using the pFET while the nFET is used for a low-side switch which connects the output to the ground when the input is high.
Re Claim 20, (Original) Hsu in view of Huang does not teach the method of claim 19, further comprising forming a bonding oxide layer on the nFET transistor, wherein the pFET transistor is formed on the bonding oxide layer.
In the same field of endeavor, Chen teaches the method of claim 19, further comprising a bonding oxide layer (Isolation structure; 208; Fig 5C; ¶[0030]) formed on the nFET transistor (Substrate may contain nFET transistor; Per ¶[0020] substrate includes FET), wherein the pFET transistor (HKMG; 280B; Fig 17C; ¶[0046]) is formed on the bonding oxide layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a bonding oxide layer formed on the nFET transistor, wherein the pFET transistor is formed on the bonding oxide layer, as taught by Chen, with the semiconductor device as taught by Hsu in view of Huang. One would have been motivated to do this with a reasonable expectation of success such that a complementary circuit may be formed, i.e. a CMOS inverter which are efficient for high-currents due to the nFET having a lower on-resistance than the pFET.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Cheng, Kangguo et al. (Pub No. US 20190237559 A1) discloses fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
[2] Basker, Veeraraghavan S. et al. (Pub No. US 8963248 B2) discloses a method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
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/T.E.D./
Examiner
Art Unit 2817
Supervisory Patent Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/
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