DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/25/2026 has been entered.
Claim Status
Previous action: claims 1, 3 through 14 and 16 through 22 rejected
Present action: claims 1, 3 through 14 and 16 through 22 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 3, 4, 8, 9, 12 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381)
Regarding claim 1.
Eisherbini teaches:
A microelectronic module (fig 1a:100; [para 0079]) comprising:
a module substrate (fig 1a:120; [para 0080]);
a chip (fig 1a:108; [para 0080]) mounted onto the module substrate (fig 1a:120; [para 0080]);
a semiconductor-based integrated passive device (fig 1b:140; [para 0087]) between the chip (fig 1a:108; [para 0080]) and the module substrate (fig 1a:120; [para 0080]),
wherein the semiconductor-based integrated passive device (fig 1b:140; [para 0087]) includes: a bank of capacitors (fig 1c:134; [para 0085]);
a lower back-end-of-the-line (BEOL) stack-up (fig 1b:130; [para 0088]);
an upper stack-up (fig 1b:110; [para 0080]) over the lower BEOL stack-up (fig 1b:130; [para 0088]),
wherein upper wiring layers in the upper stack-up (fig 1b:110; [para 0080]) provide power and ground planes ([para 0055]) for the chip (fig 1a:108; [para 0080]) and the bank of capacitors (fig 1c:134; [para 0085]);
and a layer between the upper stack-up (fig 1b:110; [para 0080]) and the lower BEOL stack-up (fig 1b:130; [para 0088]).
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Eisherbini does not state that the upper stack up layers comprises a redistribution layer
Tsai teaches:
a lower back-end-of-the-line (BEOL) stack-up (fig 9:214””; [para 0023]); an upper redistribution layer (RDL) stack-up (fig 9:232,238’; [para 0025]) over the lower BEOL stack-up (fig 9:214””; [para 0023]),
and a barrier layer (fig 9:220; [para 0023]) between the upper RDL stack-up (fig 9:232,238’; [para 0025]) and the lower BEOL stack-up (fig 9:214””; [para 0023]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the upper stack up layers to comprise a redistribution layer in order to distribute the power and signal contact across the surface thereby optimizing the spacing between wires and vias.
Regarding claim 3.
Eisherbini in view of Tsai teaches the microelectronic module of claim 1, further
Tsai teaches:
the barrier layer (fig 9:220; [para 0023]) comprises a nitride material.
Regarding claim 4
Eisherbini in view of Tsai teaches the microelectronic module of claim 1, further
Eisherbini teaches:
the lower BEOL stack-up (fig 1b:130; [para 0088]), includes lower BEOL wiring layers (fig 1b:146; [para 0088]),
and the upper stack-up includes the upper RDL wiring layers, wherein the upper wiring layers are thicker than the lower BEOL wiring layers.
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Tsai teaches:
the lower BEOL stack-up (fig 9:214””; [para 0023]); includes lower BEOL wiring layers (fig 9:236; [para 0024]);
and the upper RDL stack-up includes the upper RDL wiring layers (fig 9:232,240; [para 0025]),
wherein the upper RDL wiring layers (fig 9:232,238’; [para 0025]) are thicker than the lower BEOL wiring layers.
Regarding claim 8.
Eisherbini in view of Tsai teaches the microelectronic module of claim 4, further
Eisherbini teaches:
the bank of capacitors includes an array of trench capacitors (fig 1c:134; [para 0085]).
Regarding claim 9.
Eisherbini in view of Tsai teaches the microelectronic module of claim 4, further
Eisherbini teaches:
the semiconductor-based integrated passive device includes through silicon vias (TSVs) (fig 1b:132; [para 0084]).
Regarding claim 12.
Eisherbini in view of Tsai teaches the microelectronic module of claim 1, further
Eisherbini teaches:
the chip (fig 1a:108; [para 0084]) includes a chip-level BEOL stack-up (fig 1a:104,126; [para 0084]),
and the upper stack-up (fig 1a,1b:110; [para 0080]) is hybrid bonded (fig 1a,2; [para 0101]) to the chip-level BEOL stack-up (fig 1a,2:104,126; [para 0084]) with an oxide (fig 2:228; [para 0101])-oxide (fig 2:226; [para 0101]) dielectric interface (fig 2:112; [para 0101]) and metal (fig 2:224; [para 0101])-metal (fig 2:222; [para 0101]) contact interfaces (fig 2:112; [para 0101]).
Regarding claim 21.
Eisherbini in view of Tsai teaches the microelectronic module of claim 1, further
Eisherbini teaches:
the lower BEOL stack-up (fig 1b:130; [para 0084]) includes lower BEOL wiring layers (fig 1b:146; [para 0088])within corresponding and lower interlayer dielectric (ILD) layers (fig 1b:148; [para 0088]);
the upper stack-up (fig 1b:130; [para 0084]) includes the upper wiring layers and upper ILD layers;
the upper wiring layers are thicker than the lower BEOL wiring layers;
and the lower ILD layers are formed ,
and the upper ILD layers are formed .
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Tsai teaches:
the lower BEOL stack-up (fig 9:214””; [para 0024]) includes lower BEOL wiring layers (fig 9:236; [para 0024]) within corresponding and lower interlayer dielectric (ILD) layers (fig 9:504; [para 0044]);
the upper RDL stack-up (fig 9:214””; [para 0024]) includes the upper RDL wiring layers (fig 9:238’; [para 0024]) and upper ILD layers (fig 9:504; [para 0044]);
the upper RDL wiring layers (fig 9:238’; [para 0024]) are thicker than the lower BEOL wiring layers (fig 9:236; [para 0024]);
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Regarding vapor depositions techniques and solution based techniques. Note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and related case law cited therein which make it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe,
Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington. 411 F2d 1345, 1348, 162 USPQ 145, 147, (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir 1935).
Note that Applicant bears the burden of proof in such cases as the above case law makes clear.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) as applied to claim 4 and further in view of Gordin (US 2011/0179392).
Regarding claim 5.
Eisherbini in view of Tsai teaches the microelectronic module of claim 4, above.
Eisherbini in view of Tsai does not teach wiring metal density.
Gordin teaches:
Wiring layers are characterized by a metal density of greater than 60% ([para 0081])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide metal wiring density over 60% in order to accord with standard design rules, provide shielding, and withstand dishing (paragraphs 6 through 10)
Further given the teaching of the references, it would have been obvious to determine the optimum metal density involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) as applied to claim 4 and further in view of Yang (US 2021/0134747).
Regarding claim 6.
Eisherbini in view of Tsai teaches the microelectronic module of claim 4, further
Tsai teaches:
the lower BEOL stack-up includes lower interlayer dielectric (ILD) layers (fig 9:504; [para 0044]),
and the upper RDL stack-up includes upper ILD layers (fig 9:504; [para 0044]),
and the barrier layer (fig 9:220; [para 0023]) provides protection against moisture ingress from upper RDL stack-up into the lower BEOL stack-up (annotated fig 9).
Eisherbini in view of Tsai does not teach an organic interlayer dielectric
Yang teaches:
organic interlayer dielectric layer (fig 1:114,120,124; [para 0020,0022])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use organic interlayer dielectric material due to the low k value which will result in less capacitive coupling between lines.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) as applied to claim 4 and further in view of Yang (US 2021/0134747).
Regarding claim 7.
Eisherbini in view of Tsai teaches the microelectronic module of claim 4, further
Eisherbini in view of Tsai does not teach the upper ILD has higher thermal conductivity than the lower ILD.
Yang teaches:
the lower BEOL stack-up includes lower ILD layers (fig 6:114; [para 0020]),
and the upper stack-up includes upper ILD layers (fig 6:118,122a,122b; [para 0034]) characterized by a higher thermal conductivity (silicon carbide and silicon nitride have high thermal conductivity) than the lower ILD layers (organic dielectric polymer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the upper layers of the interlayer dielectric material from high thermal conductive material (ie SiC or SiN) in order to block diffusion of interface contaminants (paragraph 24)
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) as applied to claim 4 and further in view of Tseng (US 2023/0060520).
Regarding claim 10.
Eisherbini in view of Tsai teaches the microelectronic module of claim 4, further
Eisherbini teaches:
the semiconductor-based integrated passive device (fig 1a:106; [para 0079]) is bonded to the chip (fig 1a:108; [para 0079]) and is solder bonded (fig 1a:122; [para 0051]) to the module substrate (fig 1a:120; [para 0080]).
Eisherbini in view of Tsai does not teach solder bonding to the chip.
Tseng teaches:
the semiconductor-based integrated passive device (fig 1:12; [para 0023]) is solder bonded (fig 1,2:14; [para 0037]) to the chip (fig 1:100; [para 0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to solder bond the passive device to the chip in order to provide more margin in the bonding process and allow for a less expensive process.
Regarding claim 11.
Eisherbini in view of Tsai in view of Tseng teaches the microelectronic module of claim 10, further
Eisherbini teaches:
the semiconductor-based integrated passive device (fig 1a:106; [para 0079]) is laterally adjacent a plurality of chip [connectors] (fig 1a:116; [para 0081]) connecting the chip (fig 1a:108; [para 0080]) to the module substrate (fig 1a:120; [para 0080]).
Tseng teaches:
the semiconductor-based integrated passive device (fig 1:12; [para 0011]) is laterally adjacent a plurality of chip solder bumps (fig 1:106; [para 0012]).
Claim(s) 13, 14, 16, 17, 18, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) as applied to claim 12 and further in view of Yang (US 2021/0134747).
Regarding claim 13.
Eisherbini in view of Tsai teaches the microelectronic module of claim 12, further
Eisherbini teaches
the upper stack-up includes upper ILD layers (fig 1b:148; [para 0088]) and the chip-level BEOL stack-up (fig 1a,3:126; [para 0084]) includes chip ILD layers (fig 1a,3:126; [para 0084]),
.
Tsai teaches:
an upper redistribution layer (RDL) stack-up (fig 9:232,238’; [para 0025])
Eisherbini in view of Tsai does not teach the upper ILD has higher thermal conductivity than the lower ILD.
Yang teaches:
the lower BEOL stack-up includes lower ILD layers (fig 6:114; [para 0020]),
and the upper stack-up includes upper ILD layers (fig 6:118,122a,122b; [para 0034]) characterized by a higher thermal conductivity (silicon carbide and silicon nitride have high thermal conductivity) than the lower ILD layers (organic dielectric polymer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the upper layers of the interlayer dielectric material from high thermal conductive material (ie SiC or SiN) in order to block diffusion of interface contaminants (paragraph 24)
Regarding claim 14.
Eisherbini in view of Tsai in view of Yang teaches the microelectronic module of claim 13, further
Eisherbini teaches:
the semiconductor-based integrated passive device (fig 1a:106; [para 0079]) is as wide as the chip (fig 1a:108; [para 0079]).
Regarding claim 16.
Eisherbini in view of Tsai in view of Yang teaches the microelectronic module of claim 13, further
Tsai teaches:
the barrier layer (fig 9:220; [para 0023]) comprises a nitride material ([para 0023]).
Regarding claim 17.
Eisherbini in view of Tsai in view of Yang teaches the microelectronic module of claim 13, further
Eisherbini teaches:
the lower BEOL stack-up includes (fig 1b:130; [para 0088]) lower BEOL wiring layers (fig 1b:146; [para 0088]),
and wherein the upper wiring layers are thicker than the lower BEOL wiring layers.
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Tsai teaches:
the lower BEOL stack-up includes lower BEOL wiring layers (fig 9:236; [para 0024]),
and wherein the upper RDL wiring layers (fig 9:238’; [para 0025]),
are thicker than the lower BEOL wiring layers (fig 9:236; [para 0024]).
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Regarding claim 18.
Eisherbini in view of Tsai in view of Yangteaches the microelectronic module of claim 17, further
Tsai teaches:
the lower BEOL stack-up includes lower interlayer dielectric (ILD) layers (fig 9:504; [para 0044]),
and the upper RDL stack-up includes upper ILD layers (fig 9:504; [para 0044]),
and the barrier layer (fig 9:220; [para 0023]) provides protection against moisture ingress from upper RDL stack-up into the lower BEOL stack-up (annotated fig 9).
Yang teaches:
organic interlayer dielectric layer (fig 1:114,120,124; [para 0020,0022])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use organic interlayer dielectric material due to the low k value which will result in less capacitive coupling between lines.
Regarding claim 19.
Eisherbini in view of Tsai in view of Yang teaches the microelectronic module of claim 13, further
Eisherbini teaches:
the bank of capacitors includes an array of trench capacitors (fig 1c:134; [para 0085]).
Regarding claim 20.
Eisherbini in view of Tsai in view of Yang teaches the microelectronic module of claim 13, further
Eisherbini teaches:
the semiconductor-based integrated passive device includes through silicon vias (TSVs) (fig 1b:132; [para 0084]).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) as applied to claim 1 and further in view of Yang (US 2021/0134747).
Regarding claim 22.
Eisherbini in view of Tsai teaches the microelectric module of claim 1, above.
Eisherbini teaches:
the lower BEOL stack-up (fig 1b:130; [para 0084])includes lower BEOL wiring layers (fig 1b:146; [para 0088]) and lower interlayer dielectric (ILD) layers (fig 1b:148; [para 0088]);
the upper stack-up (fig 1b:130; [para 0084])includes the upper wiring layers (fig 1b:110; [para 0084])and upper ILD layers (fig 1b:148; [para 0088]);
the upper wiring layers are thicker than the lower BEOL wiring layers;
.
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Tsai teaches:
upper RDL stack-up (fig 9:214””; [para 0024])includes the upper RDL wiring layers (fig 9:238’; [para 0025])and upper ILD layers (fig 1b:504’; [para 0088]);
the upper RDL wiring layers (fig 9:238’; [para 0025]) are thicker than the lower BEOL wiring layers (fig 9);
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Eisherbini in view of Tsai does not teach the upper ILD has high thermal conductivity that lower ILD
Yang teaches:
the upper ILD layers (fig 6:118,122a,122b; [para 0023,0034]) are characterized by a higher thermal conductivity (silicon nitride) than the lower ILD layers (fig 6:114; [para 0020]) (porous, organic material) and the upper ILD layers (fig 6:118,122a,122b; [para 0023,0034]) are formed of a material selected from the group consisting of silicon nitride ([para 0034]), aluminum nitride, boron nitride, alumina, and diamond.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the upper layers of the interlayer dielectric material from high thermal conductive material (ie or SiN) in order to block diffusion of interface contaminants (paragraph 24)
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied combination Eisherbini (US 2023/0163098) in view of Tsai (US 2017/0025381) anticipates the claims.
Conclusion
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
April 1, 2026
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