DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 11 December 2025 is acknowledged.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 22 September 2022 and 30 December 2025 have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1-2, 4-4-6, 8-9, 15-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fastow et al (US 20190043836 A1, hereinafter “Fastow”).
Regarding Claim 1 – Fastow discloses a semiconductor structure, comprising: a peripheral complimentary metal-oxide semiconductor (CMOS) substrate (Combination of 282A and 282B [0036] and Fig. 2A); a first vertical NAND cell on a first side of the CMOS substrate (281A [0036] and Fig. 2A); and a second vertical NAND cell on a second side of the CMOS substrate opposite the first side (281B [0036] and Fig. 2A).
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Regarding Claim 2 – Fastow further discloses the semiconductor structure of claim 1, wherein the CMOS substrate comprises: a first CMOS device connected to the first vertical NAND cell ; and a second CMOS device connected to the second vertical NAND cell.
Regarding Claim 4 – Fastow further discloses the semiconductor structure of claim 1, further comprising: a first bitline (First BL in annotated Fig. 2A, based on similarity to 264B in [0022] and Fig. 1A), wherein the first vertical NAND cell is between the first bitline and the CMOS substrate (Fig. 2A); and a second bitline (Second BL in annotated Fig. 2A, based on similarity to 264B in [0022] and Fig. 1A), wherein the second vertical NAND cell is between the second bitline and the CMOS substrate (Fig. 2A).
Regarding Claim 5 – Fastow further discloses the semiconductor structure of claim 4, further comprising: a first via between the first bitline and the CMOS substrate (First Via in annotated Fig. 2A); and a second via between the second bitline and the CMOS substrate (Second Via in annotated Fig. 2A).
Regarding Claim 6 – Fastow further discloses the semiconductor structure of claim 5, wherein the first via is formed in a center of the first vertical NAND cell (The vias are in the center portion of the memory cells in Fig. 2A).
Regarding Claim 8 – Fastow further discloses the semiconductor structure of claim 1, further comprising: two first metal interconnect layers between the CMOS substrate and the first vertical NAND cell (284A [0036] and Fig. 2A); and two second metal interconnect layers between the CMOS substrate and the second vertical NAND cell (284B [0036] and Fig. 2A).
Regarding Claim 9 – Fastow further discloses the semiconductor structure of claim 8, further comprising: two first additional metal interconnect layers (First AML in annotated Fig. 2A), wherein the first vertical NAND cell is between the two first metal interconnect layers and the two first additional metal interconnect layers (Fig. 2A); and two second additional metal interconnect layers (Second AML in annotated Fig. 2A), wherein the second vertical NAND cell is between the two second metal interconnect layers and the two second additional metal interconnect layers (Fig. 2A).
Regarding Claim 15 – Fastow discloses a semiconductor structure, comprising: a first vertical NAND cell (281A [0036] and Fig. 2A) oriented in a first direction relative to a peripheral complimentary metal-oxide semiconductor (CMOS) substrate (Fig. 2A); and a second vertical NAND cell (281B [0036] and Fig. 2A) oriented in a second direction opposite the first direction relative to the CMOS substrate (Fig. 2A).
Regarding Claim 16 – Fastow further discloses the semiconductor structure of claim 15, further comprising: a first bitline (First BL in annotated Fig. 2A, based on similarity to 264B in [0022] and Fig. 1A), wherein the first vertical NAND cell is between the first bitline and the CMOS substrate (Fig. 2A); and a second bitline (Second BL in annotated Fig. 2A, based on similarity to 264B in [0022] and Fig. 1A), wherein the second vertical NAND cell is between the second bitline and the CMOS substrate (Fig. 2A).
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Regarding Claim 17 – Fastow further discloses the semiconductor structure of claim 16, further comprising: a first via between the first bitline and the CMOS substrate (First Via in annotated Fig. 2A); and a second via between the second bitline and the CMOS substrate (Second Via in annotated Fig. 2A).
Regarding Claim 19 – Fastow further discloses the semiconductor structure of claim 15, further comprising: two first metal interconnect layers between the CMOS substrate and the first vertical NAND cell (284A [0036] and Fig. 2A); and two second metal interconnect layers between the CMOS substrate and the second vertical NAND cell (284B [0036] and Fig. 2A).
Regarding Claim 20 – Fastow further discloses the semiconductor structure of claim 19, further comprising: two first additional metal interconnect layers (First AML in annotated Fig. 2A), wherein the first vertical NAND cell is between the two first metal interconnect layers and the two first additional metal interconnect layers (Fig. 2A); and two second additional metal interconnect layers (Second AML in annotated Fig. 2A), wherein the second vertical NAND cell is between the two second metal interconnect layers and the two second additional metal interconnect layers (Fig. 2A).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al (US 20190043836 A1, hereinafter “Fastow”), in view of Huang et al (US 20210134778 A1, hereinafter “Huang”).
Regarding Claim 7 – Fastow discloses all the limitations of claim 1.
Fastow further discloses the CMOS substrate comprises: a first field-effect transistor (FET) comprising a source/drain contact in a first direction (First FET in annotated Fig. 2A); and a second FET comprising a source/drain contact in a second direction opposite the first direction (Second FET in annotated Fig. 2A).
Fastow fails to disclose the first and second field-effect transistors are both in a first orientation.
However, Huang discloses the first and second field-effect transistors are both in a first orientation (Transistors 168 in semiconductor layer 107, Huang [0067], [0074] and Fig. 1B).
Huang discloses an analogous stacked NAND memory structure to Fastow. Huang teaches transistors arranged in the same orientation to enable using a single semiconductor layer for both NAND memory stacks (Huang [0067] and Fig. 1B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Fastow and Huang to use transistors arranged in the same orientation to enable using a single semiconductor layer for both NAND memory stacks.
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Regarding Claim 18 – Fastow discloses all the limitations of claim 15.
Fastow further discloses the CMOS substrate comprises: a first field-effect transistor (FET) comprising a source/drain contact in a first direction (First FET in annotated Fig. 2A); and a second FET comprising a source/drain contact in a second direction opposite the first direction (Second FET in annotated Fig. 2A).
Fastow fails to disclose the first and second field-effect transistors are both in a first orientation.
However, Huang discloses the first and second field-effect transistors are both in a first orientation (Transistors 168 in semiconductor layer 107, Huang [0067], [0074] and Fig. 1B).
Huang discloses an analogous stacked NAND memory structure to Fastow. Huang teaches transistors arranged in the same orientation to enable using a single semiconductor layer for both NAND memory stacks (Huang [0067] and Fig. 1B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Fastow and Huang to use transistors arranged in the same orientation to enable using a single semiconductor layer for both NAND memory stacks.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Fastow et al (US 20190043836 A1, hereinafter “Fastow”), in view of Sugisaki (US 20200098776 A1, hereinafter “Sugisaki”).
Regarding Claim 3 – Fastow discloses all the limitations of claim 2.
Fastow fails to disclose the first CMOS device is insulated from the second CMOS device.
However, Sugisaki discloses the first CMOS device is insulated from the second CMOS device (Sugisaki [0057] and Fig. 3).
Sugisaki discloses a stacked NAND structure analogous to Fastow. Sugisaki teaches isolating adjacent transistors from each other for the benefit of operating them independently (Sugisaki [0057] and Fig. 3). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Fastow and Sugisaki to isolate adjacent transistors from each other for the benefit of operating them independently.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898