DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The amendments to claims 1-3, 8, 15, 17, and 19 in the reply dated 26 May 2026 are acknowledged. Claims 7, 16, and 18 have been cancelled. Claims 10-14 were previously withdrawn as being drawn to nonelected Invention II.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa et al (US 20220139441 A1, hereinafter “Ogawa”).
Regarding Claim 1 - Ogawa discloses a semiconductor structure, comprising: a peripheral complementary metal-oxide semiconductor (CMOS) substrate (712 [0147] and Fig. 27B) comprising: a first field-effect transistor (FET) (e.g. 720S [0155] and Fig. 27B) fabricated in a first orientation comprising a source/drain contact (82 on the gate side of the FET in dielectric 760 [0152] and Fig. 27B) contacting a first metal interconnect layer fabricated on the CMOS substrate in a first direction (780 [0142] and Fig. 27B); and a second FET (e.g. 720B [0157] and Fig. 27B) fabricated in the first orientation comprising a source/drain contact (82 through the substrate of the FET 712 [0152] and Fig. 27B) contacting a second metal interconnect layer fabricated on the CMOS substrate in a second direction opposite the first direction (e.g. 798 [0156] and Fig. 27B); a first vertical NAND cell on the first metal interconnect layer (104 [0158] and Fig. 27B); and a second vertical NAND cell on the second metal interconnect layer (102 [0158] and Fig. 27B).
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Regarding Claim 2 – Ogawa further discloses the semiconductor structure of claim 1, wherein the CMOS substrate comprises: a first CMOS device the first FET is connected to the first vertical NAND cell (720S connected to 104 as in Fig. 27B); and a second CMOS device the second FET is connected to the second vertical NAND cell (720B connected to 102 as in Fig. 27B).
Regarding Claim 8 – Ogawa further discloses the semiconductor structure of claim 1, wherein the first metal interconnect layer comprises two first metal interconnect layers between the CMOS substrate and the first vertical NAND cell (1ML in annotated Fig. 27A); and the second metal interconnect layer comprises two second metal interconnect layers between the CMOS substrate and the second vertical NAND cell (2ML in annotated Fig. 27A).
Claims 15, 17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fastow et al (US 20190043836 A1, hereinafter “Fastow”).
Regarding Claim 15 – Fastow discloses a semiconductor structure, comprising: a first vertical NAND cell (281A [0036] and Fig. 2A) oriented in a first direction relative to a peripheral complimentary metal-oxide semiconductor (CMOS) substrate (Fig. 2A) and fabricated between i) a first metal interconnect layer on a first side of the CMOS substrate (284A [0036] and Fig. 2A) and ii) a first bitline (First BL in annotated Fig. 2A); and a second vertical NAND cell (281B [0036] and Fig. 2A) oriented in a second direction opposite the first direction relative to the CMOS substrate (Fig. 2A) and fabricated between i) a second metal interconnect layer on a second side of the CMOS substrate (284B [0036] and Fig. 2A) and ii) a second bitline (Second BL in annotated Fig. 2A).
Regarding Claim 17 – Fastow further discloses the semiconductor structure of claim 15, further comprising: a first via between the first bitline and the CMOS substrate (First Via in annotated Fig. 2A); and a second via between the second bitline and the CMOS substrate (Second Via in annotated Fig. 2A).
Regarding Claim 19 – Fastow further discloses the semiconductor structure of claim 15, substrate and the second vertical NAND cell (Two or more layers visible in 284B Fig. 2A).
Regarding Claim 20 – Fastow further discloses the semiconductor structure of claim 19, further comprising: two first additional metal interconnect layers (First AML in annotated Fig. 2A), wherein the first vertical NAND cell is between the two first metal interconnect layers and the two first additional metal interconnect layers (Fig. 2A); and two second additional metal interconnect layers (Second AML in annotated Fig. 2A), wherein the second vertical NAND cell is between the two second metal interconnect layers and the two second additional metal interconnect layers (Fig. 2A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al (US 20220139441 A1, hereinafter “Ogawa”), in view of Sugisaki (US 20200098776 A1, hereinafter “Sugisaki”).
Regarding Claim 3 – Ogawa discloses all the limitations of claim 2.
Fastow fails to disclose the first CMOS device is insulated from the second CMOS device.
However, Sugisaki discloses the first CMOS device is insulated from the second CMOS device (Sugisaki [0057] and Fig. 3).
Sugisaki discloses a stacked NAND structure analogous to Ogawa. Sugisaki teaches isolating adjacent transistors from each other for the benefit of operating them independently (Sugisaki [0057] and Fig. 3). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ogawa and Sugisaki to isolate adjacent transistors from each other for the benefit of operating them independently.
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Claims 4-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al (US 20220139441 A1, hereinafter “Ogawa”), in view of Fastow et al (US 20190043836 A1, hereinafter “Fastow”).
Regarding Claim 4 – Ogawa discloses all the limitations of claim 1.
Ogawa further discloses a first bitline (92 in NAND stack 104 [0157] and Fig. 27B) and a second bitline (92 in NAND stack 102 [0157] and Fig. 27B).
Ogawa fails to disclose the first vertical NAND cell is between the first bitline and the CMOS substrate; and a second bitline, wherein the second vertical NAND cell is between the second bitline and the CMOS substrate.
However, Fastow discloses the first vertical NAND cell is between the first bitline and the CMOS substrate (Fig. 2A); and a second bitline (Second BL in annotated Fig. 2A, based on similarity to 264B in [0022] and Fig. 1A), wherein the second vertical NAND cell is between the second bitline and the CMOS substrate (Fig. 2A).
Fastow discloses similar 3D NAND stacks to Ogawa with FET-based logic in the middle. Fastow teaches bonding dice together on the logic side with bitlines on the opposite side of the NAND stack, with vias in the center of the NAND cells, for the benefits of combining the routing of the wordlines and increased signal density (Fastow [0038]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ogawa and Fastow to place the NAND cells between bitlines and CMOS substrate for the benefit of combining wordline routing and increased signal density.
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Regarding Claim 5 – Ogawa modified by Fastow discloses all the limitations of claim 4.
The combination of Ogawa and Fastow further discloses a first via between the first bitline and the CMOS substrate (82 on the NAND side of 780 in Ogawa Fig. 27B and First Via in annotated Fastow Fig. 2A); and a second via between the second bitline and the CMOS substrate (82 on the NAND side of 798 in Ogawa Fig. 27B and Second Via in annotated Fastow Fig. 2A).
Regarding Claim 6 – Ogawa modified by Fastow discloses all the limitations of claim 5.
The combination of Ogawa and Fastow further discloses the first via is formed in a center of the first vertical NAND cell (The vias are in the center portion of the memory cells in Fastow Fig. 2A).
Regarding Claim 9 – Ogawa discloses all the limitations of claim 8.
Ogawa fails to disclose two first additional metal interconnect layers (First AML in annotated Fig. 2A), wherein the first vertical NAND cell is between the two first metal interconnect layers and the two first additional metal interconnect layers (Fig. 2A); and two second additional metal interconnect layers (Second AML in annotated Fig. 2A), wherein the second vertical NAND cell is between the two second metal interconnect layers and the two second additional metal interconnect layers (Fig. 2A).
However, Fastow discloses two first additional metal interconnect layers (First AML in annotated Fig. 2A), wherein the first vertical NAND cell is between the two first metal interconnect layers and the two first additional metal interconnect layers (Fig. 2A); and two second additional metal interconnect layers (Second AML in annotated Fig. 2A), wherein the second vertical NAND cell is between the two second metal interconnect layers and the two second additional metal interconnect layers (Fig. 2A).
Fastow discloses similar 3D NAND stacks to Ogawa with FET-based logic in the middle. Fastow teaches multiple layers of interconnects for the benefit of coupling shared CMOS circuitry for NAND stacks above and below the CMOS substrate (Fastow [0019]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ogawa and Fastow to use multiple interconnect layers for the benefit of coupling shared CMOS circuitry for NAND stacks above and below the CMOS substrate.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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