DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Application 17/932,432 filed on 09/15/2022 claims no priority.
Response to Amendment
This office action is in response to amendments submitted on 12/23/2025 wherein claims 1-15 and 17-20 are pending and ready for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1and 9-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,232,334 (see table below.) Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12,232,334 (see table below) disclose similar functions and limitations as claimed in the claims of the instant application (see table below).
Application 17,932,432
U.S. Patent No. 12,232,334
Independent claim 1
A semiconductor device, comprising:
a sensing module configured to generate a plurality of analog sensing signals;
one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data;
an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data; and
a machine learning processing unit configured to process the digital preprocessed sensing data utilizing one or more machine learning models, wherein the machine learning processing unit is fabricated on a processor wafer of the semiconductor device.
Independent claim 1
A semiconductor device, comprising:
a sensing module configured to generate a plurality of analog sensing signals; and
a machine learning (ML) processor, comprising:
one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data;
an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data; and
a machine learning processing unit configured to process the digital preprocessed sensing data utilizing one or more machine learning models, wherein the sensing module and the ML processor are fabricated on a single wafer, wherein the sensing module is fabricated on a first portion of the wafer, and wherein the ML processor is fabricated on a second portion of the wafer that surrounds the first portion of the wafer.
Claim 9
The semiconductor device of claim 1, further comprising a transceiver configured to: transmit, to a computing device, a predictive output generated by the machine learning processing unit based on the one or more machine learning models; and receive, from the computing device, instructions for performing operations based on the predictive output.
Claim 14
The semiconductor device of claim 1, further comprising a transceiver configured to: transmit, to a computing device, a predictive output generated by the machine learning processing unit based on the one or more machine learning models; and receive, from the computing device, instructions for performing operations based on the predictive output.
Claim 10
The semiconductor device of claim 1, wherein the analog preprocessed sensing data represents a convolution of the analog sensing signals and a kernel.
Claim 15
The semiconductor device of claim 1, wherein the analog preprocessed sensing data represents a convolution of the analog sensing signals and a kernel.
Claim 11
The semiconductor device of claim 10, wherein conductance values of a plurality cross-point devices of the one or more crossbar arrays are programmed to values representing the kernel.
Claim 16
The semiconductor device of claim 15, wherein conductance values of a plurality of cross-point devices of the one or more crossbar arrays are programmed to values representing the kernel.
Claim 12
The semiconductor device of claim 1, wherein the sensing module comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the one or more crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input.
Claim 17
The semiconductor device of claim 1, wherein the sensing module comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the one or more crossbar arrays is configured to receive the analog sensing signals produced by the two- dimensional sensor array as input.
Claim 13
The semiconductor device of claim 12, wherein the one or more crossbar arrays comprises a plurality of crossbar arrays positioned on a plurality of different planes.
Claim 18
The semiconductor device of claim 17, wherein the one or more crossbar arrays comprises a plurality of crossbar arrays positioned on a plurality of different planes.
Claim 14
A semiconductor device, comprising:
a sensor wafer comprising a sensing module configured to generate a plurality of analog sensing signals; and
a processor wafer comprising a machine learning processor configured to produce a predictive output by processing the analog sensing signals using one or more machine learning models, wherein the machine learning processor comprises:
a plurality of crossbar arrays configured to generate a plurality of analog outputs representative of the predictive output; and
an analog-to-digital converter unit configured to convert the plurality of analog outputs representative of the predictive output into a digital signal representative of the predictive output,
wherein the sensor wafer is connected to the processor wafer through a first interconnect layer
Claim 19
A semiconductor device, comprising:
a sensing module configured to generate a plurality of analog sensing signals; and
a machine learning processor configured to produce a predictive output by processing the plurality of analog sensing signals using one or more machine learning models, wherein the machine learning processor comprises:
a plurality of crossbar arrays configured to generate a plurality of analog outputs representative of the predictive output; and
an analog-to-digital converter unit configured to convert the plurality of analog outputs representative of the predictive output into a plurality of digital signals representative of the predictive output, wherein the sensing module and the machine learning processor are fabricated on a wafer,
wherein the sensing module is fabricated on a first portion of the wafer, and wherein the machine learning processor is fabricated on a second portion of the wafer that surrounds the first portion of the wafer.
Claims 2-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,232,334 in view of Enquist et al., U.S. Pub. No. 2002/0189941 A1in view of Boesch et al., U.S. Pub. No. 2019/0340314 A1.
Application 17,932,432
U.S. Patent No. 12,232,334
Claim 2
The semiconductor device of claim 1, wherein the sensing module is fabricated on a sensor wafer, and wherein the sensor wafer is connected to the processor wafer through a first interconnect layer.
While US 12,232,334 claims the semiconductor device of claim 1 (see claim 1 above) US 12,232,334 does not expressly claim the bolded limitations, Enquist teaches the sensing module is fabricated on a sensor wafer, and wherein the sensor wafer is connected to the processor wafer through a first interconnect layer (Enquist, claim 2, claim 13: Claim 2 teaches a first die from a first wafer and a second die from a second wafer where one die is an image sensor (“sensing module”) and the other die is an image processor (“processor”). Claim 13 teaches “conductively bonding an image sensor from a first wafer to first ends of the conductive through-vias in the carrier wafer” and “conductively bonding an image processor from a second wafer to second ends of the conductive through-vias of the carrier wafer” disclosing “the sensor wafer is connected to the processor wafer through a first interconnect layer.”
It would have been obvious to modify the claims of US 12,232,334 by including connecting a sensor wafer to a processor wafer as taught by Enquist in order to reduce the interconnect lengths allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022).)
Claim 3
The semiconductor device of claim 2, wherein the one or more crossbar arrays are fabricated on the processor wafer.
While US 12,232,334 as modified by Enquist claims the semiconductor device of claim 2 which contains a crossbar array (see claim 1 above) US 12,232,334 as modified by Enquist does not expressly claim the bolded limitations the one or more crossbar arrays are fabricated on the processor wafer. Boesch teaches the one or more crossbar arrays are fabricated on the processor wafer (Boesch, fig.3, ¶ 133, ¶ 0142: Boesch teaches crossbar switches (disclosing crossbar arrays) (see fig. 3 element 144, 154) are fabricated on a system on a chip (SoC) which is a single die (¶ 0133,¶ 0142) (disclosing processor wafer.)
It would have been obvious to modify the claims of US 12,232,334 as modified by Enquist by including fabricating a crossbar array on a wafer as taught by Boesch to improve connectivity and provide smaller and thinner packages for modern portable electronics and mobile devices.
Claim 4
The semiconductor device of claim 3, wherein the ADC is fabricated on the processor wafer.
While US 12,232,334 as modified by Enquist and Boesch claims the semiconductor device of claim 3 which contains an ADC (see claim 3 above) US 12,232,334 as modified by Enquist does not expressly claim the bolded limitations the ADC is fabricated on the processor wafer. Boesch teaches the ADC is fabricated on the processor wafer. (Boesch, fig.4, ¶ 0066, ¶ 133, ¶ 0149: Boesch teaches converters fabricated on a system on a chip (SoC) which is a single die (¶ 0066) (disclosing processor wafer.)
It would have been obvious to modify the claims of US 12,232,334 as modified by Enquist by including fabricating a converter on a wafer as taught by Boesch to improve connectivity and provide smaller and thinner packages for modern portable electronics and mobile devices.
Claim 5
The semiconductor device of claim 2, wherein the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals.
Claim 10
The semiconductor device of claim 1, wherein the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals.
Claim 6
The semiconductor device of claim 2, wherein the analog preprocessed sensing data correspond to a plurality of features extracted from the analog sensing signals, and wherein the machine learning processing unit performs machine learning using the extracted features.
Claim 11
The semiconductor device of claim 1, wherein the analog preprocessed sensing data correspond to a plurality of features extracted from the analog sensing signals, and wherein the machine learning processing unit performs machine learning using the extracted features.
Claim 7
The semiconductor device of claim 2, further comprising a packaging substrate, wherein the processor wafer is connected to the packaging substrate through a second interconnect layer.
Claim 12
The semiconductor device of claim 1, further comprising a packaging substrate, wherein the wafer is connected to the packaging substrate through an interconnect layer.
Claim 8
The semiconductor device of claim 2, wherein the machine learning processing unit is powered utilizing the analog sensing signals.
Claim 13
The semiconductor device of claim 1, wherein the ML processor is powered utilizing the analog sensing signals.
Claim 14
A semiconductor device, comprising:
a sensor wafer comprising a sensing module configured to generate a plurality of analog sensing signals; and
a processor wafer comprising a machine learning processor configured to produce a predictive output by processing the analog sensing signals using one or more machine learning models, wherein the machine learning processor comprises:
a plurality of crossbar arrays configured to generate a plurality of analog outputs representative of the predictive output; and
an analog-to-digital converter unit configured to convert the plurality of analog outputs representative of the predictive output into a digital signal representative of the predictive output,
wherein the sensor wafer is connected to the processor wafer through a first interconnect layer
Claim 19
A semiconductor device, comprising:
a sensing module configured to generate a plurality of analog sensing signals; and
a machine learning processor configured to produce a predictive output by processing the plurality of analog sensing signals using one or more machine learning models, wherein the machine learning processor comprises:
a plurality of crossbar arrays configured to generate a plurality of analog outputs representative of the predictive output; and
an analog-to-digital converter unit configured to convert the plurality of analog outputs representative of the predictive output into a plurality of digital signals representative of the predictive output, wherein the sensing module and the machine learning processor are fabricated on a wafer,
wherein the sensing module is fabricated on a first portion of the wafer, and wherein the machine learning processor is fabricated on a second portion of the wafer that surrounds the first portion of the wafer.
While US 12,232,334 claims a sensing module and machine learning processor on a wafer (see above) US 12,232,334 does not expressly claim the bolded limitations, Enquist teaches the sensor wafer is connected to the processor wafer through a first interconnect layer (Enquist, claim 2, claim 13: Claim 2 teaches a first die from a first wafer and a second die from a second wafer where one die is an image sensor (“sensing module”) and the other die is an image processor (“processor”). Claim 13 teaches “conductively bonding an image sensor from a first wafer to first ends of the conductive through-vias in the carrier wafer” and “conductively bonding an image processor from a second wafer to second ends of the conductive through-vias of the carrier wafer” disclosing “the sensor wafer is connected to the processor wafer through a first interconnect layer.”
It would have been obvious to modify the claims of US 12,232,334 by including connecting a sensor wafer to a processor wafer as taught by Enquist in order to reduce the interconnect lengths allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022).)
Claims 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,232,334 in view of Xuan Zhang et al., U.S. Pat. No. 10,970,441 B1.
Regarding claim 15: While US 12,232,334 teaches “The semiconductor device of claim 14,” US 12,232,334 does not expressly claim “a transceiver configured to transmit, to a computing device, a signal representative of a predictive output generated by the machine learning processor.” Xuan teaches a design system that uses machine learning (col 6 line 55-62) and “hardware substrate 305 also receives input information from design system server 310 and transmits output signals to design system 310” (col 35 line 54-57) where the “hardware substrate” is a “configurable platform” which is communicatively coupled to “design server 310” through many interfaces including a cellular phone, smart phone, a tablet, smart watch or “other web-based connectable equipment or mobile devices” disclosing a transceiver (col 35 line 57- col 36 line 3.)
It would have been obvious to modify the claims of US 12,232,334 including a transceiver as taught by Xuan to provide a system which integrates the functions of two devices into one device thereby reducing the complexity and cost of the system.
Claims 16 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,232,334 in view of Enquist et al., U.S. Pub. No. 2002/0189941 A1.
Regarding claim 16: While US 12,232,334 claims the semiconductor device of claim 14 where the machine learning processor is fabricated on a wafer (see claim 14 above) US 12,232,334 does not expressly claim “the sensing module is fabricated on a sensor wafer, and wherein the sensor wafer is connected to the processor wafer through a first interconnect layer.” Enquist teaches in claim 2 a first die from a first wafer and a second die from a second wafer where one die is an image sensor (“sensing module”) and the other die is an processor. Claim 13 teaches “conductively bonding an image sensor from a first wafer to first ends of the conductive through-vias in the carrier wafer” and “conductively bonding an image processor from a second wafer to second ends of the conductive through-vias of the carrier wafer” disclosing “the sensor wafer is connected to the processor wafer through a first interconnect layer.”
It would have been obvious to modify the claims of US 12,232,334 by including connecting a sensor wafer to a processor wafer as taught by Enquist in order to reduce the interconnect lengths allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022.)
Regarding claim 17: While US 12,232,334 as modified by Enquist claims the semiconductor device of claim 16 (see above) US 12,232,334 as modified does not claim “a packaging substrate, wherein the processor wafer is connected to the packaging substrate through a second interconnect layer.” Enquist teaches, in claim 2, a first die from a first wafer and a second die from a second wafer where one die is an processor where each die is connected to a silicon layer (packaging substrate) with “through-vias (e.g., 118 & 120) or other interconnects” (¶ 0037, fig. 1.)
It would have been obvious to modify the claims of US 12,232,334 by including connecting a processor wafer to a packaging substrate as taught by Enquist in order to reduce the interconnect lengths reducing electrical interference and allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022.)
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,232,334 in view of Olsson et al., U.S. Pub. No. 2017/0176344 A9.
Regarding claim 18: While US 12,232,334 claims the semiconductor device of claim 14 (see above) US 12,232,334 does not claim “the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals.” Olsson teaches an image sensor array (¶ 0051) where the images are analog signals (¶ 0054, ¶ 0060.)
It would have been obvious to modify the claims of US 12,232,334 by including analog image signals as taught by Olsson as analog image signals provide a wider range of detail and nuances compared to digital signals to provide a system with an improved “image and/or video quality at the display device or on a stored image or video signal” (Olsson, ¶ 0132.)
Claims 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12,232,334 in view of Olsson et al., U.S. Pub. No. 2017/0176344 A9 in view of Xuan Zhang et al., U.S. Pat. No. 10,970,441 B1.
Regarding claim 19: While US 12,232,334 claims the semiconductor device of claim 14 (see above) US 12,232,334 does not claim “the sensing module comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the plurality of crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input.” Olsson teaches a two-dimensional sensor array (see fig. 30.)
It would have been obvious to modify the claims of US 12,232,334 by including an image sensor array as taught by Olsson as an image sensor array can capture a multiple images in a wider field of view in order to provide a system with an improved “image and/or video quality at the display device or on a stored image or video signal” (Olsson, ¶ 0132.)
Xuan teaches “RRAM (resistive random-access memory) crossbar arrays and inverter circuits are used at each layer to perform the basic NN (neural network) operations in the analog domain” (col 22 line 7-28.)
It would have been obvious to modify the claims of US 12,232,334 by including using crossbar array to receive analog sensing signals as disclosed by Xuan in order to provide a system that is not reliant on human experts but on design automation in order to provide a system with improved productivity and performance (Xuan, col 3 line 63-col 4 line 5.)
Regarding claim 20: While US 12,232,334 as modified by Olsson claims the semiconductor device of claim 14 (see above) US 12,232,334 as modified does not claim “the plurality of crossbar arrays is positioned at different planes.” Xuan teaches “RRAM (resistive random-access memory) crossbar arrays and inverter circuits are used at each layer to perform the basic NN (neural network) operations in the analog domain” (col 22 line 7-28.)
It would have been obvious to modify the claims of US 12,232,334 by including using crossbar arrays at different layers to receive analog sensing signals as disclosed by Xuan in order to provide a system that is not reliant on human experts but on design automation in order to provide a system with improved productivity and performance (Xuan, col 3 line 63-col 4 line 5.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Xuan Zhang et al., hereinafter Xuan, U.S. Pat. No. 10,970,441 B1 in view of Mazed, U.S. Pat. No. 11,320,588 B1.
Regarding independent claim 1 Xuan teaches:
“A semiconductor device” (Xuan, col 6 line 63-col 7 line 8: Xuan teaches a system with semiconductor components disclosing a semiconductor device.)
“comprising: a sensing module configured to generate a plurality of analog sensing signals” (Xuan, fig 2C, col 5 line 53-col 6 line 4, col 19 line 26-52: Fig 2C depicts data from a an image sensor as input of the NeuADC , which is an analog to digital converter (col 5 line 53-64). Therefore the data from the image sensor must be “analog sensing signals.” Moreover, “the design system records multiple analog signals (for example, a large number of intensity measurements at each pixel in a camera”(col 19 line 26-52) therefore the sensing module must “generate a plurality of analog sensing signals.”)
“one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data” (Xuan, fig. 15a-15c, col 22 line 7- col 24 line 42: Xuan teaches “The overall circuit architecture of the NeuADC framework that realizes a three-layer MLP is illustrated in fig. 15(a). In this embodiment, RRAM crossbar arrays and inverter circuits are used at each layer to perform the basic NN operations (VMM and NAF) in the analog domain”(col 22 line 7-28) where the “synthesizable comparators implemented with a three-input NAND gate are used in the output layer, since final digitalization of output has to be performed” (col 24 line 19-42) disclosing the crossbars process analog signals and then they are converted to digital signals.)
“a machine learning processing unit configured to process the digital preprocessed sensing data utilizing one or more machine learning models” (Xuan, col 18 line 1-25, col 39 line 1-20: Xuan teaches “a digital quantized numerical signal being provided as input to the neural network, which is then trained to produce some desired class label or numerical output” (col 18 line 14-25).)
Xuan does not teach:
“the machine learning processing unit is fabricated on a processor wafer of the semiconductor device.”
Mazed teaches:
“the machine learning processing unit is fabricated on a processor wafer of the semiconductor device.” (Mazed, fig 15C, Abstract, col 58 line 4-7: Mazed teaches a “Super System on Chip (SSoC) coupled with a photonic neural learning processor (PNLP) (machine learning processing unit) and Fig. 15C depicts a wafer with photonic integrated circuits disclosing the PNLP is fabricated on a processor wafer.
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan by including the processing unit being fabricated on a wafer as taught by Mazed in order to provide a system that is space efficient (miniaturized) with improved electrical performance such as signal integrity at high frequencies.
Regarding claim 9 Xuan as modified teaches:
“comprising a transceiver configured to: transmit, to a computing device, a predictive output generated by the machine learning processing unit based on the one or more machine learning models; and receive, from the computing device, instructions for performing operations based on the predictive output.” (Xuan, fig 27, fig. 28, col 35 line 57- col 36 line 3: Xuan teaches a design system that uses machine learning (col 6 line 55-62) and “hardware substrate 305 also receives input information from design system server 310 and transmits output signals to design system 310” (col 35 line 54-57) where the “hardware substrate” is a “configurable platform” which is communicatively coupled to “design server 310” through many interfaces including a cellular phone, smart phone, a tablet, smart watch or “other web-based connectable equipment or mobile devices” disclosing a transceiver (col 35 line 57- col 36 line 3). Moreover, fig 28 depicts a user computer device 402 which “may include, but is not limited to, hardware substrate 305 and user computer devices 325” (col 36 line 36-49) which contains instructions for output from the “hardware substrate 305.”)
Claims 2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed as applied to claim 1 above, and further in view of Enquist et al., U.S. Pub. No. 2022/0189941 A1.
Regarding claim 2 Xuan as modified does not teach:
“the sensing module is fabricated on a sensor wafer, and wherein the sensor wafer is connected to the processor wafer through a first interconnect layer.”
Enquist teaches:
“the sensing module is fabricated on a sensor wafer, and wherein the sensor wafer is connected to the processor wafer through a first interconnect layer.” (Enquist, claim 2, claim 13: Claim 2 teaches a first die from a first wafer and a second die from a second wafer where one die is an image sensor (“sensing module”) and the other die is an image processor (“processor”). Claim 13 teaches “conductively bonding an image sensor from a first wafer to first ends of the conductive through-vias in the carrier wafer” and “conductively bonding an image processor from a second wafer to second ends of the conductive through-vias of the carrier wafer” disclosing “the sensor wafer is connected to the processor wafer through a first interconnect layer.”
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including connecting a sensor wafer to a processor wafer as taught by Enquist in order to reduce the interconnect lengths allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022.)
Regarding claim 7 Xuan as modified does not teach:
“a packaging substrate, wherein the processor wafer is connected to the packaging substrate through a second interconnect layer.”
Enquist teaches:
“a packaging substrate, wherein the processor wafer is connected to the packaging substrate through a second interconnect layer” (Enquist, claim 2, fig. 1, ¶ 0037: Enquist teaches, in claim 2, a first die from a first wafer and a second die from a second wafer where one die is an processor and where each die is connected to a silicon layer (packaging substrate) with “through-vias (e.g., 118 & 120) or other interconnects” (¶ 0037, fig. 1).)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan by including connecting a processor wafer to a packaging substrate as taught by Enquist in order to reduce the interconnect lengths thereby reducing electrical interference and allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022.)
Regarding claim 8 Xuan as modified teaches:
“the machine learning processing unit is powered utilizing the analog sensing signals.” (Xuan, fig. 2C, col 18 line 1-36, col 39 line 1-20: Muan teaches a computational processing module that preforms quantization and back-propagation using the neural network processes digital output from neuADC as shown in fig. 2C which is based on analog signals from the image sensor.)
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed and Enquist as applied to claim 2 above, and further in view of Boesch et al., hereinafter Boesch, U.S. Pub. No. 2019/0340314 A1.
Regarding claim 3 Xuan as modified does not teach:
“the one or more crossbar arrays are fabricated on the processor wafer.”
Boesch teaches:
“the one or more crossbar arrays are fabricated on the processor wafer” (Boesch, fig.3, ¶ 133, ¶ 0142: Boesch teaches crossbar switches (disclosing crossbar arrays) (see fig. 3 element 144, 154) are fabricated on a system on a chip (SoC) which is a single die (¶ 0133,¶ 0142) (disclosing processor wafer.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including fabricating a crossbar array on a wafer as taught by Boesch to improve connectivity and provide smaller and thinner packages for modern portable electronics and mobile devices.
Regarding claim 4 Xuan as modified does not teach:
“the ADC is fabricated on the processor wafer.”
Boesch teaches:
“the ADC is fabricated on the processor wafer” (Boesch, fig.4, ¶ 0066, ¶ 133, ¶ 0149: Boesch teaches converters fabricated on a system on a chip (SoC) which is a single die (¶ 0066) (disclosing processor wafer.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including fabricating a converter on a wafer as taught by Boesch to improve connectivity and provide smaller and thinner packages for modern portable electronics and mobile devices.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed and Enquist as applied to claim 2 above, and further in view of Olsson et al., hereinafter Olsson, U.S. Pub. No. 2017/0176344 A9.
Regarding claim 5 Xuan as modified does not teach:
“the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals.”
Olsson teaches:
“the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals” (Olsson, ¶ 0054, ¶ 0060: Olsson teaches an image sensor array (¶ 0051) where the images are analog signals
(¶ 0054, ¶ 0060.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including analog image signals as taught by Olsson as analog image signals provide a wider range of detail and nuances compared to digital signals to provide a system with an improved “image and/or video quality at the display device or on a stored image or video signal” (Olsson, ¶ 0132.)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed and Enquist as applied to claim 2 above, and further in view of Mori et al., hereinafter Mori, U.S. Pub. No. 2006/0115157 A1.
Regarding claim 6 Xuan as modified does not teach:
“the analog preprocessed sensing data correspond to a plurality of features extracted from the analog sensing signals, and wherein the machine learning processing unit performs machine learning using the extracted features.”
Mori teaches:
“the analog preprocessed sensing data correspond to a plurality of features extracted from the analog sensing signals, and wherein the machine learning processing unit performs machine learning using the extracted features.” (Mori, ¶ 0297-¶ 0301, ¶ 0498-¶ 0499: Mori teaches a neural network (machine learning) using “parameters and a feature vector (extracted features) calculated from an input image” (¶ 0299). Moreover, after the image is converted into an electrical signal the “video signal processing circuit 6832 A/D-converts this electrical signal” disclosing the image signal is an analog signal.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including the well know machine learning technique of using extracted features as taught by Mori as feature extraction allows machine learning models to learn more effectively, leading to more accurate predictions and efficient processing leading to reducing computational costs.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed as applied to claim 1 above, and further in view of Boesch et al., hereinafter Boesch, U.S. Pub. No. 2019/0340314 A1.
Regarding claim 10:
While Xuan as modified teaches “analog preprocessed sensing data” (col 22 line 7-28) Xuan does not teach the “preprocessed sensing data represents a convolution of the sensing signals and a kernel.”
Boesch teaches a convolution process that produces a kernel map (¶ 0047.) Therefore the combination of Xuan as modified and Boesch discloses the limitation “the analog preprocessed sensing data represents a convolution of the analog sensing signals and a kernel.”
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including the well known algorithm of convolution and kernels as taught by Boesch in order to reduce the number of parameters in a neural network making it more efficient and faster to train saving both time and money.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed and Boesch as applied to claim 10 above, and further in view of Kim, U.S. Pub. No. 2021/0365765 A1.
Xuan as modified does not teach:
“conductance values of a plurality cross-point devices of the one or more crossbar arrays are programmed to values representing the kernel.”
Kim teaches:
“conductance values of a plurality cross-point devices of the one or more crossbar arrays are programmed to values representing the kernel” (Kim, fig. 6, ¶ 0083: Kim teaches “weight values of the learned kernel may be obtained and stored in the crossbar array circuit 600” where the “the weight values respectively stored in the memory cells may be representative conductance 602” where “weight values of the learned kernel” disclose “values representing the kernel” and “the memory cells” of the “crossbar array” disclose “a plurality cross-point devices.”)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including the well know technique of conductance values associated with a crossbar array representing the kernel as taught as taught by Kim as representing kernels using conductance values as conductance provides a natural way to measure the connectivity between different parts of a graph or dataset providing valuable insight into underlying relationships and structure of data in order to provide “higher classification accuracy with implementation of the neural network” (Kim, ¶ 0114).
Claim 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed as applied to claim 1 above, and further in view of Olsson et al., U.S. Pub. No. 2017/0176344 A9.
Regarding claim 12 Xuan as modified teaches:
“wherein a plurality of cross-point devices of the one or more crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input.” (Xuan, col 22 line 7-28: Xuan teaches “RRAM (resistive random-access memory) crossbar arrays and inverter circuits are used at each layer to perform the basic NN (neural network) operations in the analog domain” (col 22 line 7-28).)
Xuan does not teach:
“the sensing module comprises a two-dimensional sensor array”
Olsson teaches:
“the sensing module comprises a two-dimensional sensor array” Olsson teaches a two-dimensional sensor array (see fig. 30.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including an image sensor array as taught by Olsson as an image sensor array can capture a multiple images in a wider field of view in order to provide a system with an improved “image and/or video quality at the display device or on a stored image or video signal” (Olsson, ¶ 0132.)
Regarding claim 13 Xuan as modified teaches:
“the one or more crossbar arrays comprises a plurality of crossbar arrays positioned on a plurality of different planes” (Xuan, col 22 line 7-28: Xuan teaches “RRAM (resistive random-access memory) crossbar arrays and inverter circuits are used at each layer to perform the basic NN (neural network) operations in the analog domain” (col 22 line 7-28) where the different layers disclose different planes.)
Claim 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xuan Zhang et al., hereinafter Xuan, U.S. Pat. No. 10,970,441 B1 in view of Mazed, U.S. Pat. No. 11,320,588 B1, in view of Enquist et al., U.S. Pub. No. 2022/0189941 A1.
Regarding independent claim 14 Xuan teaches:
“A semiconductor device” (Xuan, col 6 line 63-col 7 line 8: Xuan teaches a system with semiconductor components disclosing a semiconductor device.)
“comprising: a sensing module configured to generate a plurality of analog sensing signals” (Xuan, fig 2C, col 5 line 53-col 6 line 4: Fig 2C depicts data from a an image sensor as input of the NeuADC , which is an analog to digital converter (col 5 line 53-64) disclosing the data from the image sensor are “analog sensing signals.” Moreover, “the design system records multiple analog signals (for example, a large number of intensity measurements at each pixel in a camera”(col 19 line 26-52) disclosing the sensing module “generate a plurality of analog sensing signals.”)
a machine learning processor configured to produce a predictive output by processing the analog sensing signals using one or more machine learning models (Xuan, fig 2A-2C, col 16 line 62 - col 18 line 36: Xuan teaches a NeuADC and neural network computational processing module to perform quantization and back-propagation by processing analog signals to produce predictive outputs. Moreover, machine learning “involves identifying patterns in existing data to make predictions about subsequently received data” (col 39 line 1-20).)
“wherein the machine learning processor comprises: a plurality of crossbar arrays configured to generate a plurality of analog outputs representative of the predictive output: and an analog-to-digital convert unit configured to convert the plurality of analog outputs representative of the predictive output into a digital signal representative of the predictive output.” (Xuan, fig. 15a-15c, col 22 line 7- col 24 line 42, col 39 line 1-20: Xuan teaches “The overall circuit architecture of the NeuADC framework that realizes a three-layer MLP is illustrated in fig. 15(a). In this embodiment, RRAM crossbar arrays and inverter circuits are used at each layer to perform the basic NN operations (VMM and NAF) in the analog domain”(col 22 line 7-28) where the “synthesizable comparators implemented with a three-input NAND gate are used in the output layer, since final digitalization of output has to be performed” (col 24 line 19-42) disclosing the crossbars process analog signals and then they are converted to digital signals. Moreover, machine learning “involves identifying patterns in existing data to make predictions about subsequently received data” (col 39 line 1-20).)
While Xuan teaches a machine learning processor, Xuan does not teach the machine learning processor is part of “a processor wafer.”
Mazed teaches: a “Super System on Chip (SSoC) coupled with a photonic neural learning processor (PNLP) (machine learning processing unit) (see Abstract, col 58 line 4-7) and Fig. 15C depicts a wafer with photonic integrated circuits disclosing the PNLP is fabricated on a processor wafer.
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan by including the processing unit being fabricated on a wafer as taught by Mazed in order to provide a system that is space efficient (miniaturized) with improved electrical performance such as signal integrity at high frequencies.
Xuan does not teach:
“a sensor wafer”
“the sensor wafer is connected to the processor wafer through a first interconnect layer.”
Enquist teaches:
“the sensor wafer is connected to the processor wafer through a first interconnect layer.” (Enquist, claim 2, claim 13: Claim 2 teaches a first die from a first wafer and a second die from a second wafer where one die is an image sensor (“sensor wafer”) and the other die is an image processor (“processor wafer”). Claim 13 teaches “conductively bonding an image sensor from a first wafer to first ends of the conductive through-vias in the carrier wafer” and “conductively bonding an image processor from a second wafer to second ends of the conductive through-vias of the carrier wafer” disclosing “the sensor wafer is connected to the processor wafer through a first interconnect layer.”
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including connecting a sensor wafer to a processor wafer as taught by Enquist in order to reduce the interconnect lengths allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022.)
Regarding claim 15 Xuan teaches:
“a transceiver configured to transmit, to a computing device, a signal representative of a predictive output generated by the machine learning processor” (Xuan, col 6 line 55-62, col 35 line 51-col 36 line 3 : Xuan teaches a design system that uses machine learning (col 6 line 55-62) and “hardware substrate 305 also receives input information from design system server 310 and transmits output signals to design system 310” (col 35 line 54-57) where the “hardware substrate” is a “configurable platform” which is communicatively coupled to “design server 310” through many interfaces including a cellular phone, smart phone, a tablet, smart watch or “other web-based connectable equipment or mobile devices” disclosing a transceiver (col 35 line 57- col 36 line 3).)
Regarding claim 17 Xuan as modified does not teach:
“a packaging substrate, wherein the processor wafer is connected to the packaging substrate through a second interconnect layer.”
Enquist teaches:
“a packaging substrate, wherein the processor wafer is connected to the packaging substrate through a second interconnect layer” Enquist, claim 2, fig. 1, ¶ 0037: Enquist teaches, in claim 2, a first die from a first wafer and a second die from a second wafer where one die is an processor where each die is connected to a silicon layer (packaging substrate) with “through-vias (e.g., 118 & 120) or other interconnects” (¶ 0037, fig. 1.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan as modified by including connecting a processor wafer to a packaging substrate as taught by Enquist in order to reduce the interconnect lengths reducing electrical interference and allowing for faster data transfer in order to provide a system with “increased throughput in production volume per unit of time” (Enquist, ¶ 0022.)
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xuan as modified by Mazed and Enquist as applied to claim 14 above, and further in view of Olsson et al., U.S. Pub. No. 2017/0176344 A9.
Regarding claim 18 Xuan does not teach:
“the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals.”
Olsson teaches:
“the sensing module comprises an array of image sensors, wherein the plurality of analog sensing signals comprises a plurality of analog image signals” (Olsson, ¶ 0051,
¶ 0054, ¶ 0060: Olsson teaches an image sensor array (¶ 0051) where the images are analog signals (¶ 0054, ¶ 0060.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan by including analog image signals as taught by Olsson as analog image signals provide a wider range of detail and nuances compared to digital signals to provide a system with an improved “image and/or video quality at the display device or on a stored image or video signal” (Olsson, ¶ 0132.)
Regarding claim 19 Xuan teaches:
“a plurality of cross-point devices of the plurality of crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input” (Xuan, col 22 line 7-28: Xuan teaches “RRAM (resistive random-access memory) crossbar arrays and inverter circuits are used at each layer to perform the basic NN (neural network) operations in the analog domain” (col 22 line 7-28).)
Xuan does not teach:
“the sensing module comprises a two-dimensional sensor array”
Olsson teaches:
“the sensing module comprises a two-dimensional sensor array” (Olsson, fig. 30: Olsson teaches a two-dimensional sensor array (see fig. 30).)
Therefore the combination of Xuan and Olsson teaches the limitations “the sensing module comprises a two-dimensional sensor array, wherein a plurality of cross-point devices of the plurality of crossbar arrays is configured to receive the analog sensing signals produced by the two-dimensional sensor array as input.” Olsson teaches a two-dimensional sensor array (see fig. 30.)
It would have been obvious to a person of ordinary skill in the art to have modified the semiconductor device as taught by Xuan by including an image sensor array as taught by Olsson as an image sensor array can capture a multiple images in a wider field of view in order to provide a system with an improved “image and/or video quality at the display device or on a stored image or video signal” (Olsson, ¶ 0132.)
Regarding claim 20 Xuan as modified teaches:
“the plurality of crossbar arrays is positioned at different planes” Xuan teaches “RRAM (resistive random-access memory) crossbar arrays and inverter circuits are used at each layer to perform the basic NN (neural network) operations in the analog domain” (col 22 line 7-28) where “each layer” represents a different plane.)
Applicant’s arguments (remarks) filed on 12/23/2026 have been fully considered.
Regarding Response to Claim Objections page 8 of Applicant’s remarks, due to Applicant’s arguments and changes made to the claim, the objections have been withdrawn.
Regarding Non-statutory Obviousness-Type Double Patenting Rejection page 8-9 of Applicant’s remarks, Examiner acknowledges Applicant’s remarks and maintains the Double Patenting Rejection.
Regarding Rejection under 35 U.S.C. § 102 page 9-10 of Applicant’s remarks, Examiner finds Applicant’s arguments persuasive with respect to the amendments. New grounds for rejection are necessitated by the amendments and are presented above.
Applicant argues “The Office Action asserts that Xuan teaches the claimed machine learning processor by disclosing a NeuADC and a neural-network-based computational processing module that perform quantization and back-propagation to produce predictive outputs. (Office Action, p. 17.) This characterization misrepresents Xuan's disclosure.
As discussed in Xuan, the neural network (NN) is used to design, train, and optimize the quantization behavior of the NeuADC itself. (Xuan, col. 18 lines 14-30.) The NN in Xuan does not process analog sensing signals generated by a sensing module to produce a predictive output, as required by claim 14. Rather, the NN operates within the ADC framework to shape how analog signals are quantized” (remarks page 10).
Examiner respectfully disagrees. Xuan teaches “basic NN operations (VMM and NAF) in the analog domain” (col 22 line 7-28) where both VMM and NAF produce predictions. Additionally, the “design system is configured to implement machine learning, such that the neural network (NN) ‘learns’ to analyze, organize, and/or process data without being explicitly programmed” (Xuan col 38 line 32-35) where “ML (machine learning) methods and algorithms are directed toward supervised learning, which involves identifying patterns in existing data to make predictions about subsequently received data” (Xuan col 39 line 1-4). Therefore Xuan teaches a neural network system that processes analog sensing signals generated by a sensing module to produce a predictive output, “as required by claim 14” as the NN operations are in the “analog domain” (see above).
Applicant argues “Moreover, the crossbar arrays disclosed in Xuan are used to implement the NeuADC, which Xuan characterizes as an analog-to-digital converter. Xuan therefore does not disclose a separate analog-to-digital converter configured to convert a plurality of analog outputs representative of a predictive output into a corresponding digital signal representative of the predictive output, as recited in amended claim 14” (remarks page 10).
Examiner respectfully disagrees. Applicant’s argument is not germane as according to MPEP 2145 VI, “Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims.” Also stated in MPEP 2111.01 II “Though understanding the claim language may be aided by explanation contained in the written description, it is important not to import into claim limitations that are not part of the claim” (1st paragraph). Additionally, MPEP 2111 states that “an examiner must construe claim terms in the broadest reasonable manner during prosecution as is reasonable allowed in an effort to establish a clear record of what applicant intends to claim” (4th paragraph). Examiner uses the broadest reasonable interpretation to interpret “an analog-to-digital convert unit configured to convert the plurality of analog outputs representative of the predictive output into a digital signal representative of the predictive output.”
Regarding Rejection under 35 U.S.C. § 103 page 10-13 of Applicant’s remarks, Applicant argues “The Office action then refers to the NeuADC framework as allegedly teaching the crossbar arrays and the ADC as recited in claim 1. (Office action, pages 19-20.) However, as described in Xuan and acknowledged in the Office action, the crossbar arrays in Xuan are components of the NeuADC itself, which is an analog-to-digital converter. In other words, the crossbar arrays in Xuan implement the NeuADC, rather than operating upstream of, or separately from, an ADC. Because the crossbar arrays in Xuan are part of the ADC, they cannot also constitute a distinct analog preprocessing stage that precedes an ADC, as required by claim 1. Rather than teaching crossbar arrays that generate analog preprocessed sensing data prior to digitization, Xuan discloses crossbar arrays that are part of the digitization mechanism itself” (remarks, page 11).
Examiner respectfully disagrees. Applicant’s argument is not germane as according to MPEP 2145 VI, “Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims.” Also stated in MPEP 2111.01 II “Though understanding the claim language may be aided by explanation contained in the written description, it is important not to import into claim limitations that are not part of the claim” (1st paragraph). Additionally, MPEP 2111 states that “an examiner must construe claim terms in the broadest reasonable manner during prosecution as is reasonable allowed in an effort to establish a clear record of what applicant intends to claim” (4th paragraph). Examiner uses the broadest reasonable interpretation to interpret “one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data.”
Applicant argues, “Moreover, Xuan neither teaches nor suggests processing the analog signals generated by the image sensor by the crossbar arrays. The input Vin of the crossbar arrays in Xuan is not the analog signals provided by the image sensor. (See e.g., FIG. 13 and FIG. 15A-15B of Xuan). As such, Xuan does not teach or suggest "one or more crossbar arrays configured to process the analog sensing signals to generate analog preprocessed sensing data" and "an analog-to-digital converter (ADC) configured to convert the analog preprocessed sensing data into digital preprocessed sensing data," as recited in claim 1. (Emphasis added.)” (remarks page 11-12).
Examiner respectfully disagrees. Xuan teaches “RRAM crossbar arrays and inverter circuits are used at each layer to perform the basic NN operations (VMM and NAF) in the analog domain” where the input signal is an analog signal (col 22 line 7-28) and the “synthesizable comparators implemented with a three-input NAND gate are used in the output layer, since final digitalization of output has to be performed” (col 24 line 19-42) disclosing the crossbars process analog signals which are then converted to digital signals. Additionally, fig 2A -fig 2C depict an analog input and output to and from an image sensor and input to the NeuADC where the NeuADC framework includes RRAM crossbar architecture to facilitate VMM and NAF (Xuan col 6 line 10-15) therefore Xuan teaches processing the analog signals of the image sensor via the crossbar arrays.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim, U.S. Pub. NO. 2021/0365765 A1, teaches inputting pixel values of feature maps to a crossbar array in order to generate pixel values of an output feature map by selectively merging the output values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Denise R Karavias whose telephone number is (469)295-9152. The examiner can normally be reached 7:00 - 3:00 M-F.
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/DENISE R KARAVIAS/Examiner, Art Unit 2857
/MICHAEL J DALBO/Primary Examiner, Art Unit 2857