Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 01/26/2026 in response to the Office Action mailed on 10/30/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into fully
consideration all the amendments.
Response to Arguments
Applicant’s arguments, see page 6 of the remarks filed on 01/26/202, with respect to 112(b) rejection of Claims 17- have been fully considered and are persuasive. The rejection of Claims 17-19 has been withdrawn.
Applicant’s arguments, see page 6 of the remarks filed on 01/26/2025, with respect to the rejection of claim 1 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of previously applied prior art Sun et al., Lin et al. and newly found prior reference of Chang et al.. Chang et al. teaches the newly added limitation of amended Claim 1. i.e., Chang et al. teaches a microelectronic assembly, comprising a bridge die 10 (see Fig. 4: 10, paragraph 0040).
On pages 6-7 of the remarks filed on 01/26/2026, Applicant argues that the motivation provided to modify Sun in the previous office action is not related to the height of the pillars but related to the use of redundant pillars. Applicant further argues that Liu does mention height of pillars only in the context of minimizing standoffs between the chip and a substrate which is not applicable to Sun et al., as it teaches planar carriers unlike Lin which addresses uneven bases. These arguments are fully considered but are not persuasive. Firstly, the secondary reference of Lin was not relied upon to teach variations in height but to teach variations in thickness. Furthermore, according to MPEP § 2143.01, A “motivation to combine may be found explicitly or implicitly in market forces; design incentives; the ‘interrelated teachings of multiple patents’; ‘any need or problem known in the field of endeavor at the time of invention and addressed by the patent’; and the background knowledge, creativity, and common sense of the person of ordinary skill.” Zup v. Nash Mfg., 896 F.3d 1365, 1371, 127 USPQ2d 1423, 1427 (Fed. Cir. 2018) (quoting Plantronics, Inc. v. Aliph, Inc., 724 F.3d 1343, 1354 [107 USPQ2d 1706] (Fed. Cir. 2013) (citing Perfect Web Techs., Inc. v. InfoUSA, Inc., 587 F.3d 1324, 1328 [92 USPQ2d 1849] (Fed. Cir. 2009) (quoting KSR, 550 U.S. at 418-21)). As such, a person of ordinary skill in the art would have been motivated to combine the teachings of Sun et al. and Lin et al, in order to have conductive contacts with different thicknesses in the microelectronic assembly of Sun et al. Doing so would simultaneously optimize signal density, cost and space, something neither thick-contacts alone nor thin-contacts alone can achieve. Therefore, Sun and Lin are still relied upon to teach the limitations of Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US 20220270976 A1), in view of Chang et al. (US 20210210423 A1) and Lin et al. (US 20150171038 A1).
Regarding Claim 1, Sun et al. teaches a microelectronic assembly, comprising:
a substrate 183 having a surface 105 (see annotated Fig. 13: 183, 105 paragraph 0051),
the surface 105 including: a first conductive contact 109_1 having a first thickness t1; and a second conductive contact 109_2 having a second thickness t2 (see annotated Fig. 13: 109_1, 109_2, 105, t1, t2, paragraph 0049),
the second conductive contact 109_2 including a solder material 106 on a top surface of the second conductive contact 109_2 (see annotated Fig. 13: 106, 105, 109_2, paragraph 0049);
and a bridge component 175 embedded in a dielectric material of the substrate 183 and electrically coupled to the first and second conductive contacts 109_1, 109_2 at the surface 105 of the substrate 183 (see annotated Fig. 13: 175, 105, 109_1, 109_2, paragraph 0049).
Sun et al. fails to teach the bridge component 175 is a bridge die and the second thickness t2 different than the first thickness t1.
However, Chang et al. teaches a microelectronic assembly, comprising a bridge die 10 (see Fig. 4: 10, paragraph 0040).
Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the teachings of Sun et al. and Chang et al. in order to replace the bridge component of Sun et al. with the bridge die of Chang et al.. One of ordinary skill in the art would have been able to carry out such a substitution and achieve predictable results. Doing so would ensure higher performance and signal integrity.
Furthermore, Lin et al. teaches a microelectronic assembly, comprising a first conductive contact 22A having a first thickness T22A; and a second conductive contact 22D having a second thickness T22D different than the first thickness T22A (see Fig. 3C: 22A, T22A, Fig. 3D: 22D, T22D, paragraph 0040, 0043).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Sun et al. and Lin et al. in order to have the second thickness different than the first thickness. Doing so would enable the placement of a combination of thick and thin conductive contacts in various positions in order to simultaneously optimize signal density, cost and space, something neither type alone can achieve.
Regarding Claim 2, Lin et al. teaches the microelectronic assembly of claim 1, wherein the first thickness T22A is greater than the second thickness T22D (paragraph 0043) (H.
Regarding Claim 3, Lin et al. teaches the microelectronic assembly of claim 1, wherein the first thickness T22A is between 1 microns and 20 microns (see paragraph 0040).
Note that while Lin et al. fails to explicitly teach a thickness between 5 microns and 50 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 5 microns and 50 microns.
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Annotated Fig 13 of Sun et al. (US 20220270976 A1)
Regarding Claim 4, Lin et al. teaches the microelectronic assembly of claim 1, wherein the second thickness T22D is less than 5 microns (see paragraph 0043).
Note that while Lin et al. fails to explicitly teach a thickness between 2 microns and 35 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 2 microns and 35 microns.
Regarding Claim 5, Sun et al. et al. fails to teach the microelectronic assembly of claim 1, wherein the first conductive contact includes a first material on a top surface; and wherein the second conductive contact includes a second material between the solder material and the second conductive contact.
However, Lin et al. teaches wherein the first conductive contact 22A includes a first material 24A on a top surface; and wherein the second conductive contact 22D includes a second material 24D between the solder material 26D and the second conductive contact 22D (See Fig. 3C: 22A, 24A, Fig. 3D: 22D, 24D, 26D, paragraph 0040, 0043).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Sun et al. and Lin et al. in order to come up with the claimed invention. Doing so would prevent the diffusion of copper into the bonding material such as the solder alloy, as recognized by Lin et al. (paragraph 0041).
Regarding Claim 6, Lin et al. teaches the microelectronic assembly of claim 5, wherein the first material 24A includes gold, palladium, nickel, an organic surface protection layer, or a combination thereof (see paragraph 0041).
Regarding Claim 7, Lin et al. teaches the microelectronic assembly of claim 5, wherein the second material 24D includes nickel, cobalt, iron, or a combination thereof (see paragraph 0044).
Regarding Claim 8, Lin et al. teaches the microelectronic assembly of claim 5, wherein a thickness T24D of the second material 24D is between 0.5 micron and 3 microns.
Note that while Lin et al. fails to explicitly teach a thickness between 1 microns and 8 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 1 microns and 8 microns.
Regarding Claim 9, Sun et al. teaches the microelectronic assembly of claim 1, further comprising: a first microelectronic component 130-1 having a third conductive contact 132_1 electrically coupled, by a first interconnect 106, to the first conductive contact 109_1, wherein the first interconnect 106 includes solder; and a second microelectronic component 130-2 having a fourth conductive contact 132_2 electrically coupled, by a second interconnect 106, to the second conductive contact 109_2, wherein the second interconnect 106 includes solder (see annotated Fig. 13: 130-1, 130-2, 106, 132_2, 132_1, paragraph 0050).
Sun et al. fails to explicitly teach, wherein the solder of the first interconnect 106 having a thickness between 2 microns and 35 microns and wherein the solder of the second interconnect 106 having a thickness between 5 microns and 50 microns.
However, Lin et al. teaches wherein the first interconnect 26A includes solder having a thickness T26A between 2 microns and 7 microns and wherein the second interconnect 26D includes solder having a thickness T26D less than 10 microns (paragraph 0042, 0045).
Note that even though Lin et al. fails to explicitly teach the thickness T26A is between 2 microns and 35 microns and the thickness T26D between 5 microns and 50 microns, these thickness ranges overlap the disclosed ranges by Lin et al. According to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Sun et al. and Lin et al. in order to have the first interconnect include solder having a thickness between 2 microns and 35 microns the second interconnect 106 include solder having a thickness between 5 microns and 50 microns. Doing so would compensate for the difference in height between the first and second conductive contact ensuring proper alignment of microelectronic components.
Regarding Claim 10, Sun et al. teaches the microelectronic assembly of claim 9, wherein the surface 105 of the substrate 183 further includes a fifth conductive contact 109_3 and the first microelectronic component 130-1 is electrically coupled to the fifth conductive contact 109_3, and the microelectronic assembly further comprising: a conductive pillar 177 through the dielectric material of the substrate 183 and electrically coupled to the fifth conductive contact 109_3 (see annotated Fig. 13: 134_1, 177, 130-1, 183, 105, paragraph 0049).
Regarding Claim 11, Sun et al. teaches the microelectronic assembly of claim 1, wherein the surface 105 of the substrate 183 is a second surface 105, the substrate 183 further including a first surface 103 opposite the second surface 105, and the microelectronic assembly further including: a package substrate 102 electrically coupled to the second surface 103 of the substrate 183 (see annotated Fig. 13: 102, 103, 105, paragraph 0035, 0051).
Claims 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US 20220270976 A1), in view of Lin et al. (US 20150171038 A1).
Regarding Claim 12, Sun et al. teaches a microelectronic assembly, comprising:
a substrate 183 having a surface 105 (see annotated Fig. 13: 183, 105 paragraph 0051),
the surface 105 including: a first conductive contact 109_3 having a first thickness t1; and a second conductive contact 109_4 having a second thickness t2 (see annotated Fig. 13: 109_3, 109_4, 105, t1, t2, paragraph 0049),
a first microelectronic component 130-1 having a third conductive contact 134_1 electrically coupled, by a first interconnect 106, to the first conductive contact 109_3, wherein the first interconnect 109 includes solder (see annotated Fig. 13: 130-1, 106, 134_1, paragraph 0050);
and a second microelectronic component 130-2 having a fourth conductive contact 134_2 electrically coupled, by a second interconnect 106, to the second conductive contact 109_4, wherein the second interconnect 106 includes solder (see annotated Fig. 13: 130-2, 134_2, 106, paragraph 0050).
Sun et al. fails to teach the second thickness t2 is different than the first thickness t1, wherein the solder of the first interconnect 109 having a thickness between 2 microns and 35 microns, wherein the solder of the first interconnect 109 having a thickness between 5 microns and 50 microns.
However, Lin et al. teaches a microelectronic assembly, comprising a first conductive contact 22A having a first thickness T22A; and a second conductive contact 22D having a second thickness T22D different than the first thickness T22A (see Fig. 3C: 22A, T22A, Fig. 3D: 22D, T22D, paragraph 0040, 0043). Lin et al. further teaches wherein the first interconnect 26A includes solder having a thickness T26A between 2 microns and 7 microns and wherein the second interconnect 26D includes solder having a thickness T26D less than 10 microns (paragraph 0042, 0045).
Note that even though Lin et al. fails to explicitly teach the thickness T26A is between 2 microns and 35 microns and the thickness T26D between 5 microns and 50 microns, these thickness ranges overlap the disclosed ranges by Lin et al. According to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose the above thicknesses to be within the claimed ranges.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Sun et al. and Lin et al. in order to come up with the claimed invention. Doing so would enable the placement of a combination of thick and thin conductive contacts and interconnect structures in various positions in order to improve the symmetry, mechanical stability, additional thermal arrangement, or to optimize the interconnect structure thereby reducing inductance and enhancing speed, as recognized by Kim et al. (paragraph 0002).
Regarding Claim 13, Lin et al. teaches the microelectronic assembly of claim 12, wherein the first thickness T22A is between 1 microns and 20 microns (see paragraph 0040).
Note that while Lin et al. fails to explicitly teach a thickness between 5 microns and 50 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 5 microns and 50 microns.
Regarding Claim 14, Lin et al. teaches the microelectronic assembly of claim 12, wherein the second thickness T22D is less than 5 microns (see paragraph 0043).
Note that while Lin et al. fails to explicitly teach a thickness between 2 microns and 35 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 2 microns and 35 microns.
Regarding Claim 15, Sun et al. fails to teach the microelectronic assembly of claim 12, further comprising: a material between the second conductive contact and the solder of the second interconnect, wherein the material includes nickel, cobalt, iron, or a combination thereof.
However, Lin et al. teaches the microelectronic assembly further comprising: a material 24D between the second conductive contact 22D and the solder of the second interconnect 26D, wherein the material includes nickel, cobalt, iron, or a combination thereof (see Fig. 3D: 24D, 22D, 26D, paragraph 0044).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Sun et al. and Lin et al. in order to have a material between the second conductive contact and the solder of the second interconnect, wherein the material includes nickel, cobalt, iron, or a combination thereof. Doing so would prevent the diffusion of copper into the bonding material such as the solder alloy, as recognized by Lin et al. (paragraph 0041).
Regarding Claim 16, Sun et al. teaches the microelectronic assembly of claim 12, further comprising: a bridge component 177 embedded in a dielectric material of the substrate 183 and electrically coupled, by conductive pathways through the substrate 183, to the first and second conductive contacts 190_3, 190_4 at the surface 105 of the substrate 183 (see annotated Fig. 13: 109_3, 109_4, 177, 183, 105, paragraph 0049).
Regarding Claim 17, Sun et al. teaches a microelectronic assembly, comprising:
a substrate 183 having a surface 105 (see annotated Fig. 13: 183, 105 paragraph 0051),
the surface 105 including first conductive contacts 109_3 and second conductive contacts 109_4, wherein the first conductive contacts 109_3 have a first thickness t1 and the second conductive contacts 109_4 have a second thickness t2 (see annotated Fig. 13: 109_3, 109_4, 105, t1, t2, paragraph 0049);
a first microelectronic component 130-1 having third conductive contacts 134_1, wherein respective ones of the third conductive contacts 134_1 are coupled to respective ones of the first conductive contacts 190_3 by first interconnects 106 (see annotated Fig. 13: 130-1, 106, 134_1, paragraph 0050),
wherein the first interconnects 106 include solder (paragraph 0050);
and a second microelectronic component 130-2 having fourth conductive contacts 134_2, wherein respective ones of the fourth conductive contacts 134_2 are coupled to respective ones of the second conductive contacts 109_4 by second interconnects 106 (see annotated Fig. 13: 130-2, 106, 134_2, paragraph 0050),
wherein the second interconnects 106 include solder.
Sun et a. fails to teach the second thickness t2 is different than the first thickness t1, wherein the solder of the first interconnects 106 having a thickness between 2 microns and 35 microns, wherein the solder of the second interconnects 106 having a thickness between 5 microns and 50 microns.
However, Lin et al. teaches a microelectronic assembly, comprising first conductive contacts 22A having a first thickness T22A; and second conductive contacts 22D having a second thickness T22D different than the first thickness T22A (see Fig. 3C: 22A, T22A, Fig. 3D: 22D, T22D, paragraph 0040, 0043). Lin et al. further teaches wherein the first interconnects 26A include solder having a thickness T26A between 2 microns and 7 microns and wherein the second interconnects 26D includes solder having a thickness T26D less than 10 microns (paragraph 0042, 0045).
Note that even though Lin et al. fails to explicitly teach the thickness T26A is between 2 microns and 35 microns and the thickness T26D between 5 microns and 50 microns, these thickness ranges overlap the disclosed ranges by Lin et al. According to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose the above thicknesses to be within the claimed ranges.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Sun et al. and Lin et al. in order to come up with the claimed invention. Doing so would enable the placement of a combination of thick and thin conductive contacts and interconnect structures in various positions in order to improve the symmetry, mechanical stability, additional thermal arrangement, or to optimize the interconnect structure thereby reducing inductance and enhancing speed, as recognized by Kim et al. (paragraph 0002).
Regarding Claim 18, Lin et al. teaches the microelectronic assembly of claim 17, wherein the first thickness T22A is between 1 microns and 20 microns (see paragraph 0040).
Note that while Lin et al. fails to explicitly teach a thickness between 5 microns and 50 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 5 microns and 50 microns.
Regarding Claim 19, Lin et al. teaches the microelectronic assembly of claim 17, wherein the second thickness T22D is less than 5 microns (see paragraph 0043).
Note that while Lin et al. fails to explicitly teach a thickness between 2 microns and 35 microns, according to MPEP § 2144.05 (I), “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to choose a thickness between 2 microns and 35 microns.
Regarding Claim 20, Sun et al. teaches the microelectronic assembly of claim 17, further comprising: a surface insulation material 115 between the surface 105 of the substrate 183 and the first and second conductive contacts 190_3, 190_4 (see annotated Fig. 13: 115, paragraph 0050).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 03/27/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 7, 2026