DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-6 and 21-34 are pending in the application and are currently being examined. Claims 1 and 4-5 have been amended. Claims 7-20 have been canceled. Claims 12-20 (now canceled) have been withdrawn per the 11/19/2025 restriction election. New claims 21-34 have been added.
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections below.
Regarding the objections to the Abstract and Specification, the amendments are sufficient to overcome the objections. The Objections to the Abstract and Specification have thus been withdrawn.
Regarding the claim objection of 12/1/2025, as the claim in question has been canceled, the objection is now moot. The claim objection is withdrawn.
Regarding the 112 rejection of claim 7, as the claim in question has been canceled, the 112 rejection of independent claim 7 is now moot. This claim rejection is withdrawn.
Regarding the 112 rejection of claim 1. Examiner agrees the amendments overcome the 112 rejection of independent claim 1. This claim rejection is withdrawn.
Regarding the prior art rejections of claims 7-11, Examiner agrees they are deemed moot due to the cancellation of the claims in question. The prior art rejections of claims 7-11 are hereby withdrawn.
Regarding the newly added claims, Examiner respectfully disagrees with the assertation that these claims do not add new matter. Specifically newly added claim 27. Examiner is unsure how the referenced location of the specification teaches an n-FET stacked above a p-FET adjacent to a p-FET stacked above an n-FET, especially with the rest of the specification taken into consideration.
Claim Objections
Claims 24 and 32 objected to because of the following informalities: lines 3 and 5 of claim 24 both recite "of the first stacked nanosheet device the diffusion break". Both instances appear to be missing the word "and" before the diffusion break, which will be added in for the purposes of examination. Claim 32 appears to be incomplete. It is assumed that the "; and" at the end of the claim is to be a period, and will be treated as such for the purposes of examination. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 27 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Lines 1-3 recite “wherein the first stacked nanosheet device comprises a p-FET device stacked above an n-FET device, and the second stacked nanosheet device comprises an n-FET device stacked above a p-FET device”. It is unknown where the written description and drawings describe this limitation. The drawings show the method of forming the device and seem to depict both the first and second nanosheet device are a p-FET device stacked above an n-FET device, or an n-FET device stacked above a p-FET device. The written description also appears to teach the same as the figures.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 21-23, and 25-34 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hong et al. (US 2022/0302172 A1, hereafter Hong).
Regarding claim 1, Fig. 3B of Hong teaches semiconductor device comprising:
lower semiconductor channel layers (110, [0039]) vertically aligned and stacked one on top of another, the lower semiconductor channel layers (110) separated from each other by a gate stack material (115, [0040]) wrapping around the lower semiconductor channel layers (110); and
upper semiconductor channel layers (120, [0039]) vertically aligned and stacked one on top of another, the upper semiconductor channel layers (120) separated from each other by the gate stack material (125, [0040], Hong states that gate 115 and 125 may be different materials, meaning that they also may comprise the same material) wrapping around the upper semiconductor channel layers (120), the upper semiconductor channel layers (120) vertically aligned above the lower semiconductor channel layers (110);
a lower dielectric layer (single diffusion break, 300L, [0060]) adjacent to a first vertical side and a second vertical side (see annotated Fig. 3B) of the lower semiconductor channel layers (110), wherein the first vertical side and the second vertical side of the lower semiconductor channel layers (110) are on opposite sides of the lower semiconductor channel layers (110), wherein the lower dielectric layer (300L) comprises a first polarity stress on the lower semiconductor channel layers (110) (Hong states the stress or strain depends on if the adjacent FETs are PFETs or NFETs [0064]); and
an upper dielectric layer (single diffusion break, 300U, [0060]) adjacent to a first vertical side and a second vertical side (see annotated Fig. 3B) of the upper semiconductor channel layers (120), wherein the first vertical side and the second vertical side of the upper semiconductor channel layers (120) are on opposite sides of the upper semiconductor channel layers (120) and vertically aligned above the lower dielectric layer (300L), wherein the upper dielectric layer (300U) comprises a second polarity stress on the upper semiconductor channel layers (120) (Hong states the stress or strain depends on if the adjacent FETs are PFETs or NFETs [0064]), wherein the first polarity stress and the second polarity stress are opposite polarity stresses from each other [0064], and wherein the lower dielectric layer and the upper dielectric layer are two different materials (Hong teaches the diffusion breaks 300U and 300L comprise different materials [0064]).
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Regarding claim 2, Hong teaches the semiconductor device according to claim 1, wherein the first polarity stress comprises a tensile stress and the second polarity stress comprises a compressive stress. Hong discloses that the lower nanosheet transistor (LNT, [0041]) can be either a PFET or an NFET, and the upper nanosheet transistor (UNT, [0041]). If LNT is a PFET, the first polarity would be tensile as the diffusion break exerts a compressive stress on the PFET [0064], and if UNT is an NFET, the second polarity would be compressive as the diffusion break exerts a tensile stress on the NFET [0064].
Regarding claim 3, Hong teaches the semiconductor device according to claim 2. As the semiconductor device has a first polarity stress comprising a tensile stress and the second polarity stress comprising a compressive stress, it is inherent that the upper device (UNT, [0041]) is an NFET as it has the second polarity stress and the lower device (LNT, [0041]) is a PFET as it has the first polarity stress, as described in the rejection of claim 2.
Regarding claim 4, Hong teaches the semiconductor device according to claim 1. Hong further teaches the first polarity stress comprises a compressive stress and the second polarity stress comprises a tensile stress. Hong discloses that the lower nanosheet transistor (LNT, [0041]) can be either a PFET or an NFET, and the upper nanosheet transistor (UNT, [0041]). If LNT is an NFET, the first polarity would be compressive as the diffusion break exerts a tensile stress on the NFET [0064], and if UNT is an PFET, the second polarity would be tensile as the diffusion break exerts a compressive stress on the PFET [0064].
Regarding claim 6, Hong teaches the semiconductor device according to claim 1. Hong further teaches in Fig. 1B the lower dielectric layer (300L, [0060]) extends vertically into a substrate (105, [0005]) of the semiconductor device.
Regarding claim 21, Fig. 3B of Hong teaches a semiconductor device comprising:
a first stacked nanosheet device (100, [0035]) comprising upper channel layers (120, [0039]) vertically aligned above lower channel layers (110, [0039]);
a second stacked nanosheet device (200, [0035]) comprising upper channel layers (120) vertically aligned above lower channel layers (110); and
a diffusion break (single diffusion break, 300L and 300U, [0060]) arranged between the first stacked nanosheet device (100) and the second stacked nanosheet device (200), wherein the diffusion break comprises a first dielectric material (300U) entirely above a second dielectric material (300L), and wherein the first dielectric material (300U) is different than the second dielectric material (300L) [0064].
Regarding claim 22, Hong teaches the semiconductor device according to claim 21, further comprising:
a bottom dielectric isolation layer (131, [0038]) between and physically separating the first stacked nanosheet device (100, [0035]) and the second stacked nanosheet device (200, [0035]) from an underlying substrate (105, [0005]), wherein the diffusion break (300L and 300U, [0060]) extends through the bottom dielectric isolation layer (131), and wherein sidewalls of the second dielectric material (300L) directly contact sidewalls of the bottom dielectric isolation layer (131).
Regarding claim 23, Hong teaches the semiconductor device according to claim 21, further comprising:
a middle dielectric isolation layer (132, [0040]) between and physically separating the upper channel layers (120, [0039]) of the first stacked nanosheet device (100, [0035]) from the lower channel layers (110, [0039]) of the first stacked nanosheet device (100), wherein a bottommost surface of the first dielectric material (300L, [0060]) is below a topmost surface of the middle dielectric isolation layer (132).
Regarding claim 25, Hong teaches the semiconductor device according to claim 21, wherein the first stacked nanosheet device (100, [0035]) comprises a p-FET device stacked above an n-FET device, and the second stacked nanosheet device (200, [0035]) comprises a p-FET device stacked above an n-FET device [0041]. Hong states that each of the lower devices in LNT may be one of an NFET or a PFET, and the upper devices are the other. Meaning that if both the lower devices are an NFET, both the upper devices would be PFETs.
Regarding claim 26, Hong teaches the semiconductor device according to claim 21, wherein the first stacked nanosheet device (100, [0035]) comprises an n-FET device stacked above a p-FET device, and the second stacked nanosheet device (200, [0035]) comprises an n-FET device stacked above a p-FET device [0041]. Hong states that each of the lower devices in LNT may be one of an NFET or a PFET, and the upper devices are the other. Meaning that if both the lower devices are PFETs, both the upper devices would be NFETs.
Regarding claim 27, Hong teaches the semiconductor device according to claim 21, wherein the first stacked nanosheet device (100, [0035]) comprises a p-FET device stacked above an n-FET device, and the second stacked nanosheet device (200, [0035]) comprises an n-FET device stacked above a p-FET device [0041]. Hong states that each of the lower devices in LNT may be one of an NFET or a PFET, meaning the lower device of 100 can be a PFET and the lower device of 200 can be an NFET, and the upper devices are the opposite polarity, allowing for an NFET over a PFET in 100 and a PFET over an NFET in 200.
Regarding claim 28, Fig. 2B of Hong teaches a semiconductor device comprising:
a first region (see annotated Fig. 2B) comprising a first stacked nanosheet device (100, [0035]);
a second region (see annotated Fig. 2B) comprising a second stacked nanosheet device (200, [0035]); and
a third region (see annotated Fig. 2B) comprising a diffusion break (double diffusion break, 200L and 200U, [0052]), wherein the third region is between the first region and the second region, and wherein the diffusion break (200L and 200U) comprises a first dielectric material (200U) entirely above a second dielectric material (200L), and wherein the first dielectric material (200U) is different than the second dielectric material (200L) [0056].
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Regarding claim 29, Hong teaches the semiconductor device according to claim 28, wherein the third region (see annotated Fig. 2B) further comprises:
channel material layers (110 and 120, [0039]) directly contacting sidewalls of the diffusion break (200L and 200U, [0052]); and
inner spacers (132, [0040]) directly contacting sidewalls of the diffusion break (200L and 200U), wherein a width of each channel material layer (110 and 120) is substantially equal to a width of each inner spacer (132) measured in a direction parallel to a gate length (D1, [0006]).
Regarding claim 30, Hong teaches the semiconductor device according to claim 28, wherein the third region further comprises:
channel material layers (110 and 120, [0039]) directly contacting sidewalls of the diffusion break (200L and 200U, [0052]);
inner spacers (110S and 120S, [0054]) directly contacting sidewalls of the diffusion break (200L and 200U); and
middle dielectric material layers (132, [0040]) directly contacting sidewalls of the diffusion break (200L and 200U).
Regarding claim 31, Hong teaches the semiconductor device according to claim 28, wherein the third region further comprises:
middle dielectric isolation layers (132, [0040]) between and physically separating upper channel material layers (120, [0039]) from lower channel material layers (110, [0039]), wherein a bottommost surface the first dielectric material (200U, [0052]) is below a topmost surface of the middle dielectric isolation layers (132), and wherein a topmost surface of the second dielectric material (200L, [0052]) is above a bottommost surface of the middle dielectric isolation layers (132).
Regarding claim 32, Hong teaches the semiconductor device according to claim 28, further comprising:
a first source drain region (121/122 and 111/112, [0040]) between and separating the first region (see annotated Fig. 2B) from the third region (see annotated Fig. 2B); and
a second source drain region (121/122 and 111/112, [0040]) between and separating the third region from the second region (see annotated Fig. 2B).
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Regarding claim 33, Hong teaches the semiconductor device according to claim 28, wherein the first stacked nanosheet device (100, [0035]) comprises a p-FET device stacked above an n-FET device, and the second stacked nanosheet device (200, [0035]) comprises a p-FET device stacked above an n-FET device [0041]. Hong states that each of the lower devices in LNT may be one of an NFET or a PFET, and the upper devices are the other. Meaning that if both the lower devices are an NFET, both the upper devices would be PFETs.
Regarding claim 34, Hong teaches the semiconductor device according to claim 28, wherein the first stacked nanosheet device (100, [0035]) comprises an n-FET device stacked above a p-FET device, and the second stacked nanosheet device (200, [0035]) comprises an n-FET device stacked above a p-FET device [0041]. Hong states that each of the lower devices in LNT may be one of an NFET or a PFET, and the upper devices are the other. Meaning that if both the lower devices are PFETs, both the upper devices would be NFETs.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claim 1 above, in view of Lilak et al. (US 2020/0266218 A1, hereafter Lilak).
Regarding claim 5, Hong teaches the semiconductor device according to claim 1. Hong further teaches a lower source-drain region (111/112, [0040]) adjacent to the lower set of lower semiconductor channel layers (110, [0039]); and
an upper source-drain region (121/122, [0040]) adjacent to the upper set of upper semiconductor channel layers (120, [0039]) and vertically aligned above the lower source-drain region (111/112).
Hong is silent on the source drain regions specifically being epitaxy regions. One skilled in the art would know to form the source drain regions of Hong in a way well known in the art. Lilak teaches a similar device in Fig. 1B in which the lower source-drain region (118-1, [0020]) and source-drain region (118-2, [0020]) are both epitaxy structures [0020]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the source-drain regions of Hong to be epitaxy structures as taught by Lilak.
Regarding claim 24, Hong teaches the semiconductor device according to claim 21. Hong further teaches a lower source-drain (111/112, [0040]) between the lower channel layers (110, [0039]) of the first stacked nanosheet device (100, [0035]) and the diffusion break (300L and 300U, [0060]);
an upper source-drain between the upper channel layers (121/122, [0040]) of the first stacked nanosheet device (100, [0035]) and the diffusion break (300L and 300U, [0060]), wherein the upper source-drain (121/122) is above and vertically aligned with the lower source-drain (111/112); and
a dielectric layer (133, [0040]) between and separating the upper source-drain (121/122) from the lower source-drain (111/112).
Hong is silent on the source drain regions specifically being epitaxy regions. One skilled in the art would know to form the source drain regions of Hong in a way well known in the art. Lilak teaches a similar device in Fig. 1B in which the lower source-drain region (118-1, [0020]) and source-drain region (118-2, [0020]) are both epitaxy structures [0020]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the source-drain regions of Hong to be epitaxy structures as taught by Lilak.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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